2013-07-19 16:59:32 +00:00
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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2014-09-08 16:57:28 +00:00
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* Copyright (c) 2014 The Linux Foundation. All rights reserved.
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*
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2013-07-19 16:59:32 +00:00
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "adreno_gpu.h"
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#include "msm_gem.h"
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2013-11-16 17:56:06 +00:00
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#include "msm_mmu.h"
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2013-07-19 16:59:32 +00:00
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#define RB_SIZE SZ_32K
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#define RB_BLKSIZE 16
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int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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switch (param) {
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case MSM_PARAM_GPU_ID:
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*value = adreno_gpu->info->revn;
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return 0;
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case MSM_PARAM_GMEM_SIZE:
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2013-12-05 22:39:53 +00:00
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*value = adreno_gpu->gmem;
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2013-07-19 16:59:32 +00:00
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return 0;
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2014-02-04 19:16:04 +00:00
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case MSM_PARAM_CHIP_ID:
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*value = adreno_gpu->rev.patchid |
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(adreno_gpu->rev.minor << 8) |
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(adreno_gpu->rev.major << 16) |
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(adreno_gpu->rev.core << 24);
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return 0;
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2013-07-19 16:59:32 +00:00
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default:
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DBG("%s: invalid param: %u", gpu->name, param);
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return -EINVAL;
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}
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}
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#define rbmemptr(adreno_gpu, member) \
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((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member))
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int adreno_hw_init(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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2014-07-10 02:08:15 +00:00
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int ret;
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2013-07-19 16:59:32 +00:00
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DBG("%s", gpu->name);
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2014-07-11 15:59:22 +00:00
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ret = msm_gem_get_iova(gpu->rb->bo, gpu->id, &gpu->rb_iova);
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2014-07-10 02:08:15 +00:00
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if (ret) {
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gpu->rb_iova = 0;
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dev_err(gpu->dev->dev, "could not map ringbuffer: %d\n", ret);
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return ret;
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}
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2013-07-19 16:59:32 +00:00
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/* Setup REG_CP_RB_CNTL: */
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2014-09-08 16:57:28 +00:00
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adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
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2013-07-19 16:59:32 +00:00
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/* size is log2(quad-words): */
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AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
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2013-12-05 22:39:53 +00:00
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AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)));
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2013-07-19 16:59:32 +00:00
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/* Setup ringbuffer address: */
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2014-09-08 16:57:28 +00:00
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adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_BASE, gpu->rb_iova);
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adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
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rbmemptr(adreno_gpu, rptr));
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2013-07-19 16:59:32 +00:00
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/* Setup scratch/timestamp: */
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2014-09-08 16:57:28 +00:00
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adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_ADDR,
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rbmemptr(adreno_gpu, fence));
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2013-07-19 16:59:32 +00:00
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2014-09-08 16:57:28 +00:00
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adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_UMSK, 0x1);
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2013-07-19 16:59:32 +00:00
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return 0;
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}
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static uint32_t get_wptr(struct msm_ringbuffer *ring)
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{
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return ring->cur - ring->start;
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}
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uint32_t adreno_last_fence(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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return adreno_gpu->memptrs->fence;
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}
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2013-08-24 18:20:38 +00:00
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void adreno_recover(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct drm_device *dev = gpu->dev;
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int ret;
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gpu->funcs->pm_suspend(gpu);
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/* reset ringbuffer: */
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gpu->rb->cur = gpu->rb->start;
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/* reset completed fence seqno, just discard anything pending: */
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adreno_gpu->memptrs->fence = gpu->submitted_fence;
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2013-09-03 11:12:03 +00:00
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adreno_gpu->memptrs->rptr = 0;
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adreno_gpu->memptrs->wptr = 0;
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2013-08-24 18:20:38 +00:00
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gpu->funcs->pm_resume(gpu);
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ret = gpu->funcs->hw_init(gpu);
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if (ret) {
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dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
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/* hmm, oh well? */
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}
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}
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2013-07-19 16:59:32 +00:00
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int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
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struct msm_file_private *ctx)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct msm_drm_private *priv = gpu->dev->dev_private;
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struct msm_ringbuffer *ring = gpu->rb;
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unsigned i, ibs = 0;
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for (i = 0; i < submit->nr_cmds; i++) {
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switch (submit->cmd[i].type) {
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case MSM_SUBMIT_CMD_IB_TARGET_BUF:
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/* ignore IB-targets */
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break;
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case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
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/* ignore if there has not been a ctx switch: */
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if (priv->lastctx == ctx)
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break;
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case MSM_SUBMIT_CMD_BUF:
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OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2);
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OUT_RING(ring, submit->cmd[i].iova);
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OUT_RING(ring, submit->cmd[i].size);
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ibs++;
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break;
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}
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}
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/* on a320, at least, we seem to need to pad things out to an
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* even number of qwords to avoid issue w/ CP hanging on wrap-
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* around:
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*/
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if (ibs % 2)
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OUT_PKT2(ring);
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OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
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OUT_RING(ring, submit->fence);
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2014-09-08 19:40:16 +00:00
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if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) {
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2013-07-19 16:59:32 +00:00
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/* Flush HLSQ lazy updates to make sure there is nothing
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* pending for indirect loads after the timestamp has
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* passed:
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*/
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OUT_PKT3(ring, CP_EVENT_WRITE, 1);
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OUT_RING(ring, HLSQ_FLUSH);
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OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
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OUT_RING(ring, 0x00000000);
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}
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OUT_PKT3(ring, CP_EVENT_WRITE, 3);
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OUT_RING(ring, CACHE_FLUSH_TS);
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OUT_RING(ring, rbmemptr(adreno_gpu, fence));
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OUT_RING(ring, submit->fence);
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/* we could maybe be clever and only CP_COND_EXEC the interrupt: */
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OUT_PKT3(ring, CP_INTERRUPT, 1);
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OUT_RING(ring, 0x80000000);
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#if 0
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if (adreno_is_a3xx(adreno_gpu)) {
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/* Dummy set-constant to trigger context rollover */
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
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OUT_RING(ring, 0x00000000);
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}
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#endif
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gpu->funcs->flush(gpu);
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return 0;
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}
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void adreno_flush(struct msm_gpu *gpu)
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{
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2014-09-08 16:57:28 +00:00
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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2013-07-19 16:59:32 +00:00
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uint32_t wptr = get_wptr(gpu->rb);
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/* ensure writes to ringbuffer have hit system memory: */
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mb();
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2014-09-08 16:57:28 +00:00
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adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
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2013-07-19 16:59:32 +00:00
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}
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void adreno_idle(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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2014-01-11 21:11:59 +00:00
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uint32_t wptr = get_wptr(gpu->rb);
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2013-07-19 16:59:32 +00:00
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2014-01-11 21:11:59 +00:00
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/* wait for CP to drain ringbuffer: */
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if (spin_until(adreno_gpu->memptrs->rptr == wptr))
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DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name);
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2013-07-19 16:59:32 +00:00
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/* TODO maybe we need to reset GPU here to recover from hang? */
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}
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#ifdef CONFIG_DEBUG_FS
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void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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2014-09-05 19:05:38 +00:00
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int i;
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2013-07-19 16:59:32 +00:00
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seq_printf(m, "revision: %d (%d.%d.%d.%d)\n",
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adreno_gpu->info->revn, adreno_gpu->rev.core,
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adreno_gpu->rev.major, adreno_gpu->rev.minor,
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adreno_gpu->rev.patchid);
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seq_printf(m, "fence: %d/%d\n", adreno_gpu->memptrs->fence,
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2013-08-24 18:20:38 +00:00
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gpu->submitted_fence);
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2013-07-19 16:59:32 +00:00
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seq_printf(m, "rptr: %d\n", adreno_gpu->memptrs->rptr);
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seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr);
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seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb));
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2014-09-05 19:05:38 +00:00
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gpu->funcs->pm_resume(gpu);
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/* dump these out in a form that can be parsed by demsm: */
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seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name);
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for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
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uint32_t start = adreno_gpu->registers[i];
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uint32_t end = adreno_gpu->registers[i+1];
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uint32_t addr;
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for (addr = start; addr <= end; addr++) {
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uint32_t val = gpu_read(gpu, addr);
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seq_printf(m, "IO:R %08x %08x\n", addr<<2, val);
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}
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}
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gpu->funcs->pm_suspend(gpu);
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2013-07-19 16:59:32 +00:00
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}
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#endif
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2013-12-22 15:29:43 +00:00
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/* would be nice to not have to duplicate the _show() stuff with printk(): */
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void adreno_dump(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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2014-09-05 19:05:38 +00:00
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int i;
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2013-12-22 15:29:43 +00:00
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printk("revision: %d (%d.%d.%d.%d)\n",
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adreno_gpu->info->revn, adreno_gpu->rev.core,
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adreno_gpu->rev.major, adreno_gpu->rev.minor,
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adreno_gpu->rev.patchid);
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printk("fence: %d/%d\n", adreno_gpu->memptrs->fence,
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gpu->submitted_fence);
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printk("rptr: %d\n", adreno_gpu->memptrs->rptr);
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printk("wptr: %d\n", adreno_gpu->memptrs->wptr);
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printk("rb wptr: %d\n", get_wptr(gpu->rb));
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2014-09-05 19:05:38 +00:00
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/* dump these out in a form that can be parsed by demsm: */
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printk("IO:region %s 00000000 00020000\n", gpu->name);
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for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
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uint32_t start = adreno_gpu->registers[i];
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uint32_t end = adreno_gpu->registers[i+1];
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uint32_t addr;
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for (addr = start; addr <= end; addr++) {
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uint32_t val = gpu_read(gpu, addr);
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printk("IO:R %08x %08x\n", addr<<2, val);
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}
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}
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2013-12-22 15:29:43 +00:00
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}
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2014-01-11 21:11:59 +00:00
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static uint32_t ring_freewords(struct msm_gpu *gpu)
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2013-07-19 16:59:32 +00:00
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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2014-01-11 21:11:59 +00:00
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uint32_t size = gpu->rb->size / 4;
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uint32_t wptr = get_wptr(gpu->rb);
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uint32_t rptr = adreno_gpu->memptrs->rptr;
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return (rptr + (size - 1) - wptr) % size;
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}
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void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords)
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{
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if (spin_until(ring_freewords(gpu) >= ndwords))
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DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name);
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2013-07-19 16:59:32 +00:00
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}
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static const char *iommu_ports[] = {
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"gfx3d_user", "gfx3d_priv",
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"gfx3d1_user", "gfx3d1_priv",
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};
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int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
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2014-09-05 19:03:40 +00:00
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struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs)
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2013-07-19 16:59:32 +00:00
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{
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2014-09-05 19:03:40 +00:00
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struct adreno_platform_config *config = pdev->dev.platform_data;
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struct msm_gpu *gpu = &adreno_gpu->base;
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2013-11-16 17:56:06 +00:00
|
|
|
struct msm_mmu *mmu;
|
2014-09-05 17:30:27 +00:00
|
|
|
int ret;
|
2013-07-19 16:59:32 +00:00
|
|
|
|
2014-09-05 19:03:40 +00:00
|
|
|
adreno_gpu->funcs = funcs;
|
|
|
|
adreno_gpu->info = adreno_info(config->rev);
|
|
|
|
adreno_gpu->gmem = adreno_gpu->info->gmem;
|
|
|
|
adreno_gpu->revn = adreno_gpu->info->revn;
|
|
|
|
adreno_gpu->rev = config->rev;
|
|
|
|
|
|
|
|
gpu->fast_rate = config->fast_rate;
|
|
|
|
gpu->slow_rate = config->slow_rate;
|
|
|
|
gpu->bus_freq = config->bus_freq;
|
|
|
|
#ifdef CONFIG_MSM_BUS_SCALING
|
|
|
|
gpu->bus_scale_table = config->bus_scale_table;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
|
|
|
|
gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
|
2013-07-19 16:59:32 +00:00
|
|
|
|
2014-10-31 15:50:55 +00:00
|
|
|
ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
|
|
|
|
adreno_gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq",
|
|
|
|
RB_SIZE);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2014-09-05 19:03:40 +00:00
|
|
|
ret = request_firmware(&adreno_gpu->pm4, adreno_gpu->info->pm4fw, drm->dev);
|
2013-07-19 16:59:32 +00:00
|
|
|
if (ret) {
|
|
|
|
dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n",
|
2014-09-05 19:03:40 +00:00
|
|
|
adreno_gpu->info->pm4fw, ret);
|
2013-07-19 16:59:32 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-09-05 19:03:40 +00:00
|
|
|
ret = request_firmware(&adreno_gpu->pfp, adreno_gpu->info->pfpfw, drm->dev);
|
2013-07-19 16:59:32 +00:00
|
|
|
if (ret) {
|
|
|
|
dev_err(drm->dev, "failed to load %s PFP firmware: %d\n",
|
2014-09-05 19:03:40 +00:00
|
|
|
adreno_gpu->info->pfpfw, ret);
|
2013-07-19 16:59:32 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-09-05 19:03:40 +00:00
|
|
|
mmu = gpu->mmu;
|
2013-11-16 17:56:06 +00:00
|
|
|
if (mmu) {
|
|
|
|
ret = mmu->funcs->attach(mmu, iommu_ports,
|
|
|
|
ARRAY_SIZE(iommu_ports));
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2013-07-19 16:59:32 +00:00
|
|
|
|
2014-07-11 15:59:22 +00:00
|
|
|
mutex_lock(&drm->struct_mutex);
|
2014-09-05 19:03:40 +00:00
|
|
|
adreno_gpu->memptrs_bo = msm_gem_new(drm, sizeof(*adreno_gpu->memptrs),
|
2013-07-19 16:59:32 +00:00
|
|
|
MSM_BO_UNCACHED);
|
2014-07-11 15:59:22 +00:00
|
|
|
mutex_unlock(&drm->struct_mutex);
|
2014-09-05 19:03:40 +00:00
|
|
|
if (IS_ERR(adreno_gpu->memptrs_bo)) {
|
|
|
|
ret = PTR_ERR(adreno_gpu->memptrs_bo);
|
|
|
|
adreno_gpu->memptrs_bo = NULL;
|
2013-07-19 16:59:32 +00:00
|
|
|
dev_err(drm->dev, "could not allocate memptrs: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-09-05 19:03:40 +00:00
|
|
|
adreno_gpu->memptrs = msm_gem_vaddr(adreno_gpu->memptrs_bo);
|
|
|
|
if (!adreno_gpu->memptrs) {
|
2013-07-19 16:59:32 +00:00
|
|
|
dev_err(drm->dev, "could not vmap memptrs\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2014-09-05 19:03:40 +00:00
|
|
|
ret = msm_gem_get_iova(adreno_gpu->memptrs_bo, gpu->id,
|
|
|
|
&adreno_gpu->memptrs_iova);
|
2013-07-19 16:59:32 +00:00
|
|
|
if (ret) {
|
|
|
|
dev_err(drm->dev, "could not map memptrs: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void adreno_gpu_cleanup(struct adreno_gpu *gpu)
|
|
|
|
{
|
|
|
|
if (gpu->memptrs_bo) {
|
|
|
|
if (gpu->memptrs_iova)
|
|
|
|
msm_gem_put_iova(gpu->memptrs_bo, gpu->base.id);
|
2015-05-15 13:19:36 +00:00
|
|
|
drm_gem_object_unreference_unlocked(gpu->memptrs_bo);
|
2013-07-19 16:59:32 +00:00
|
|
|
}
|
2014-11-25 12:44:20 +00:00
|
|
|
release_firmware(gpu->pm4);
|
|
|
|
release_firmware(gpu->pfp);
|
2013-07-19 16:59:32 +00:00
|
|
|
msm_gpu_cleanup(&gpu->base);
|
|
|
|
}
|