2010-02-02 19:25:44 +00:00
|
|
|
#undef DEBUG
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ARM performance counter support.
|
|
|
|
*
|
|
|
|
* Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
|
2010-11-13 19:04:32 +00:00
|
|
|
* Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
|
2010-01-26 17:51:05 +00:00
|
|
|
*
|
2010-02-02 19:25:44 +00:00
|
|
|
* This code is based on the sparc64 perf event code, which is in turn based
|
2014-09-29 16:15:32 +00:00
|
|
|
* on the x86 code.
|
2010-02-02 19:25:44 +00:00
|
|
|
*/
|
|
|
|
#define pr_fmt(fmt) "hw perfevents: " fmt
|
|
|
|
|
2015-05-26 16:23:39 +00:00
|
|
|
#include <linux/bitmap.h>
|
2015-05-13 16:12:25 +00:00
|
|
|
#include <linux/cpumask.h>
|
2016-02-23 18:22:39 +00:00
|
|
|
#include <linux/cpu_pm.h>
|
2015-05-26 16:23:39 +00:00
|
|
|
#include <linux/export.h>
|
2010-02-02 19:25:44 +00:00
|
|
|
#include <linux/kernel.h>
|
2015-07-06 11:23:53 +00:00
|
|
|
#include <linux/perf/arm_pmu.h>
|
2015-05-26 16:23:39 +00:00
|
|
|
#include <linux/slab.h>
|
2017-02-01 15:36:40 +00:00
|
|
|
#include <linux/sched/clock.h>
|
2015-05-26 16:23:39 +00:00
|
|
|
#include <linux/spinlock.h>
|
2014-02-07 21:01:19 +00:00
|
|
|
#include <linux/irq.h>
|
|
|
|
#include <linux/irqdesc.h>
|
2010-02-02 19:25:44 +00:00
|
|
|
|
|
|
|
#include <asm/irq_regs.h>
|
|
|
|
|
2017-12-12 16:56:06 +00:00
|
|
|
static DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu);
|
|
|
|
static DEFINE_PER_CPU(int, cpu_irq);
|
|
|
|
|
2010-02-02 19:25:44 +00:00
|
|
|
static int
|
2011-04-28 14:47:10 +00:00
|
|
|
armpmu_map_cache_event(const unsigned (*cache_map)
|
|
|
|
[PERF_COUNT_HW_CACHE_MAX]
|
|
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX],
|
|
|
|
u64 config)
|
2010-02-02 19:25:44 +00:00
|
|
|
{
|
|
|
|
unsigned int cache_type, cache_op, cache_result, ret;
|
|
|
|
|
|
|
|
cache_type = (config >> 0) & 0xff;
|
|
|
|
if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
cache_op = (config >> 8) & 0xff;
|
|
|
|
if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
cache_result = (config >> 16) & 0xff;
|
|
|
|
if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2017-08-08 15:58:33 +00:00
|
|
|
if (!cache_map)
|
|
|
|
return -ENOENT;
|
|
|
|
|
2011-04-28 14:47:10 +00:00
|
|
|
ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
|
2010-02-02 19:25:44 +00:00
|
|
|
|
|
|
|
if (ret == CACHE_OP_UNSUPPORTED)
|
|
|
|
return -ENOENT;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-11-13 17:13:56 +00:00
|
|
|
static int
|
2012-07-29 11:36:28 +00:00
|
|
|
armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
|
2010-11-13 17:13:56 +00:00
|
|
|
{
|
2013-08-08 17:41:59 +00:00
|
|
|
int mapping;
|
|
|
|
|
|
|
|
if (config >= PERF_COUNT_HW_MAX)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2017-08-08 15:58:33 +00:00
|
|
|
if (!event_map)
|
|
|
|
return -ENOENT;
|
|
|
|
|
2013-08-08 17:41:59 +00:00
|
|
|
mapping = (*event_map)[config];
|
2011-04-28 14:47:10 +00:00
|
|
|
return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
|
2010-11-13 17:13:56 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2011-04-28 14:47:10 +00:00
|
|
|
armpmu_map_raw_event(u32 raw_event_mask, u64 config)
|
2010-11-13 17:13:56 +00:00
|
|
|
{
|
2011-04-28 14:47:10 +00:00
|
|
|
return (int)(config & raw_event_mask);
|
|
|
|
}
|
|
|
|
|
2012-07-29 11:36:28 +00:00
|
|
|
int
|
|
|
|
armpmu_map_event(struct perf_event *event,
|
|
|
|
const unsigned (*event_map)[PERF_COUNT_HW_MAX],
|
|
|
|
const unsigned (*cache_map)
|
|
|
|
[PERF_COUNT_HW_CACHE_MAX]
|
|
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX],
|
|
|
|
u32 raw_event_mask)
|
2011-04-28 14:47:10 +00:00
|
|
|
{
|
|
|
|
u64 config = event->attr.config;
|
2012-09-12 09:53:23 +00:00
|
|
|
int type = event->attr.type;
|
2011-04-28 14:47:10 +00:00
|
|
|
|
2012-09-12 09:53:23 +00:00
|
|
|
if (type == event->pmu->type)
|
|
|
|
return armpmu_map_raw_event(raw_event_mask, config);
|
|
|
|
|
|
|
|
switch (type) {
|
2011-04-28 14:47:10 +00:00
|
|
|
case PERF_TYPE_HARDWARE:
|
2012-07-29 11:36:28 +00:00
|
|
|
return armpmu_map_hw_event(event_map, config);
|
2011-04-28 14:47:10 +00:00
|
|
|
case PERF_TYPE_HW_CACHE:
|
|
|
|
return armpmu_map_cache_event(cache_map, config);
|
|
|
|
case PERF_TYPE_RAW:
|
|
|
|
return armpmu_map_raw_event(raw_event_mask, config);
|
|
|
|
}
|
|
|
|
|
|
|
|
return -ENOENT;
|
2010-11-13 17:13:56 +00:00
|
|
|
}
|
|
|
|
|
2012-07-30 11:00:02 +00:00
|
|
|
int armpmu_event_set_period(struct perf_event *event)
|
2010-02-02 19:25:44 +00:00
|
|
|
{
|
2011-04-28 15:27:54 +00:00
|
|
|
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
|
2012-07-30 11:00:02 +00:00
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
2010-05-21 12:43:08 +00:00
|
|
|
s64 left = local64_read(&hwc->period_left);
|
2010-02-02 19:25:44 +00:00
|
|
|
s64 period = hwc->sample_period;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
if (unlikely(left <= -period)) {
|
|
|
|
left = period;
|
2010-05-21 12:43:08 +00:00
|
|
|
local64_set(&hwc->period_left, left);
|
2010-02-02 19:25:44 +00:00
|
|
|
hwc->last_period = period;
|
|
|
|
ret = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (unlikely(left <= 0)) {
|
|
|
|
left += period;
|
2010-05-21 12:43:08 +00:00
|
|
|
local64_set(&hwc->period_left, left);
|
2010-02-02 19:25:44 +00:00
|
|
|
hwc->last_period = period;
|
|
|
|
ret = 1;
|
|
|
|
}
|
|
|
|
|
2015-01-05 14:58:54 +00:00
|
|
|
/*
|
|
|
|
* Limit the maximum period to prevent the counter value
|
|
|
|
* from overtaking the one we are about to program. In
|
|
|
|
* effect we are reducing max_period to account for
|
|
|
|
* interrupt latency (and we are being very conservative).
|
|
|
|
*/
|
|
|
|
if (left > (armpmu->max_period >> 1))
|
|
|
|
left = armpmu->max_period >> 1;
|
2010-02-02 19:25:44 +00:00
|
|
|
|
2010-05-21 12:43:08 +00:00
|
|
|
local64_set(&hwc->prev_count, (u64)-left);
|
2010-02-02 19:25:44 +00:00
|
|
|
|
2012-07-30 11:00:02 +00:00
|
|
|
armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
|
2010-02-02 19:25:44 +00:00
|
|
|
|
|
|
|
perf_event_update_userpage(event);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-07-30 11:00:02 +00:00
|
|
|
u64 armpmu_event_update(struct perf_event *event)
|
2010-02-02 19:25:44 +00:00
|
|
|
{
|
2011-04-28 15:27:54 +00:00
|
|
|
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
|
2012-07-30 11:00:02 +00:00
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
2011-03-25 16:12:37 +00:00
|
|
|
u64 delta, prev_raw_count, new_raw_count;
|
2010-02-02 19:25:44 +00:00
|
|
|
|
|
|
|
again:
|
2010-05-21 12:43:08 +00:00
|
|
|
prev_raw_count = local64_read(&hwc->prev_count);
|
2012-07-30 11:00:02 +00:00
|
|
|
new_raw_count = armpmu->read_counter(event);
|
2010-02-02 19:25:44 +00:00
|
|
|
|
2010-05-21 12:43:08 +00:00
|
|
|
if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
|
2010-02-02 19:25:44 +00:00
|
|
|
new_raw_count) != prev_raw_count)
|
|
|
|
goto again;
|
|
|
|
|
2012-03-06 16:33:17 +00:00
|
|
|
delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
|
2010-02-02 19:25:44 +00:00
|
|
|
|
2010-05-21 12:43:08 +00:00
|
|
|
local64_add(delta, &event->count);
|
|
|
|
local64_sub(delta, &hwc->period_left);
|
2010-02-02 19:25:44 +00:00
|
|
|
|
|
|
|
return new_raw_count;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
perf: Rework the PMU methods
Replace pmu::{enable,disable,start,stop,unthrottle} with
pmu::{add,del,start,stop}, all of which take a flags argument.
The new interface extends the capability to stop a counter while
keeping it scheduled on the PMU. We replace the throttled state with
the generic stopped state.
This also allows us to efficiently stop/start counters over certain
code paths (like IRQ handlers).
It also allows scheduling a counter without it starting, allowing for
a generic frozen state (useful for rotating stopped counters).
The stopped state is implemented in two different ways, depending on
how the architecture implemented the throttled state:
1) We disable the counter:
a) the pmu has per-counter enable bits, we flip that
b) we program a NOP event, preserving the counter state
2) We store the counter state and ignore all read/overflow events
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: paulus <paulus@samba.org>
Cc: stephane eranian <eranian@googlemail.com>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Yanmin <yanmin_zhang@linux.intel.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Cc: David Miller <davem@davemloft.net>
Cc: Michael Cree <mcree@orcon.net.nz>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-06-16 12:37:10 +00:00
|
|
|
armpmu_read(struct perf_event *event)
|
2010-02-02 19:25:44 +00:00
|
|
|
{
|
2012-07-30 11:00:02 +00:00
|
|
|
armpmu_event_update(event);
|
2010-02-02 19:25:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
perf: Rework the PMU methods
Replace pmu::{enable,disable,start,stop,unthrottle} with
pmu::{add,del,start,stop}, all of which take a flags argument.
The new interface extends the capability to stop a counter while
keeping it scheduled on the PMU. We replace the throttled state with
the generic stopped state.
This also allows us to efficiently stop/start counters over certain
code paths (like IRQ handlers).
It also allows scheduling a counter without it starting, allowing for
a generic frozen state (useful for rotating stopped counters).
The stopped state is implemented in two different ways, depending on
how the architecture implemented the throttled state:
1) We disable the counter:
a) the pmu has per-counter enable bits, we flip that
b) we program a NOP event, preserving the counter state
2) We store the counter state and ignore all read/overflow events
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: paulus <paulus@samba.org>
Cc: stephane eranian <eranian@googlemail.com>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Yanmin <yanmin_zhang@linux.intel.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Cc: David Miller <davem@davemloft.net>
Cc: Michael Cree <mcree@orcon.net.nz>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-06-16 12:37:10 +00:00
|
|
|
armpmu_stop(struct perf_event *event, int flags)
|
2010-02-02 19:25:44 +00:00
|
|
|
{
|
2011-04-28 15:27:54 +00:00
|
|
|
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
|
2010-02-02 19:25:44 +00:00
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
|
perf: Rework the PMU methods
Replace pmu::{enable,disable,start,stop,unthrottle} with
pmu::{add,del,start,stop}, all of which take a flags argument.
The new interface extends the capability to stop a counter while
keeping it scheduled on the PMU. We replace the throttled state with
the generic stopped state.
This also allows us to efficiently stop/start counters over certain
code paths (like IRQ handlers).
It also allows scheduling a counter without it starting, allowing for
a generic frozen state (useful for rotating stopped counters).
The stopped state is implemented in two different ways, depending on
how the architecture implemented the throttled state:
1) We disable the counter:
a) the pmu has per-counter enable bits, we flip that
b) we program a NOP event, preserving the counter state
2) We store the counter state and ignore all read/overflow events
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: paulus <paulus@samba.org>
Cc: stephane eranian <eranian@googlemail.com>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Yanmin <yanmin_zhang@linux.intel.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Cc: David Miller <davem@davemloft.net>
Cc: Michael Cree <mcree@orcon.net.nz>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-06-16 12:37:10 +00:00
|
|
|
/*
|
|
|
|
* ARM pmu always has to update the counter, so ignore
|
|
|
|
* PERF_EF_UPDATE, see comments in armpmu_start().
|
|
|
|
*/
|
|
|
|
if (!(hwc->state & PERF_HES_STOPPED)) {
|
2012-07-30 11:00:02 +00:00
|
|
|
armpmu->disable(event);
|
|
|
|
armpmu_event_update(event);
|
perf: Rework the PMU methods
Replace pmu::{enable,disable,start,stop,unthrottle} with
pmu::{add,del,start,stop}, all of which take a flags argument.
The new interface extends the capability to stop a counter while
keeping it scheduled on the PMU. We replace the throttled state with
the generic stopped state.
This also allows us to efficiently stop/start counters over certain
code paths (like IRQ handlers).
It also allows scheduling a counter without it starting, allowing for
a generic frozen state (useful for rotating stopped counters).
The stopped state is implemented in two different ways, depending on
how the architecture implemented the throttled state:
1) We disable the counter:
a) the pmu has per-counter enable bits, we flip that
b) we program a NOP event, preserving the counter state
2) We store the counter state and ignore all read/overflow events
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: paulus <paulus@samba.org>
Cc: stephane eranian <eranian@googlemail.com>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Yanmin <yanmin_zhang@linux.intel.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Cc: David Miller <davem@davemloft.net>
Cc: Michael Cree <mcree@orcon.net.nz>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-06-16 12:37:10 +00:00
|
|
|
hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
|
|
|
|
}
|
2010-02-02 19:25:44 +00:00
|
|
|
}
|
|
|
|
|
2012-07-30 11:00:02 +00:00
|
|
|
static void armpmu_start(struct perf_event *event, int flags)
|
2010-02-02 19:25:44 +00:00
|
|
|
{
|
2011-04-28 15:27:54 +00:00
|
|
|
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
|
2010-02-02 19:25:44 +00:00
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
|
perf: Rework the PMU methods
Replace pmu::{enable,disable,start,stop,unthrottle} with
pmu::{add,del,start,stop}, all of which take a flags argument.
The new interface extends the capability to stop a counter while
keeping it scheduled on the PMU. We replace the throttled state with
the generic stopped state.
This also allows us to efficiently stop/start counters over certain
code paths (like IRQ handlers).
It also allows scheduling a counter without it starting, allowing for
a generic frozen state (useful for rotating stopped counters).
The stopped state is implemented in two different ways, depending on
how the architecture implemented the throttled state:
1) We disable the counter:
a) the pmu has per-counter enable bits, we flip that
b) we program a NOP event, preserving the counter state
2) We store the counter state and ignore all read/overflow events
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: paulus <paulus@samba.org>
Cc: stephane eranian <eranian@googlemail.com>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Yanmin <yanmin_zhang@linux.intel.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Cc: David Miller <davem@davemloft.net>
Cc: Michael Cree <mcree@orcon.net.nz>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-06-16 12:37:10 +00:00
|
|
|
/*
|
|
|
|
* ARM pmu always has to reprogram the period, so ignore
|
|
|
|
* PERF_EF_RELOAD, see the comment below.
|
|
|
|
*/
|
|
|
|
if (flags & PERF_EF_RELOAD)
|
|
|
|
WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
|
|
|
|
|
|
|
|
hwc->state = 0;
|
2010-02-02 19:25:44 +00:00
|
|
|
/*
|
|
|
|
* Set the period again. Some counters can't be stopped, so when we
|
perf: Rework the PMU methods
Replace pmu::{enable,disable,start,stop,unthrottle} with
pmu::{add,del,start,stop}, all of which take a flags argument.
The new interface extends the capability to stop a counter while
keeping it scheduled on the PMU. We replace the throttled state with
the generic stopped state.
This also allows us to efficiently stop/start counters over certain
code paths (like IRQ handlers).
It also allows scheduling a counter without it starting, allowing for
a generic frozen state (useful for rotating stopped counters).
The stopped state is implemented in two different ways, depending on
how the architecture implemented the throttled state:
1) We disable the counter:
a) the pmu has per-counter enable bits, we flip that
b) we program a NOP event, preserving the counter state
2) We store the counter state and ignore all read/overflow events
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: paulus <paulus@samba.org>
Cc: stephane eranian <eranian@googlemail.com>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Yanmin <yanmin_zhang@linux.intel.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Cc: David Miller <davem@davemloft.net>
Cc: Michael Cree <mcree@orcon.net.nz>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-06-16 12:37:10 +00:00
|
|
|
* were stopped we simply disabled the IRQ source and the counter
|
2010-02-02 19:25:44 +00:00
|
|
|
* may have been left counting. If we don't do this step then we may
|
|
|
|
* get an interrupt too soon or *way* too late if the overflow has
|
|
|
|
* happened since disabling.
|
|
|
|
*/
|
2012-07-30 11:00:02 +00:00
|
|
|
armpmu_event_set_period(event);
|
|
|
|
armpmu->enable(event);
|
2010-02-02 19:25:44 +00:00
|
|
|
}
|
|
|
|
|
perf: Rework the PMU methods
Replace pmu::{enable,disable,start,stop,unthrottle} with
pmu::{add,del,start,stop}, all of which take a flags argument.
The new interface extends the capability to stop a counter while
keeping it scheduled on the PMU. We replace the throttled state with
the generic stopped state.
This also allows us to efficiently stop/start counters over certain
code paths (like IRQ handlers).
It also allows scheduling a counter without it starting, allowing for
a generic frozen state (useful for rotating stopped counters).
The stopped state is implemented in two different ways, depending on
how the architecture implemented the throttled state:
1) We disable the counter:
a) the pmu has per-counter enable bits, we flip that
b) we program a NOP event, preserving the counter state
2) We store the counter state and ignore all read/overflow events
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: paulus <paulus@samba.org>
Cc: stephane eranian <eranian@googlemail.com>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Yanmin <yanmin_zhang@linux.intel.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Cc: David Miller <davem@davemloft.net>
Cc: Michael Cree <mcree@orcon.net.nz>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-06-16 12:37:10 +00:00
|
|
|
static void
|
|
|
|
armpmu_del(struct perf_event *event, int flags)
|
|
|
|
{
|
2011-04-28 15:27:54 +00:00
|
|
|
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
|
2014-05-13 18:36:31 +00:00
|
|
|
struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
|
perf: Rework the PMU methods
Replace pmu::{enable,disable,start,stop,unthrottle} with
pmu::{add,del,start,stop}, all of which take a flags argument.
The new interface extends the capability to stop a counter while
keeping it scheduled on the PMU. We replace the throttled state with
the generic stopped state.
This also allows us to efficiently stop/start counters over certain
code paths (like IRQ handlers).
It also allows scheduling a counter without it starting, allowing for
a generic frozen state (useful for rotating stopped counters).
The stopped state is implemented in two different ways, depending on
how the architecture implemented the throttled state:
1) We disable the counter:
a) the pmu has per-counter enable bits, we flip that
b) we program a NOP event, preserving the counter state
2) We store the counter state and ignore all read/overflow events
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: paulus <paulus@samba.org>
Cc: stephane eranian <eranian@googlemail.com>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Yanmin <yanmin_zhang@linux.intel.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Cc: David Miller <davem@davemloft.net>
Cc: Michael Cree <mcree@orcon.net.nz>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-06-16 12:37:10 +00:00
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
int idx = hwc->idx;
|
|
|
|
|
|
|
|
armpmu_stop(event, PERF_EF_UPDATE);
|
2011-05-17 10:20:11 +00:00
|
|
|
hw_events->events[idx] = NULL;
|
|
|
|
clear_bit(idx, hw_events->used_mask);
|
2014-02-07 21:01:22 +00:00
|
|
|
if (armpmu->clear_event_idx)
|
|
|
|
armpmu->clear_event_idx(hw_events, event);
|
perf: Rework the PMU methods
Replace pmu::{enable,disable,start,stop,unthrottle} with
pmu::{add,del,start,stop}, all of which take a flags argument.
The new interface extends the capability to stop a counter while
keeping it scheduled on the PMU. We replace the throttled state with
the generic stopped state.
This also allows us to efficiently stop/start counters over certain
code paths (like IRQ handlers).
It also allows scheduling a counter without it starting, allowing for
a generic frozen state (useful for rotating stopped counters).
The stopped state is implemented in two different ways, depending on
how the architecture implemented the throttled state:
1) We disable the counter:
a) the pmu has per-counter enable bits, we flip that
b) we program a NOP event, preserving the counter state
2) We store the counter state and ignore all read/overflow events
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: paulus <paulus@samba.org>
Cc: stephane eranian <eranian@googlemail.com>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Yanmin <yanmin_zhang@linux.intel.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Cc: David Miller <davem@davemloft.net>
Cc: Michael Cree <mcree@orcon.net.nz>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-06-16 12:37:10 +00:00
|
|
|
|
|
|
|
perf_event_update_userpage(event);
|
|
|
|
}
|
|
|
|
|
2010-02-02 19:25:44 +00:00
|
|
|
static int
|
perf: Rework the PMU methods
Replace pmu::{enable,disable,start,stop,unthrottle} with
pmu::{add,del,start,stop}, all of which take a flags argument.
The new interface extends the capability to stop a counter while
keeping it scheduled on the PMU. We replace the throttled state with
the generic stopped state.
This also allows us to efficiently stop/start counters over certain
code paths (like IRQ handlers).
It also allows scheduling a counter without it starting, allowing for
a generic frozen state (useful for rotating stopped counters).
The stopped state is implemented in two different ways, depending on
how the architecture implemented the throttled state:
1) We disable the counter:
a) the pmu has per-counter enable bits, we flip that
b) we program a NOP event, preserving the counter state
2) We store the counter state and ignore all read/overflow events
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: paulus <paulus@samba.org>
Cc: stephane eranian <eranian@googlemail.com>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Yanmin <yanmin_zhang@linux.intel.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Cc: David Miller <davem@davemloft.net>
Cc: Michael Cree <mcree@orcon.net.nz>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-06-16 12:37:10 +00:00
|
|
|
armpmu_add(struct perf_event *event, int flags)
|
2010-02-02 19:25:44 +00:00
|
|
|
{
|
2011-04-28 15:27:54 +00:00
|
|
|
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
|
2014-05-13 18:36:31 +00:00
|
|
|
struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
|
2010-02-02 19:25:44 +00:00
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
int idx;
|
|
|
|
|
2015-05-13 16:12:25 +00:00
|
|
|
/* An event following a process won't be stopped earlier */
|
|
|
|
if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
|
|
|
|
return -ENOENT;
|
|
|
|
|
2010-02-02 19:25:44 +00:00
|
|
|
/* If we don't have a space for the counter then finish early. */
|
2012-07-30 11:00:02 +00:00
|
|
|
idx = armpmu->get_event_idx(hw_events, event);
|
2017-04-11 08:39:44 +00:00
|
|
|
if (idx < 0)
|
|
|
|
return idx;
|
2010-02-02 19:25:44 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If there is an event in the counter we are going to use then make
|
|
|
|
* sure it is disabled.
|
|
|
|
*/
|
|
|
|
event->hw.idx = idx;
|
2012-07-30 11:00:02 +00:00
|
|
|
armpmu->disable(event);
|
2011-05-17 10:20:11 +00:00
|
|
|
hw_events->events[idx] = event;
|
2010-02-02 19:25:44 +00:00
|
|
|
|
perf: Rework the PMU methods
Replace pmu::{enable,disable,start,stop,unthrottle} with
pmu::{add,del,start,stop}, all of which take a flags argument.
The new interface extends the capability to stop a counter while
keeping it scheduled on the PMU. We replace the throttled state with
the generic stopped state.
This also allows us to efficiently stop/start counters over certain
code paths (like IRQ handlers).
It also allows scheduling a counter without it starting, allowing for
a generic frozen state (useful for rotating stopped counters).
The stopped state is implemented in two different ways, depending on
how the architecture implemented the throttled state:
1) We disable the counter:
a) the pmu has per-counter enable bits, we flip that
b) we program a NOP event, preserving the counter state
2) We store the counter state and ignore all read/overflow events
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: paulus <paulus@samba.org>
Cc: stephane eranian <eranian@googlemail.com>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Yanmin <yanmin_zhang@linux.intel.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Cc: David Miller <davem@davemloft.net>
Cc: Michael Cree <mcree@orcon.net.nz>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-06-16 12:37:10 +00:00
|
|
|
hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
|
|
|
|
if (flags & PERF_EF_START)
|
|
|
|
armpmu_start(event, PERF_EF_RELOAD);
|
2010-02-02 19:25:44 +00:00
|
|
|
|
|
|
|
/* Propagate our changes to the userspace mapping. */
|
|
|
|
perf_event_update_userpage(event);
|
|
|
|
|
2017-04-11 08:39:44 +00:00
|
|
|
return 0;
|
2010-02-02 19:25:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2015-03-17 18:14:58 +00:00
|
|
|
validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
|
|
|
|
struct perf_event *event)
|
2010-02-02 19:25:44 +00:00
|
|
|
{
|
2015-03-17 18:14:58 +00:00
|
|
|
struct arm_pmu *armpmu;
|
2010-02-02 19:25:44 +00:00
|
|
|
|
2013-08-07 22:39:41 +00:00
|
|
|
if (is_software_event(event))
|
|
|
|
return 1;
|
|
|
|
|
2015-03-17 18:14:58 +00:00
|
|
|
/*
|
|
|
|
* Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
|
|
|
|
* core perf code won't check that the pmu->ctx == leader->ctx
|
|
|
|
* until after pmu->event_init(event).
|
|
|
|
*/
|
|
|
|
if (event->pmu != pmu)
|
|
|
|
return 0;
|
|
|
|
|
2013-10-09 12:51:29 +00:00
|
|
|
if (event->state < PERF_EVENT_STATE_OFF)
|
2013-04-12 18:04:19 +00:00
|
|
|
return 1;
|
|
|
|
|
|
|
|
if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
|
2010-09-02 08:32:08 +00:00
|
|
|
return 1;
|
2010-02-02 19:25:44 +00:00
|
|
|
|
2015-03-17 18:14:58 +00:00
|
|
|
armpmu = to_arm_pmu(event->pmu);
|
2012-07-30 11:00:02 +00:00
|
|
|
return armpmu->get_event_idx(hw_events, event) >= 0;
|
2010-02-02 19:25:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
validate_group(struct perf_event *event)
|
|
|
|
{
|
|
|
|
struct perf_event *sibling, *leader = event->group_leader;
|
2011-05-17 10:20:11 +00:00
|
|
|
struct pmu_hw_events fake_pmu;
|
2010-02-02 19:25:44 +00:00
|
|
|
|
2011-11-17 15:05:14 +00:00
|
|
|
/*
|
|
|
|
* Initialise the fake PMU. We only need to populate the
|
|
|
|
* used_mask for the purposes of validation.
|
|
|
|
*/
|
2014-05-13 18:08:19 +00:00
|
|
|
memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
|
2010-02-02 19:25:44 +00:00
|
|
|
|
2015-03-17 18:14:58 +00:00
|
|
|
if (!validate_event(event->pmu, &fake_pmu, leader))
|
2011-11-09 16:56:37 +00:00
|
|
|
return -EINVAL;
|
2010-02-02 19:25:44 +00:00
|
|
|
|
2018-03-15 16:36:56 +00:00
|
|
|
for_each_sibling_event(sibling, leader) {
|
2015-03-17 18:14:58 +00:00
|
|
|
if (!validate_event(event->pmu, &fake_pmu, sibling))
|
2011-11-09 16:56:37 +00:00
|
|
|
return -EINVAL;
|
2010-02-02 19:25:44 +00:00
|
|
|
}
|
|
|
|
|
2015-03-17 18:14:58 +00:00
|
|
|
if (!validate_event(event->pmu, &fake_pmu, event))
|
2011-11-09 16:56:37 +00:00
|
|
|
return -EINVAL;
|
2010-02-02 19:25:44 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-31 09:34:25 +00:00
|
|
|
static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
|
2011-02-08 03:54:36 +00:00
|
|
|
{
|
2014-02-07 21:01:19 +00:00
|
|
|
struct arm_pmu *armpmu;
|
2014-02-11 18:08:41 +00:00
|
|
|
int ret;
|
|
|
|
u64 start_clock, finish_clock;
|
2014-02-07 21:01:19 +00:00
|
|
|
|
2014-05-13 18:46:10 +00:00
|
|
|
/*
|
|
|
|
* we request the IRQ with a (possibly percpu) struct arm_pmu**, but
|
|
|
|
* the handlers expect a struct arm_pmu*. The percpu_irq framework will
|
|
|
|
* do any necessary shifting, we just need to perform the first
|
|
|
|
* dereference.
|
|
|
|
*/
|
|
|
|
armpmu = *(void **)dev;
|
2017-12-12 16:56:06 +00:00
|
|
|
if (WARN_ON_ONCE(!armpmu))
|
|
|
|
return IRQ_NONE;
|
2017-04-11 08:39:49 +00:00
|
|
|
|
2014-02-11 18:08:41 +00:00
|
|
|
start_clock = sched_clock();
|
2018-02-05 16:41:56 +00:00
|
|
|
ret = armpmu->handle_irq(irq, armpmu);
|
2014-02-11 18:08:41 +00:00
|
|
|
finish_clock = sched_clock();
|
|
|
|
|
|
|
|
perf_sample_event_took(finish_clock - start_clock);
|
|
|
|
return ret;
|
2011-02-08 03:54:36 +00:00
|
|
|
}
|
|
|
|
|
2011-07-19 10:57:30 +00:00
|
|
|
static int
|
|
|
|
event_requires_mode_exclusion(struct perf_event_attr *attr)
|
|
|
|
{
|
|
|
|
return attr->exclude_idle || attr->exclude_user ||
|
|
|
|
attr->exclude_kernel || attr->exclude_hv;
|
|
|
|
}
|
|
|
|
|
2010-02-02 19:25:44 +00:00
|
|
|
static int
|
|
|
|
__hw_perf_event_init(struct perf_event *event)
|
|
|
|
{
|
2011-04-28 15:27:54 +00:00
|
|
|
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
|
2010-02-02 19:25:44 +00:00
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
2013-01-18 16:10:06 +00:00
|
|
|
int mapping;
|
2010-02-02 19:25:44 +00:00
|
|
|
|
2011-04-28 14:47:10 +00:00
|
|
|
mapping = armpmu->map_event(event);
|
2010-02-02 19:25:44 +00:00
|
|
|
|
|
|
|
if (mapping < 0) {
|
|
|
|
pr_debug("event %x:%llx not supported\n", event->attr.type,
|
|
|
|
event->attr.config);
|
|
|
|
return mapping;
|
|
|
|
}
|
|
|
|
|
2011-07-19 10:57:30 +00:00
|
|
|
/*
|
|
|
|
* We don't assign an index until we actually place the event onto
|
|
|
|
* hardware. Use -1 to signify that we haven't decided where to put it
|
|
|
|
* yet. For SMP systems, each core has it's own PMU so we can't do any
|
|
|
|
* clever allocation or constraints checking at this point.
|
|
|
|
*/
|
|
|
|
hwc->idx = -1;
|
|
|
|
hwc->config_base = 0;
|
|
|
|
hwc->config = 0;
|
|
|
|
hwc->event_base = 0;
|
|
|
|
|
2010-02-02 19:25:44 +00:00
|
|
|
/*
|
|
|
|
* Check whether we need to exclude the counter from certain modes.
|
|
|
|
*/
|
2011-07-19 10:57:30 +00:00
|
|
|
if ((!armpmu->set_event_filter ||
|
|
|
|
armpmu->set_event_filter(hwc, &event->attr)) &&
|
|
|
|
event_requires_mode_exclusion(&event->attr)) {
|
2010-02-02 19:25:44 +00:00
|
|
|
pr_debug("ARM performance counters do not support "
|
|
|
|
"mode exclusion\n");
|
2012-07-04 17:15:42 +00:00
|
|
|
return -EOPNOTSUPP;
|
2010-02-02 19:25:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2011-07-19 10:57:30 +00:00
|
|
|
* Store the event encoding into the config_base field.
|
2010-02-02 19:25:44 +00:00
|
|
|
*/
|
2011-07-19 10:57:30 +00:00
|
|
|
hwc->config_base |= (unsigned long)mapping;
|
2010-02-02 19:25:44 +00:00
|
|
|
|
2014-05-16 21:15:49 +00:00
|
|
|
if (!is_sampling_event(event)) {
|
2012-03-06 16:33:17 +00:00
|
|
|
/*
|
|
|
|
* For non-sampling runs, limit the sample_period to half
|
|
|
|
* of the counter width. That way, the new counter value
|
|
|
|
* is far less likely to overtake the previous one unless
|
|
|
|
* you have some serious IRQ latency issues.
|
|
|
|
*/
|
|
|
|
hwc->sample_period = armpmu->max_period >> 1;
|
2010-02-02 19:25:44 +00:00
|
|
|
hwc->last_period = hwc->sample_period;
|
2010-05-21 12:43:08 +00:00
|
|
|
local64_set(&hwc->period_left, hwc->sample_period);
|
2010-02-02 19:25:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (event->group_leader != event) {
|
2013-02-28 16:51:29 +00:00
|
|
|
if (validate_group(event) != 0)
|
2010-02-02 19:25:44 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2013-01-18 16:10:06 +00:00
|
|
|
return 0;
|
2010-02-02 19:25:44 +00:00
|
|
|
}
|
|
|
|
|
2010-06-11 11:35:08 +00:00
|
|
|
static int armpmu_event_init(struct perf_event *event)
|
2010-02-02 19:25:44 +00:00
|
|
|
{
|
2011-04-28 15:27:54 +00:00
|
|
|
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
|
2010-02-02 19:25:44 +00:00
|
|
|
|
2015-05-13 16:12:25 +00:00
|
|
|
/*
|
|
|
|
* Reject CPU-affine events for CPUs that are of a different class to
|
|
|
|
* that which this PMU handles. Process-following events (where
|
|
|
|
* event->cpu == -1) can be migrated between CPUs, and thus we have to
|
|
|
|
* reject them later (in armpmu_add) if they're scheduled on a
|
|
|
|
* different class of CPU.
|
|
|
|
*/
|
|
|
|
if (event->cpu != -1 &&
|
|
|
|
!cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
|
|
|
|
return -ENOENT;
|
|
|
|
|
2012-02-09 22:20:59 +00:00
|
|
|
/* does not support taken branch sampling */
|
|
|
|
if (has_branch_stack(event))
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
2011-04-28 14:47:10 +00:00
|
|
|
if (armpmu->map_event(event) == -ENOENT)
|
2010-06-11 11:35:08 +00:00
|
|
|
return -ENOENT;
|
|
|
|
|
drivers/perf: arm_pmu: split irq request from enable
For historical reasons, we lazily request and free interrupts in the
arm pmu driver. This requires us to refcount use of the pmu (by way of
counting the active events) in order to request/free interrupts at the
correct times, which complicates the driver somewhat.
The existing logic is flawed, as it only considers currently online CPUs
when requesting, freeing, or managing the affinity of interrupts.
Intervening hotplug events can result in erroneous IRQ affinity, online
CPUs for which interrupts have not been requested, or offline CPUs whose
interrupts are still requested.
To fix this, this patch splits the requesting of interrupts from any
per-cpu management (i.e. per-cpu enable/disable, and configuration of
cpu affinity). We now request all interrupts up-front at probe time (and
never free them, since we never unregister PMUs).
The management of affinity, and per-cpu enable/disable now happens in
our cpu hotplug callback, ensuring it occurs consistently. This means
that we must now invoke the CPU hotplug callback at boot time in order
to configure IRQs, and since the callback also resets the PMU hardware,
we can remove the duplicate reset in the probe path.
This rework renders our event refcounting unnecessary, so this is
removed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
[will: make armpmu_get_cpu_irq static]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-03-10 10:46:15 +00:00
|
|
|
return __hw_perf_event_init(event);
|
2010-02-02 19:25:44 +00:00
|
|
|
}
|
|
|
|
|
perf: Rework the PMU methods
Replace pmu::{enable,disable,start,stop,unthrottle} with
pmu::{add,del,start,stop}, all of which take a flags argument.
The new interface extends the capability to stop a counter while
keeping it scheduled on the PMU. We replace the throttled state with
the generic stopped state.
This also allows us to efficiently stop/start counters over certain
code paths (like IRQ handlers).
It also allows scheduling a counter without it starting, allowing for
a generic frozen state (useful for rotating stopped counters).
The stopped state is implemented in two different ways, depending on
how the architecture implemented the throttled state:
1) We disable the counter:
a) the pmu has per-counter enable bits, we flip that
b) we program a NOP event, preserving the counter state
2) We store the counter state and ignore all read/overflow events
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: paulus <paulus@samba.org>
Cc: stephane eranian <eranian@googlemail.com>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Yanmin <yanmin_zhang@linux.intel.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Cc: David Miller <davem@davemloft.net>
Cc: Michael Cree <mcree@orcon.net.nz>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-06-16 12:37:10 +00:00
|
|
|
static void armpmu_enable(struct pmu *pmu)
|
2010-02-02 19:25:44 +00:00
|
|
|
{
|
2011-05-17 10:20:11 +00:00
|
|
|
struct arm_pmu *armpmu = to_arm_pmu(pmu);
|
2014-05-13 18:36:31 +00:00
|
|
|
struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
|
2011-08-23 10:59:49 +00:00
|
|
|
int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
|
2010-02-02 19:25:44 +00:00
|
|
|
|
2015-05-13 16:12:25 +00:00
|
|
|
/* For task-bound events we may be called on other CPUs */
|
|
|
|
if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
|
|
|
|
return;
|
|
|
|
|
2011-07-01 13:38:12 +00:00
|
|
|
if (enabled)
|
2012-07-30 11:00:02 +00:00
|
|
|
armpmu->start(armpmu);
|
2010-02-02 19:25:44 +00:00
|
|
|
}
|
|
|
|
|
perf: Rework the PMU methods
Replace pmu::{enable,disable,start,stop,unthrottle} with
pmu::{add,del,start,stop}, all of which take a flags argument.
The new interface extends the capability to stop a counter while
keeping it scheduled on the PMU. We replace the throttled state with
the generic stopped state.
This also allows us to efficiently stop/start counters over certain
code paths (like IRQ handlers).
It also allows scheduling a counter without it starting, allowing for
a generic frozen state (useful for rotating stopped counters).
The stopped state is implemented in two different ways, depending on
how the architecture implemented the throttled state:
1) We disable the counter:
a) the pmu has per-counter enable bits, we flip that
b) we program a NOP event, preserving the counter state
2) We store the counter state and ignore all read/overflow events
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: paulus <paulus@samba.org>
Cc: stephane eranian <eranian@googlemail.com>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Yanmin <yanmin_zhang@linux.intel.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Cc: David Miller <davem@davemloft.net>
Cc: Michael Cree <mcree@orcon.net.nz>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-06-16 12:37:10 +00:00
|
|
|
static void armpmu_disable(struct pmu *pmu)
|
2010-02-02 19:25:44 +00:00
|
|
|
{
|
2011-04-28 15:27:54 +00:00
|
|
|
struct arm_pmu *armpmu = to_arm_pmu(pmu);
|
2015-05-13 16:12:25 +00:00
|
|
|
|
|
|
|
/* For task-bound events we may be called on other CPUs */
|
|
|
|
if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
|
|
|
|
return;
|
|
|
|
|
2012-07-30 11:00:02 +00:00
|
|
|
armpmu->stop(armpmu);
|
2010-02-02 19:25:44 +00:00
|
|
|
}
|
|
|
|
|
2015-05-13 16:12:26 +00:00
|
|
|
/*
|
|
|
|
* In heterogeneous systems, events are specific to a particular
|
|
|
|
* microarchitecture, and aren't suitable for another. Thus, only match CPUs of
|
|
|
|
* the same microarchitecture.
|
|
|
|
*/
|
|
|
|
static int armpmu_filter_match(struct perf_event *event)
|
|
|
|
{
|
|
|
|
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
|
|
|
|
unsigned int cpu = smp_processor_id();
|
|
|
|
return cpumask_test_cpu(cpu, &armpmu->supported_cpus);
|
|
|
|
}
|
|
|
|
|
drivers/perf: arm_pmu: expose a cpumask in sysfs
In systems with heterogeneous CPUs, there are multiple logical CPU PMUs,
each of which covers a subset of CPUs in the system. In some cases
userspace needs to know which CPUs a given logical PMU covers, so we'd
like to expose a cpumask under sysfs, similar to what is done for uncore
PMUs.
Unfortunately, prior to commit 00e727bb389359c8 ("perf stat: Balance
opening and reading events"), perf stat only correctly handled a cpumask
holding a single CPU, and only when profiling in system-wide mode. In
other cases, the presence of a cpumask file could cause perf stat to
behave erratically.
Thus, exposing a cpumask file would break older perf binaries in cases
where they would otherwise work.
To avoid this issue while still providing userspace with the information
it needs, this patch exposes a differently-named file (cpus) under
sysfs. New tools can look for this and operate correctly, while older
tools will not be adversely affected by its presence.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-09-09 13:08:30 +00:00
|
|
|
static ssize_t armpmu_cpumask_show(struct device *dev,
|
|
|
|
struct device_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev));
|
|
|
|
return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus);
|
|
|
|
}
|
|
|
|
|
|
|
|
static DEVICE_ATTR(cpus, S_IRUGO, armpmu_cpumask_show, NULL);
|
|
|
|
|
|
|
|
static struct attribute *armpmu_common_attrs[] = {
|
|
|
|
&dev_attr_cpus.attr,
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct attribute_group armpmu_common_attr_group = {
|
|
|
|
.attrs = armpmu_common_attrs,
|
|
|
|
};
|
|
|
|
|
2015-05-26 16:23:39 +00:00
|
|
|
/* Set at runtime when we know what CPU type we are. */
|
|
|
|
static struct arm_pmu *__oprofile_cpu_pmu;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Despite the names, these two functions are CPU-specific and are used
|
|
|
|
* by the OProfile/perf code.
|
|
|
|
*/
|
|
|
|
const char *perf_pmu_name(void)
|
|
|
|
{
|
|
|
|
if (!__oprofile_cpu_pmu)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
return __oprofile_cpu_pmu->name;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(perf_pmu_name);
|
|
|
|
|
|
|
|
int perf_num_counters(void)
|
|
|
|
{
|
|
|
|
int max_events = 0;
|
|
|
|
|
|
|
|
if (__oprofile_cpu_pmu != NULL)
|
|
|
|
max_events = __oprofile_cpu_pmu->num_events;
|
|
|
|
|
|
|
|
return max_events;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(perf_num_counters);
|
|
|
|
|
2017-12-12 16:56:06 +00:00
|
|
|
static int armpmu_count_irq_users(const int irq)
|
2015-05-26 16:23:39 +00:00
|
|
|
{
|
2017-12-12 16:56:06 +00:00
|
|
|
int cpu, count = 0;
|
2015-05-26 16:23:39 +00:00
|
|
|
|
2017-12-12 16:56:06 +00:00
|
|
|
for_each_possible_cpu(cpu) {
|
|
|
|
if (per_cpu(cpu_irq, cpu) == irq)
|
|
|
|
count++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
2017-03-10 10:46:14 +00:00
|
|
|
|
2017-10-09 16:09:05 +00:00
|
|
|
void armpmu_free_irq(int irq, int cpu)
|
2017-12-12 16:56:06 +00:00
|
|
|
{
|
|
|
|
if (per_cpu(cpu_irq, cpu) == 0)
|
|
|
|
return;
|
|
|
|
if (WARN_ON(irq != per_cpu(cpu_irq, cpu)))
|
2017-04-11 08:39:51 +00:00
|
|
|
return;
|
2017-03-10 10:46:14 +00:00
|
|
|
|
2017-12-12 16:56:06 +00:00
|
|
|
if (!irq_is_percpu_devid(irq))
|
|
|
|
free_irq(irq, per_cpu_ptr(&cpu_armpmu, cpu));
|
|
|
|
else if (armpmu_count_irq_users(irq) == 1)
|
|
|
|
free_percpu_irq(irq, &cpu_armpmu);
|
|
|
|
|
|
|
|
per_cpu(cpu_irq, cpu) = 0;
|
2017-04-11 08:39:51 +00:00
|
|
|
}
|
2017-03-10 10:46:14 +00:00
|
|
|
|
2017-10-09 16:09:05 +00:00
|
|
|
int armpmu_request_irq(int irq, int cpu)
|
2017-12-12 16:56:06 +00:00
|
|
|
{
|
|
|
|
int err = 0;
|
|
|
|
const irq_handler_t handler = armpmu_dispatch_irq;
|
2017-04-11 08:39:51 +00:00
|
|
|
if (!irq)
|
|
|
|
return 0;
|
2015-05-26 16:23:39 +00:00
|
|
|
|
2018-02-05 16:41:59 +00:00
|
|
|
if (!irq_is_percpu_devid(irq)) {
|
2017-07-25 15:30:34 +00:00
|
|
|
unsigned long irq_flags;
|
|
|
|
|
|
|
|
err = irq_force_affinity(irq, cpumask_of(cpu));
|
|
|
|
|
|
|
|
if (err && num_possible_cpus() > 1) {
|
|
|
|
pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
|
|
|
|
irq, cpu);
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
2018-02-05 16:41:56 +00:00
|
|
|
irq_flags = IRQF_PERCPU |
|
|
|
|
IRQF_NOBALANCING |
|
|
|
|
IRQF_NO_THREAD;
|
2017-07-25 15:30:34 +00:00
|
|
|
|
2018-02-05 16:42:00 +00:00
|
|
|
irq_set_status_flags(irq, IRQ_NOAUTOEN);
|
2017-07-25 15:30:34 +00:00
|
|
|
err = request_irq(irq, handler, irq_flags, "arm-pmu",
|
2017-12-12 16:56:06 +00:00
|
|
|
per_cpu_ptr(&cpu_armpmu, cpu));
|
|
|
|
} else if (armpmu_count_irq_users(irq) == 0) {
|
2018-02-05 16:41:59 +00:00
|
|
|
err = request_percpu_irq(irq, handler, "arm-pmu",
|
2017-12-12 16:56:06 +00:00
|
|
|
&cpu_armpmu);
|
2017-04-11 08:39:51 +00:00
|
|
|
}
|
2017-03-10 10:46:14 +00:00
|
|
|
|
2017-07-25 15:30:34 +00:00
|
|
|
if (err)
|
|
|
|
goto err_out;
|
2015-05-26 16:23:39 +00:00
|
|
|
|
2017-12-12 16:56:06 +00:00
|
|
|
per_cpu(cpu_irq, cpu) = irq;
|
2015-05-26 16:23:39 +00:00
|
|
|
return 0;
|
2017-07-25 15:30:34 +00:00
|
|
|
|
|
|
|
err_out:
|
|
|
|
pr_err("unable to request IRQ%d for ARM PMU counters\n", irq);
|
|
|
|
return err;
|
2015-05-26 16:23:39 +00:00
|
|
|
}
|
|
|
|
|
drivers/perf: arm_pmu: split irq request from enable
For historical reasons, we lazily request and free interrupts in the
arm pmu driver. This requires us to refcount use of the pmu (by way of
counting the active events) in order to request/free interrupts at the
correct times, which complicates the driver somewhat.
The existing logic is flawed, as it only considers currently online CPUs
when requesting, freeing, or managing the affinity of interrupts.
Intervening hotplug events can result in erroneous IRQ affinity, online
CPUs for which interrupts have not been requested, or offline CPUs whose
interrupts are still requested.
To fix this, this patch splits the requesting of interrupts from any
per-cpu management (i.e. per-cpu enable/disable, and configuration of
cpu affinity). We now request all interrupts up-front at probe time (and
never free them, since we never unregister PMUs).
The management of affinity, and per-cpu enable/disable now happens in
our cpu hotplug callback, ensuring it occurs consistently. This means
that we must now invoke the CPU hotplug callback at boot time in order
to configure IRQs, and since the callback also resets the PMU hardware,
we can remove the duplicate reset in the probe path.
This rework renders our event refcounting unnecessary, so this is
removed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
[will: make armpmu_get_cpu_irq static]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-03-10 10:46:15 +00:00
|
|
|
static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu)
|
|
|
|
{
|
|
|
|
struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
|
|
|
|
return per_cpu(hw_events->irq, cpu);
|
|
|
|
}
|
|
|
|
|
2015-05-26 16:23:39 +00:00
|
|
|
/*
|
|
|
|
* PMU hardware loses all context when a CPU goes offline.
|
|
|
|
* When a CPU is hotplugged back in, since some hardware registers are
|
|
|
|
* UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
|
|
|
|
* junk values out of them.
|
|
|
|
*/
|
2016-08-17 17:14:20 +00:00
|
|
|
static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node)
|
2015-05-26 16:23:39 +00:00
|
|
|
{
|
2016-08-17 17:14:20 +00:00
|
|
|
struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
|
drivers/perf: arm_pmu: split irq request from enable
For historical reasons, we lazily request and free interrupts in the
arm pmu driver. This requires us to refcount use of the pmu (by way of
counting the active events) in order to request/free interrupts at the
correct times, which complicates the driver somewhat.
The existing logic is flawed, as it only considers currently online CPUs
when requesting, freeing, or managing the affinity of interrupts.
Intervening hotplug events can result in erroneous IRQ affinity, online
CPUs for which interrupts have not been requested, or offline CPUs whose
interrupts are still requested.
To fix this, this patch splits the requesting of interrupts from any
per-cpu management (i.e. per-cpu enable/disable, and configuration of
cpu affinity). We now request all interrupts up-front at probe time (and
never free them, since we never unregister PMUs).
The management of affinity, and per-cpu enable/disable now happens in
our cpu hotplug callback, ensuring it occurs consistently. This means
that we must now invoke the CPU hotplug callback at boot time in order
to configure IRQs, and since the callback also resets the PMU hardware,
we can remove the duplicate reset in the probe path.
This rework renders our event refcounting unnecessary, so this is
removed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
[will: make armpmu_get_cpu_irq static]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-03-10 10:46:15 +00:00
|
|
|
int irq;
|
2015-05-26 16:23:39 +00:00
|
|
|
|
2016-08-17 17:14:20 +00:00
|
|
|
if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
|
|
|
|
return 0;
|
|
|
|
if (pmu->reset)
|
|
|
|
pmu->reset(pmu);
|
drivers/perf: arm_pmu: split irq request from enable
For historical reasons, we lazily request and free interrupts in the
arm pmu driver. This requires us to refcount use of the pmu (by way of
counting the active events) in order to request/free interrupts at the
correct times, which complicates the driver somewhat.
The existing logic is flawed, as it only considers currently online CPUs
when requesting, freeing, or managing the affinity of interrupts.
Intervening hotplug events can result in erroneous IRQ affinity, online
CPUs for which interrupts have not been requested, or offline CPUs whose
interrupts are still requested.
To fix this, this patch splits the requesting of interrupts from any
per-cpu management (i.e. per-cpu enable/disable, and configuration of
cpu affinity). We now request all interrupts up-front at probe time (and
never free them, since we never unregister PMUs).
The management of affinity, and per-cpu enable/disable now happens in
our cpu hotplug callback, ensuring it occurs consistently. This means
that we must now invoke the CPU hotplug callback at boot time in order
to configure IRQs, and since the callback also resets the PMU hardware,
we can remove the duplicate reset in the probe path.
This rework renders our event refcounting unnecessary, so this is
removed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
[will: make armpmu_get_cpu_irq static]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-03-10 10:46:15 +00:00
|
|
|
|
2017-12-12 16:56:06 +00:00
|
|
|
per_cpu(cpu_armpmu, cpu) = pmu;
|
|
|
|
|
drivers/perf: arm_pmu: split irq request from enable
For historical reasons, we lazily request and free interrupts in the
arm pmu driver. This requires us to refcount use of the pmu (by way of
counting the active events) in order to request/free interrupts at the
correct times, which complicates the driver somewhat.
The existing logic is flawed, as it only considers currently online CPUs
when requesting, freeing, or managing the affinity of interrupts.
Intervening hotplug events can result in erroneous IRQ affinity, online
CPUs for which interrupts have not been requested, or offline CPUs whose
interrupts are still requested.
To fix this, this patch splits the requesting of interrupts from any
per-cpu management (i.e. per-cpu enable/disable, and configuration of
cpu affinity). We now request all interrupts up-front at probe time (and
never free them, since we never unregister PMUs).
The management of affinity, and per-cpu enable/disable now happens in
our cpu hotplug callback, ensuring it occurs consistently. This means
that we must now invoke the CPU hotplug callback at boot time in order
to configure IRQs, and since the callback also resets the PMU hardware,
we can remove the duplicate reset in the probe path.
This rework renders our event refcounting unnecessary, so this is
removed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
[will: make armpmu_get_cpu_irq static]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-03-10 10:46:15 +00:00
|
|
|
irq = armpmu_get_cpu_irq(pmu, cpu);
|
|
|
|
if (irq) {
|
2018-02-05 16:42:00 +00:00
|
|
|
if (irq_is_percpu_devid(irq))
|
drivers/perf: arm_pmu: split irq request from enable
For historical reasons, we lazily request and free interrupts in the
arm pmu driver. This requires us to refcount use of the pmu (by way of
counting the active events) in order to request/free interrupts at the
correct times, which complicates the driver somewhat.
The existing logic is flawed, as it only considers currently online CPUs
when requesting, freeing, or managing the affinity of interrupts.
Intervening hotplug events can result in erroneous IRQ affinity, online
CPUs for which interrupts have not been requested, or offline CPUs whose
interrupts are still requested.
To fix this, this patch splits the requesting of interrupts from any
per-cpu management (i.e. per-cpu enable/disable, and configuration of
cpu affinity). We now request all interrupts up-front at probe time (and
never free them, since we never unregister PMUs).
The management of affinity, and per-cpu enable/disable now happens in
our cpu hotplug callback, ensuring it occurs consistently. This means
that we must now invoke the CPU hotplug callback at boot time in order
to configure IRQs, and since the callback also resets the PMU hardware,
we can remove the duplicate reset in the probe path.
This rework renders our event refcounting unnecessary, so this is
removed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
[will: make armpmu_get_cpu_irq static]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-03-10 10:46:15 +00:00
|
|
|
enable_percpu_irq(irq, IRQ_TYPE_NONE);
|
2018-02-05 16:42:00 +00:00
|
|
|
else
|
|
|
|
enable_irq(irq);
|
drivers/perf: arm_pmu: split irq request from enable
For historical reasons, we lazily request and free interrupts in the
arm pmu driver. This requires us to refcount use of the pmu (by way of
counting the active events) in order to request/free interrupts at the
correct times, which complicates the driver somewhat.
The existing logic is flawed, as it only considers currently online CPUs
when requesting, freeing, or managing the affinity of interrupts.
Intervening hotplug events can result in erroneous IRQ affinity, online
CPUs for which interrupts have not been requested, or offline CPUs whose
interrupts are still requested.
To fix this, this patch splits the requesting of interrupts from any
per-cpu management (i.e. per-cpu enable/disable, and configuration of
cpu affinity). We now request all interrupts up-front at probe time (and
never free them, since we never unregister PMUs).
The management of affinity, and per-cpu enable/disable now happens in
our cpu hotplug callback, ensuring it occurs consistently. This means
that we must now invoke the CPU hotplug callback at boot time in order
to configure IRQs, and since the callback also resets the PMU hardware,
we can remove the duplicate reset in the probe path.
This rework renders our event refcounting unnecessary, so this is
removed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
[will: make armpmu_get_cpu_irq static]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-03-10 10:46:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node)
|
|
|
|
{
|
|
|
|
struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
|
|
|
|
int irq;
|
|
|
|
|
|
|
|
if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
irq = armpmu_get_cpu_irq(pmu, cpu);
|
2018-02-05 16:42:00 +00:00
|
|
|
if (irq) {
|
|
|
|
if (irq_is_percpu_devid(irq))
|
|
|
|
disable_percpu_irq(irq);
|
|
|
|
else
|
2018-02-26 16:10:56 +00:00
|
|
|
disable_irq_nosync(irq);
|
2018-02-05 16:42:00 +00:00
|
|
|
}
|
drivers/perf: arm_pmu: split irq request from enable
For historical reasons, we lazily request and free interrupts in the
arm pmu driver. This requires us to refcount use of the pmu (by way of
counting the active events) in order to request/free interrupts at the
correct times, which complicates the driver somewhat.
The existing logic is flawed, as it only considers currently online CPUs
when requesting, freeing, or managing the affinity of interrupts.
Intervening hotplug events can result in erroneous IRQ affinity, online
CPUs for which interrupts have not been requested, or offline CPUs whose
interrupts are still requested.
To fix this, this patch splits the requesting of interrupts from any
per-cpu management (i.e. per-cpu enable/disable, and configuration of
cpu affinity). We now request all interrupts up-front at probe time (and
never free them, since we never unregister PMUs).
The management of affinity, and per-cpu enable/disable now happens in
our cpu hotplug callback, ensuring it occurs consistently. This means
that we must now invoke the CPU hotplug callback at boot time in order
to configure IRQs, and since the callback also resets the PMU hardware,
we can remove the duplicate reset in the probe path.
This rework renders our event refcounting unnecessary, so this is
removed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
[will: make armpmu_get_cpu_irq static]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-03-10 10:46:15 +00:00
|
|
|
|
2017-12-12 16:56:06 +00:00
|
|
|
per_cpu(cpu_armpmu, cpu) = NULL;
|
|
|
|
|
2016-07-13 17:16:36 +00:00
|
|
|
return 0;
|
2015-05-26 16:23:39 +00:00
|
|
|
}
|
|
|
|
|
2016-02-23 18:22:39 +00:00
|
|
|
#ifdef CONFIG_CPU_PM
|
|
|
|
static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
|
|
|
|
{
|
|
|
|
struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
|
|
|
|
struct perf_event *event;
|
|
|
|
int idx;
|
|
|
|
|
|
|
|
for (idx = 0; idx < armpmu->num_events; idx++) {
|
|
|
|
/*
|
|
|
|
* If the counter is not used skip it, there is no
|
|
|
|
* need of stopping/restarting it.
|
|
|
|
*/
|
|
|
|
if (!test_bit(idx, hw_events->used_mask))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
event = hw_events->events[idx];
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case CPU_PM_ENTER:
|
|
|
|
/*
|
|
|
|
* Stop and update the counter
|
|
|
|
*/
|
|
|
|
armpmu_stop(event, PERF_EF_UPDATE);
|
|
|
|
break;
|
|
|
|
case CPU_PM_EXIT:
|
|
|
|
case CPU_PM_ENTER_FAILED:
|
2016-04-21 09:24:34 +00:00
|
|
|
/*
|
|
|
|
* Restore and enable the counter.
|
|
|
|
* armpmu_start() indirectly calls
|
|
|
|
*
|
|
|
|
* perf_event_update_userpage()
|
|
|
|
*
|
|
|
|
* that requires RCU read locking to be functional,
|
|
|
|
* wrap the call within RCU_NONIDLE to make the
|
|
|
|
* RCU subsystem aware this cpu is not idle from
|
|
|
|
* an RCU perspective for the armpmu_start() call
|
|
|
|
* duration.
|
|
|
|
*/
|
|
|
|
RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
|
2016-02-23 18:22:39 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
|
|
|
|
void *v)
|
|
|
|
{
|
|
|
|
struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
|
|
|
|
struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
|
|
|
|
int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
|
|
|
|
|
|
|
|
if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Always reset the PMU registers on power-up even if
|
|
|
|
* there are no events running.
|
|
|
|
*/
|
|
|
|
if (cmd == CPU_PM_EXIT && armpmu->reset)
|
|
|
|
armpmu->reset(armpmu);
|
|
|
|
|
|
|
|
if (!enabled)
|
|
|
|
return NOTIFY_OK;
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case CPU_PM_ENTER:
|
|
|
|
armpmu->stop(armpmu);
|
|
|
|
cpu_pm_pmu_setup(armpmu, cmd);
|
|
|
|
break;
|
|
|
|
case CPU_PM_EXIT:
|
|
|
|
cpu_pm_pmu_setup(armpmu, cmd);
|
|
|
|
case CPU_PM_ENTER_FAILED:
|
|
|
|
armpmu->start(armpmu);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
return NOTIFY_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
|
|
|
|
{
|
|
|
|
cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
|
|
|
|
return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
|
|
|
|
{
|
|
|
|
cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
|
|
|
|
static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
|
|
|
|
#endif
|
|
|
|
|
2015-05-26 16:23:39 +00:00
|
|
|
static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
drivers/perf: arm_pmu: split irq request from enable
For historical reasons, we lazily request and free interrupts in the
arm pmu driver. This requires us to refcount use of the pmu (by way of
counting the active events) in order to request/free interrupts at the
correct times, which complicates the driver somewhat.
The existing logic is flawed, as it only considers currently online CPUs
when requesting, freeing, or managing the affinity of interrupts.
Intervening hotplug events can result in erroneous IRQ affinity, online
CPUs for which interrupts have not been requested, or offline CPUs whose
interrupts are still requested.
To fix this, this patch splits the requesting of interrupts from any
per-cpu management (i.e. per-cpu enable/disable, and configuration of
cpu affinity). We now request all interrupts up-front at probe time (and
never free them, since we never unregister PMUs).
The management of affinity, and per-cpu enable/disable now happens in
our cpu hotplug callback, ensuring it occurs consistently. This means
that we must now invoke the CPU hotplug callback at boot time in order
to configure IRQs, and since the callback also resets the PMU hardware,
we can remove the duplicate reset in the probe path.
This rework renders our event refcounting unnecessary, so this is
removed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
[will: make armpmu_get_cpu_irq static]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-03-10 10:46:15 +00:00
|
|
|
err = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_STARTING,
|
|
|
|
&cpu_pmu->node);
|
2016-08-17 17:14:20 +00:00
|
|
|
if (err)
|
2017-03-10 10:46:13 +00:00
|
|
|
goto out;
|
2015-05-26 16:23:39 +00:00
|
|
|
|
2016-02-23 18:22:39 +00:00
|
|
|
err = cpu_pm_pmu_register(cpu_pmu);
|
|
|
|
if (err)
|
|
|
|
goto out_unregister;
|
|
|
|
|
2015-05-26 16:23:39 +00:00
|
|
|
return 0;
|
|
|
|
|
2016-02-23 18:22:39 +00:00
|
|
|
out_unregister:
|
2016-08-17 17:14:20 +00:00
|
|
|
cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
|
|
|
|
&cpu_pmu->node);
|
2017-03-10 10:46:13 +00:00
|
|
|
out:
|
2015-05-26 16:23:39 +00:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
|
|
|
|
{
|
2016-02-23 18:22:39 +00:00
|
|
|
cpu_pm_pmu_unregister(cpu_pmu);
|
2016-08-17 17:14:20 +00:00
|
|
|
cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
|
|
|
|
&cpu_pmu->node);
|
2015-05-26 16:23:39 +00:00
|
|
|
}
|
|
|
|
|
2018-02-05 16:41:58 +00:00
|
|
|
static struct arm_pmu *__armpmu_alloc(gfp_t flags)
|
2017-03-10 10:46:13 +00:00
|
|
|
{
|
|
|
|
struct arm_pmu *pmu;
|
|
|
|
int cpu;
|
|
|
|
|
2018-02-05 16:41:58 +00:00
|
|
|
pmu = kzalloc(sizeof(*pmu), flags);
|
2017-03-10 10:46:13 +00:00
|
|
|
if (!pmu) {
|
|
|
|
pr_info("failed to allocate PMU device!\n");
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2018-02-05 16:41:58 +00:00
|
|
|
pmu->hw_events = alloc_percpu_gfp(struct pmu_hw_events, flags);
|
2017-03-10 10:46:13 +00:00
|
|
|
if (!pmu->hw_events) {
|
|
|
|
pr_info("failed to allocate per-cpu PMU data.\n");
|
|
|
|
goto out_free_pmu;
|
|
|
|
}
|
|
|
|
|
2017-04-11 08:39:46 +00:00
|
|
|
pmu->pmu = (struct pmu) {
|
|
|
|
.pmu_enable = armpmu_enable,
|
|
|
|
.pmu_disable = armpmu_disable,
|
|
|
|
.event_init = armpmu_event_init,
|
|
|
|
.add = armpmu_add,
|
|
|
|
.del = armpmu_del,
|
|
|
|
.start = armpmu_start,
|
|
|
|
.stop = armpmu_stop,
|
|
|
|
.read = armpmu_read,
|
|
|
|
.filter_match = armpmu_filter_match,
|
|
|
|
.attr_groups = pmu->attr_groups,
|
|
|
|
/*
|
|
|
|
* This is a CPU PMU potentially in a heterogeneous
|
|
|
|
* configuration (e.g. big.LITTLE). This is not an uncore PMU,
|
|
|
|
* and we have taken ctx sharing into account (e.g. with our
|
|
|
|
* pmu::filter_match callback and pmu::event_init group
|
|
|
|
* validation).
|
|
|
|
*/
|
|
|
|
.capabilities = PERF_PMU_CAP_HETEROGENEOUS_CPUS,
|
|
|
|
};
|
|
|
|
|
|
|
|
pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =
|
|
|
|
&armpmu_common_attr_group;
|
|
|
|
|
2017-03-10 10:46:13 +00:00
|
|
|
for_each_possible_cpu(cpu) {
|
|
|
|
struct pmu_hw_events *events;
|
|
|
|
|
|
|
|
events = per_cpu_ptr(pmu->hw_events, cpu);
|
|
|
|
raw_spin_lock_init(&events->pmu_lock);
|
|
|
|
events->percpu_pmu = pmu;
|
|
|
|
}
|
|
|
|
|
|
|
|
return pmu;
|
|
|
|
|
|
|
|
out_free_pmu:
|
|
|
|
kfree(pmu);
|
|
|
|
out:
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2018-02-05 16:41:58 +00:00
|
|
|
struct arm_pmu *armpmu_alloc(void)
|
|
|
|
{
|
|
|
|
return __armpmu_alloc(GFP_KERNEL);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct arm_pmu *armpmu_alloc_atomic(void)
|
|
|
|
{
|
|
|
|
return __armpmu_alloc(GFP_ATOMIC);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2017-04-11 08:39:53 +00:00
|
|
|
void armpmu_free(struct arm_pmu *pmu)
|
2017-03-10 10:46:13 +00:00
|
|
|
{
|
|
|
|
free_percpu(pmu->hw_events);
|
|
|
|
kfree(pmu);
|
|
|
|
}
|
|
|
|
|
2017-04-11 08:39:47 +00:00
|
|
|
int armpmu_register(struct arm_pmu *pmu)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = cpu_pmu_init(pmu);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
|
|
|
|
if (ret)
|
|
|
|
goto out_destroy;
|
|
|
|
|
|
|
|
if (!__oprofile_cpu_pmu)
|
|
|
|
__oprofile_cpu_pmu = pmu;
|
|
|
|
|
|
|
|
pr_info("enabled with %s PMU driver, %d counters available\n",
|
|
|
|
pmu->name, pmu->num_events);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
out_destroy:
|
|
|
|
cpu_pmu_destroy(pmu);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2016-07-20 07:51:11 +00:00
|
|
|
static int arm_pmu_hp_init(void)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2016-08-17 17:14:20 +00:00
|
|
|
ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING,
|
2016-12-21 19:19:54 +00:00
|
|
|
"perf/arm/pmu:starting",
|
drivers/perf: arm_pmu: split irq request from enable
For historical reasons, we lazily request and free interrupts in the
arm pmu driver. This requires us to refcount use of the pmu (by way of
counting the active events) in order to request/free interrupts at the
correct times, which complicates the driver somewhat.
The existing logic is flawed, as it only considers currently online CPUs
when requesting, freeing, or managing the affinity of interrupts.
Intervening hotplug events can result in erroneous IRQ affinity, online
CPUs for which interrupts have not been requested, or offline CPUs whose
interrupts are still requested.
To fix this, this patch splits the requesting of interrupts from any
per-cpu management (i.e. per-cpu enable/disable, and configuration of
cpu affinity). We now request all interrupts up-front at probe time (and
never free them, since we never unregister PMUs).
The management of affinity, and per-cpu enable/disable now happens in
our cpu hotplug callback, ensuring it occurs consistently. This means
that we must now invoke the CPU hotplug callback at boot time in order
to configure IRQs, and since the callback also resets the PMU hardware,
we can remove the duplicate reset in the probe path.
This rework renders our event refcounting unnecessary, so this is
removed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
[will: make armpmu_get_cpu_irq static]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-03-10 10:46:15 +00:00
|
|
|
arm_perf_starting_cpu,
|
|
|
|
arm_perf_teardown_cpu);
|
2016-07-20 07:51:11 +00:00
|
|
|
if (ret)
|
|
|
|
pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n",
|
|
|
|
ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
subsys_initcall(arm_pmu_hp_init);
|