forked from Minki/linux
ARM: perf: consolidate common PMU behaviour
The functions for mapping PMU events (perf, cache and raw) are common between all PMU types and differ only in the data on which they operate. This patch implements common definitions of these mapping functions and changes the arm_pmu struct to hold pointers to the data which they require. This is in anticipation of separating out the PMU-specific code into separate files. Acked-by: Jamie Iles <jamie.iles@jamieiles.com> Acked-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Will Deacon
parent
3561d43fd2
commit
84fee97a02
@ -84,14 +84,17 @@ struct arm_pmu {
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irqreturn_t (*handle_irq)(int irq_num, void *dev);
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void (*enable)(struct hw_perf_event *evt, int idx);
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void (*disable)(struct hw_perf_event *evt, int idx);
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int (*event_map)(int evt);
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u64 (*raw_event)(u64);
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int (*get_event_idx)(struct cpu_hw_events *cpuc,
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struct hw_perf_event *hwc);
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u32 (*read_counter)(int idx);
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void (*write_counter)(int idx, u32 val);
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void (*start)(void);
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void (*stop)(void);
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const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX];
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const unsigned (*event_map)[PERF_COUNT_HW_MAX];
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u32 raw_event_mask;
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int num_events;
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u64 max_period;
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};
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@ -136,10 +139,6 @@ EXPORT_SYMBOL_GPL(perf_num_counters);
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#define CACHE_OP_UNSUPPORTED 0xFFFF
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static unsigned armpmu_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX];
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static int
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armpmu_map_cache_event(u64 config)
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{
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@ -157,7 +156,7 @@ armpmu_map_cache_event(u64 config)
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if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
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return -EINVAL;
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ret = (int)armpmu_perf_cache_map[cache_type][cache_op][cache_result];
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ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result];
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if (ret == CACHE_OP_UNSUPPORTED)
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return -ENOENT;
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@ -165,6 +164,19 @@ armpmu_map_cache_event(u64 config)
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return ret;
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}
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static int
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armpmu_map_event(u64 config)
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{
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int mapping = (*armpmu->event_map)[config];
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return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping;
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}
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static int
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armpmu_map_raw_event(u64 config)
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{
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return (int)(config & armpmu->raw_event_mask);
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}
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static int
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armpmu_event_set_period(struct perf_event *event,
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struct hw_perf_event *hwc,
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@ -458,11 +470,11 @@ __hw_perf_event_init(struct perf_event *event)
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/* Decode the generic type into an ARM event identifier. */
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if (PERF_TYPE_HARDWARE == event->attr.type) {
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mapping = armpmu->event_map(event->attr.config);
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mapping = armpmu_map_event(event->attr.config);
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} else if (PERF_TYPE_HW_CACHE == event->attr.type) {
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mapping = armpmu_map_cache_event(event->attr.config);
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} else if (PERF_TYPE_RAW == event->attr.type) {
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mapping = armpmu->raw_event(event->attr.config);
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mapping = armpmu_map_raw_event(event->attr.config);
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} else {
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pr_debug("event type %x not supported\n", event->attr.type);
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return -EOPNOTSUPP;
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@ -1121,30 +1133,6 @@ armv6pmu_stop(void)
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spin_unlock_irqrestore(&pmu_lock, flags);
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}
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static inline int
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armv6pmu_event_map(int config)
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{
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int mapping = armv6_perf_map[config];
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if (HW_OP_UNSUPPORTED == mapping)
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mapping = -EOPNOTSUPP;
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return mapping;
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}
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static inline int
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armv6mpcore_pmu_event_map(int config)
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{
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int mapping = armv6mpcore_perf_map[config];
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if (HW_OP_UNSUPPORTED == mapping)
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mapping = -EOPNOTSUPP;
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return mapping;
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}
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static u64
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armv6pmu_raw_event(u64 config)
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{
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return config & 0xff;
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}
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static int
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armv6pmu_get_event_idx(struct cpu_hw_events *cpuc,
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struct hw_perf_event *event)
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@ -1240,13 +1228,14 @@ static const struct arm_pmu armv6pmu = {
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.handle_irq = armv6pmu_handle_irq,
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.enable = armv6pmu_enable_event,
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.disable = armv6pmu_disable_event,
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.event_map = armv6pmu_event_map,
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.raw_event = armv6pmu_raw_event,
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.read_counter = armv6pmu_read_counter,
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.write_counter = armv6pmu_write_counter,
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.get_event_idx = armv6pmu_get_event_idx,
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.start = armv6pmu_start,
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.stop = armv6pmu_stop,
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.cache_map = &armv6_perf_cache_map,
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.event_map = &armv6_perf_map,
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.raw_event_mask = 0xFF,
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.num_events = 3,
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.max_period = (1LLU << 32) - 1,
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};
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@ -1263,13 +1252,14 @@ static const struct arm_pmu armv6mpcore_pmu = {
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.handle_irq = armv6pmu_handle_irq,
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.enable = armv6pmu_enable_event,
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.disable = armv6mpcore_pmu_disable_event,
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.event_map = armv6mpcore_pmu_event_map,
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.raw_event = armv6pmu_raw_event,
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.read_counter = armv6pmu_read_counter,
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.write_counter = armv6pmu_write_counter,
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.get_event_idx = armv6pmu_get_event_idx,
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.start = armv6pmu_start,
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.stop = armv6pmu_stop,
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.cache_map = &armv6mpcore_perf_cache_map,
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.event_map = &armv6mpcore_perf_map,
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.raw_event_mask = 0xFF,
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.num_events = 3,
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.max_period = (1LLU << 32) - 1,
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};
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@ -2093,27 +2083,6 @@ static void armv7pmu_stop(void)
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spin_unlock_irqrestore(&pmu_lock, flags);
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}
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static inline int armv7_a8_pmu_event_map(int config)
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{
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int mapping = armv7_a8_perf_map[config];
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if (HW_OP_UNSUPPORTED == mapping)
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mapping = -EOPNOTSUPP;
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return mapping;
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}
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static inline int armv7_a9_pmu_event_map(int config)
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{
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int mapping = armv7_a9_perf_map[config];
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if (HW_OP_UNSUPPORTED == mapping)
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mapping = -EOPNOTSUPP;
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return mapping;
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}
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static u64 armv7pmu_raw_event(u64 config)
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{
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return config & 0xff;
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}
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static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc,
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struct hw_perf_event *event)
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{
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@ -2144,12 +2113,12 @@ static struct arm_pmu armv7pmu = {
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.handle_irq = armv7pmu_handle_irq,
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.enable = armv7pmu_enable_event,
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.disable = armv7pmu_disable_event,
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.raw_event = armv7pmu_raw_event,
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.read_counter = armv7pmu_read_counter,
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.write_counter = armv7pmu_write_counter,
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.get_event_idx = armv7pmu_get_event_idx,
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.start = armv7pmu_start,
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.stop = armv7pmu_stop,
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.raw_event_mask = 0xFF,
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.max_period = (1LLU << 32) - 1,
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};
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@ -2318,21 +2287,6 @@ static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
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#define XSCALE_PMU_RESET (CCNT_RESET | PMN_RESET)
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#define XSCALE_PMU_CNT64 0x008
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static inline int
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xscalepmu_event_map(int config)
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{
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int mapping = xscale_perf_map[config];
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if (HW_OP_UNSUPPORTED == mapping)
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mapping = -EOPNOTSUPP;
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return mapping;
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}
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static u64
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xscalepmu_raw_event(u64 config)
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{
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return config & 0xff;
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}
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#define XSCALE1_OVERFLOWED_MASK 0x700
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#define XSCALE1_CCOUNT_OVERFLOW 0x400
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#define XSCALE1_COUNT0_OVERFLOW 0x100
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@ -2598,13 +2552,14 @@ static const struct arm_pmu xscale1pmu = {
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.handle_irq = xscale1pmu_handle_irq,
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.enable = xscale1pmu_enable_event,
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.disable = xscale1pmu_disable_event,
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.event_map = xscalepmu_event_map,
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.raw_event = xscalepmu_raw_event,
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.read_counter = xscale1pmu_read_counter,
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.write_counter = xscale1pmu_write_counter,
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.get_event_idx = xscale1pmu_get_event_idx,
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.start = xscale1pmu_start,
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.stop = xscale1pmu_stop,
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.cache_map = &xscale_perf_cache_map,
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.event_map = &xscale_perf_map,
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.raw_event_mask = 0xFF,
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.num_events = 3,
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.max_period = (1LLU << 32) - 1,
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};
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@ -2953,13 +2908,14 @@ static const struct arm_pmu xscale2pmu = {
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.handle_irq = xscale2pmu_handle_irq,
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.enable = xscale2pmu_enable_event,
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.disable = xscale2pmu_disable_event,
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.event_map = xscalepmu_event_map,
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.raw_event = xscalepmu_raw_event,
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.read_counter = xscale2pmu_read_counter,
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.write_counter = xscale2pmu_write_counter,
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.get_event_idx = xscale2pmu_get_event_idx,
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.start = xscale2pmu_start,
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.stop = xscale2pmu_stop,
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.cache_map = &xscale_perf_cache_map,
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.event_map = &xscale_perf_map,
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.raw_event_mask = 0xFF,
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.num_events = 5,
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.max_period = (1LLU << 32) - 1,
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};
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@ -2978,20 +2934,14 @@ init_hw_perf_events(void)
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case 0xB560: /* ARM1156 */
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case 0xB760: /* ARM1176 */
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armpmu = &armv6pmu;
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memcpy(armpmu_perf_cache_map, armv6_perf_cache_map,
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sizeof(armv6_perf_cache_map));
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break;
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case 0xB020: /* ARM11mpcore */
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armpmu = &armv6mpcore_pmu;
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memcpy(armpmu_perf_cache_map,
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armv6mpcore_perf_cache_map,
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sizeof(armv6mpcore_perf_cache_map));
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break;
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case 0xC080: /* Cortex-A8 */
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armv7pmu.id = ARM_PERF_PMU_ID_CA8;
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memcpy(armpmu_perf_cache_map, armv7_a8_perf_cache_map,
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sizeof(armv7_a8_perf_cache_map));
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armv7pmu.event_map = armv7_a8_pmu_event_map;
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armv7pmu.cache_map = &armv7_a8_perf_cache_map;
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armv7pmu.event_map = &armv7_a8_perf_map;
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armpmu = &armv7pmu;
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/* Reset PMNC and read the nb of CNTx counters
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@ -3000,9 +2950,8 @@ init_hw_perf_events(void)
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break;
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case 0xC090: /* Cortex-A9 */
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armv7pmu.id = ARM_PERF_PMU_ID_CA9;
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memcpy(armpmu_perf_cache_map, armv7_a9_perf_cache_map,
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sizeof(armv7_a9_perf_cache_map));
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armv7pmu.event_map = armv7_a9_pmu_event_map;
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armv7pmu.cache_map = &armv7_a9_perf_cache_map;
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armv7pmu.event_map = &armv7_a9_perf_map;
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armpmu = &armv7pmu;
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/* Reset PMNC and read the nb of CNTx counters
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@ -3016,13 +2965,9 @@ init_hw_perf_events(void)
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switch (part_number) {
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case 1:
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armpmu = &xscale1pmu;
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memcpy(armpmu_perf_cache_map, xscale_perf_cache_map,
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sizeof(xscale_perf_cache_map));
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break;
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case 2:
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armpmu = &xscale2pmu;
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memcpy(armpmu_perf_cache_map, xscale_perf_cache_map,
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sizeof(xscale_perf_cache_map));
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break;
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}
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}
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