2007-10-21 23:41:49 +00:00
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/*
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2014-03-05 17:09:32 +00:00
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* Copyright © 2006-2014 Intel Corporation.
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2007-10-21 23:41:49 +00:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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2014-03-05 17:09:32 +00:00
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* Authors: David Woodhouse <dwmw2@infradead.org>,
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* Ashok Raj <ashok.raj@intel.com>,
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* Shaohua Li <shaohua.li@intel.com>,
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* Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>,
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* Fenghua Yu <fenghua.yu@intel.com>
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2007-10-21 23:41:49 +00:00
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*/
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#include <linux/init.h>
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#include <linux/bitmap.h>
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2008-03-04 23:22:08 +00:00
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#include <linux/debugfs.h>
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2011-10-29 14:26:25 +00:00
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#include <linux/export.h>
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2007-10-21 23:41:49 +00:00
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#include <linux/slab.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/pci.h>
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#include <linux/dmar.h>
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#include <linux/dma-mapping.h>
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#include <linux/mempool.h>
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2014-02-19 06:07:37 +00:00
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#include <linux/memory.h>
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2008-03-04 23:22:08 +00:00
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#include <linux/timer.h>
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2008-09-09 15:37:29 +00:00
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#include <linux/iova.h>
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2008-12-03 13:52:32 +00:00
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#include <linux/iommu.h>
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2008-09-09 15:37:29 +00:00
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#include <linux/intel-iommu.h>
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2011-03-23 21:16:14 +00:00
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#include <linux/syscore_ops.h>
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2009-09-02 01:25:07 +00:00
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#include <linux/tboot.h>
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2009-08-31 05:24:23 +00:00
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#include <linux/dmi.h>
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2011-04-04 13:55:18 +00:00
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#include <linux/pci-ats.h>
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2011-12-08 18:22:09 +00:00
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#include <linux/memblock.h>
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2014-06-04 23:06:51 +00:00
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#include <linux/dma-contiguous.h>
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2012-03-30 18:47:08 +00:00
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#include <asm/irq_remapping.h>
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2007-10-21 23:41:49 +00:00
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#include <asm/cacheflush.h>
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2008-07-11 01:23:42 +00:00
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#include <asm/iommu.h>
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2007-10-21 23:41:49 +00:00
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2012-09-26 10:44:43 +00:00
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#include "irq_remapping.h"
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2008-10-17 01:02:32 +00:00
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#define ROOT_SIZE VTD_PAGE_SIZE
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#define CONTEXT_SIZE VTD_PAGE_SIZE
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2007-10-21 23:41:49 +00:00
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#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
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2015-03-25 15:05:47 +00:00
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#define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB)
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2007-10-21 23:41:49 +00:00
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#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
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2009-09-30 16:12:17 +00:00
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#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
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2007-10-21 23:41:49 +00:00
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#define IOAPIC_RANGE_START (0xfee00000)
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#define IOAPIC_RANGE_END (0xfeefffff)
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#define IOVA_START_ADDR (0x1000)
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#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
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2009-04-25 00:30:20 +00:00
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#define MAX_AGAW_WIDTH 64
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2014-01-06 06:18:12 +00:00
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#define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
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2009-04-25 00:30:20 +00:00
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2009-09-19 14:34:04 +00:00
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#define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
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#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
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/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
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to match. That way, we can use 'unsigned long' for PFNs with impunity. */
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#define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \
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__DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
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#define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
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2007-10-21 23:41:49 +00:00
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2015-01-12 17:51:15 +00:00
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/* IO virtual address start page frame number */
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#define IOVA_START_PFN (1)
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2008-11-20 15:49:43 +00:00
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#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
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2009-04-07 02:01:15 +00:00
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#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
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2009-04-07 02:01:13 +00:00
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#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
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2008-03-04 23:22:08 +00:00
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2010-09-22 20:05:11 +00:00
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/* page table handling */
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#define LEVEL_STRIDE (9)
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#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
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2011-11-10 09:32:30 +00:00
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/*
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* This bitmap is used to advertise the page sizes our hardware support
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* to the IOMMU core, which will then use this information to split
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* physically contiguous memory regions it is mapping into page sizes
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* that we support.
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*
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* Traditionally the IOMMU core just handed us the mappings directly,
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* after making sure the size is an order of a 4KiB page and that the
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* mapping has natural alignment.
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*
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* To retain this behavior, we currently advertise that we support
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* all page sizes that are an order of 4KiB.
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*
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* If at some point we'd like to utilize the IOMMU core's new behavior,
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* we could change this to advertise the real page sizes we support.
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*/
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#define INTEL_IOMMU_PGSIZES (~0xFFFUL)
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2010-09-22 20:05:11 +00:00
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static inline int agaw_to_level(int agaw)
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{
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return agaw + 2;
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}
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static inline int agaw_to_width(int agaw)
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{
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2014-01-06 06:18:12 +00:00
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return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH);
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2010-09-22 20:05:11 +00:00
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}
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static inline int width_to_agaw(int width)
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{
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2014-01-06 06:18:12 +00:00
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return DIV_ROUND_UP(width - 30, LEVEL_STRIDE);
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2010-09-22 20:05:11 +00:00
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}
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static inline unsigned int level_to_offset_bits(int level)
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{
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return (level - 1) * LEVEL_STRIDE;
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}
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static inline int pfn_level_offset(unsigned long pfn, int level)
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{
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return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
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}
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static inline unsigned long level_mask(int level)
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{
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return -1UL << level_to_offset_bits(level);
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}
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static inline unsigned long level_size(int level)
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{
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return 1UL << level_to_offset_bits(level);
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}
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static inline unsigned long align_to_level(unsigned long pfn, int level)
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{
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return (pfn + level_size(level) - 1) & level_mask(level);
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}
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2009-05-10 22:57:41 +00:00
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intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
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static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
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{
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2014-01-06 06:18:12 +00:00
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return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
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}
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2009-06-27 15:21:20 +00:00
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/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
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are never going to work. */
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static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
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{
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return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
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}
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static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
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{
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return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
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}
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static inline unsigned long page_to_dma_pfn(struct page *pg)
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{
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return mm_to_dma_pfn(page_to_pfn(pg));
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}
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static inline unsigned long virt_to_dma_pfn(void *p)
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{
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return page_to_dma_pfn(virt_to_page(p));
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}
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2008-12-08 03:06:32 +00:00
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/* global iommu list, set NULL for ignored DMAR units */
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static struct intel_iommu **g_iommus;
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2009-09-30 16:12:17 +00:00
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static void __init check_tylersburg_isoch(void);
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2009-02-13 23:18:03 +00:00
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static int rwbf_quirk;
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2011-05-03 07:08:37 +00:00
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/*
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* set to 1 to panic kernel if can't successfully enable VT-d
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* (used when kernel is launched w/ TXT)
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*/
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static int force_on = 0;
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2008-11-20 15:49:44 +00:00
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/*
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* 0: Present
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* 1-11: Reserved
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* 12-63: Context Ptr (12 - (haw-1))
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* 64-127: Reserved
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*/
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struct root_entry {
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2015-02-13 14:35:21 +00:00
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u64 lo;
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u64 hi;
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2008-11-20 15:49:44 +00:00
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};
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#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
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2008-11-20 15:49:45 +00:00
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/*
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* low 64 bits:
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* 0: present
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* 1: fault processing disable
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* 2-3: translation type
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* 12-63: address space root
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* high 64 bits:
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* 0-2: address width
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* 3-6: aval
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* 8-23: domain id
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*/
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struct context_entry {
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u64 lo;
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u64 hi;
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};
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2008-11-21 16:54:46 +00:00
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static inline bool context_present(struct context_entry *context)
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{
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return (context->lo & 1);
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}
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static inline void context_set_present(struct context_entry *context)
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{
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context->lo |= 1;
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}
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static inline void context_set_fault_enable(struct context_entry *context)
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{
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context->lo &= (((u64)-1) << 2) | 1;
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}
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static inline void context_set_translation_type(struct context_entry *context,
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unsigned long value)
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{
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context->lo &= (((u64)-1) << 4) | 3;
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context->lo |= (value & 3) << 2;
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}
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static inline void context_set_address_root(struct context_entry *context,
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unsigned long value)
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{
|
x86/vt-d: Fix incorrect bit operations in setting values
The function context_set_address_root() and set_root_value are setting new
address in a wrong way, and this patch is trying to fix this problem.
According to Intel Vt-d specs(Feb 2011, Revision 1.3), Chapter 9.1 and 9.2,
field ctp in root entry is using bits 12:63, field asr in context entry is
using bits 12:63.
To set these fields, the following functions are used:
static inline void context_set_address_root(struct context_entry *context,
unsigned long value);
and
static inline void set_root_value(struct root_entry *root, unsigned long value)
But they are using an invalid method to set these fields, in current code, only
a '|' operator is used to set it. This will not set the asr to the expected
value if it has an old value.
For example:
Before calling this function,
context->lo = 0x3456789012111;
value = 0x123456789abcef12;
After we call context_set_address_root(context, value), expected result is
context->lo == 0x123456789abce111;
But the actual result is:
context->lo == 0x1237577f9bbde111;
So we need to clear bits 12:63 before setting the new value, this will fix
this problem.
Signed-off-by: Li, Zhen-Hua <zhen-hual@hp.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-11-05 07:30:19 +00:00
|
|
|
context->lo &= ~VTD_PAGE_MASK;
|
2008-11-21 16:54:46 +00:00
|
|
|
context->lo |= value & VTD_PAGE_MASK;
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}
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static inline void context_set_address_width(struct context_entry *context,
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unsigned long value)
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{
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context->hi |= value & 7;
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|
|
|
}
|
|
|
|
|
|
|
|
static inline void context_set_domain_id(struct context_entry *context,
|
|
|
|
unsigned long value)
|
|
|
|
{
|
|
|
|
context->hi |= (value & ((1 << 16) - 1)) << 8;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void context_clear_entry(struct context_entry *context)
|
|
|
|
{
|
|
|
|
context->lo = 0;
|
|
|
|
context->hi = 0;
|
|
|
|
}
|
2008-11-20 15:49:45 +00:00
|
|
|
|
2008-11-20 15:49:46 +00:00
|
|
|
/*
|
|
|
|
* 0: readable
|
|
|
|
* 1: writable
|
|
|
|
* 2-6: reserved
|
|
|
|
* 7: super page
|
2009-03-18 07:33:07 +00:00
|
|
|
* 8-10: available
|
|
|
|
* 11: snoop behavior
|
2008-11-20 15:49:46 +00:00
|
|
|
* 12-63: Host physcial address
|
|
|
|
*/
|
|
|
|
struct dma_pte {
|
|
|
|
u64 val;
|
|
|
|
};
|
|
|
|
|
2008-11-21 16:56:53 +00:00
|
|
|
static inline void dma_clear_pte(struct dma_pte *pte)
|
|
|
|
{
|
|
|
|
pte->val = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline u64 dma_pte_addr(struct dma_pte *pte)
|
|
|
|
{
|
2009-07-01 18:21:24 +00:00
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
return pte->val & VTD_PAGE_MASK;
|
|
|
|
#else
|
|
|
|
/* Must have a full atomic 64-bit read */
|
2010-08-10 00:38:53 +00:00
|
|
|
return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
|
2009-07-01 18:21:24 +00:00
|
|
|
#endif
|
2008-11-21 16:56:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool dma_pte_present(struct dma_pte *pte)
|
|
|
|
{
|
|
|
|
return (pte->val & 3) != 0;
|
|
|
|
}
|
2008-11-20 15:49:46 +00:00
|
|
|
|
2011-10-14 19:32:46 +00:00
|
|
|
static inline bool dma_pte_superpage(struct dma_pte *pte)
|
|
|
|
{
|
2014-07-04 09:19:10 +00:00
|
|
|
return (pte->val & DMA_PTE_LARGE_PAGE);
|
2011-10-14 19:32:46 +00:00
|
|
|
}
|
|
|
|
|
2009-07-02 10:21:16 +00:00
|
|
|
static inline int first_pte_in_page(struct dma_pte *pte)
|
|
|
|
{
|
|
|
|
return !((unsigned long)pte & ~VTD_PAGE_MASK);
|
|
|
|
}
|
|
|
|
|
2009-06-19 20:47:29 +00:00
|
|
|
/*
|
|
|
|
* This domain is a statically identity mapping domain.
|
|
|
|
* 1. This domain creats a static 1:1 mapping to all usable memory.
|
|
|
|
* 2. It maps to each iommu if successful.
|
|
|
|
* 3. Each iommu mapps to this domain if successful.
|
|
|
|
*/
|
2009-08-04 15:19:20 +00:00
|
|
|
static struct dmar_domain *si_domain;
|
|
|
|
static int hw_pass_through = 1;
|
2009-06-19 20:47:29 +00:00
|
|
|
|
2008-12-08 08:35:39 +00:00
|
|
|
/* domain represents a virtual machine, more than one devices
|
|
|
|
* across iommus may be owned in one domain, e.g. kvm guest.
|
|
|
|
*/
|
2014-07-11 06:19:27 +00:00
|
|
|
#define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 0)
|
2008-12-08 08:35:39 +00:00
|
|
|
|
2009-06-19 20:47:29 +00:00
|
|
|
/* si_domain contains mulitple devices */
|
2014-07-11 06:19:27 +00:00
|
|
|
#define DOMAIN_FLAG_STATIC_IDENTITY (1 << 1)
|
2009-06-19 20:47:29 +00:00
|
|
|
|
2008-11-20 15:49:47 +00:00
|
|
|
struct dmar_domain {
|
|
|
|
int id; /* domain id */
|
2009-10-02 18:01:24 +00:00
|
|
|
int nid; /* node id */
|
2014-11-09 14:47:57 +00:00
|
|
|
DECLARE_BITMAP(iommu_bmp, DMAR_UNITS_SUPPORTED);
|
2012-03-05 23:05:16 +00:00
|
|
|
/* bitmap of iommus this domain uses*/
|
2008-11-20 15:49:47 +00:00
|
|
|
|
2015-03-26 12:43:08 +00:00
|
|
|
struct list_head devices; /* all devices' list */
|
2008-11-20 15:49:47 +00:00
|
|
|
struct iova_domain iovad; /* iova's that belong to this domain */
|
|
|
|
|
|
|
|
struct dma_pte *pgd; /* virtual address */
|
|
|
|
int gaw; /* max guest address width */
|
|
|
|
|
|
|
|
/* adjusted guest address width, 0 is level 2 30-bit */
|
|
|
|
int agaw;
|
|
|
|
|
2008-12-08 01:17:15 +00:00
|
|
|
int flags; /* flags to find out type of domain */
|
2008-12-08 07:49:06 +00:00
|
|
|
|
|
|
|
int iommu_coherency;/* indicate coherency of iommu access */
|
2009-03-18 07:33:05 +00:00
|
|
|
int iommu_snooping; /* indicate snooping control feature*/
|
2008-12-08 14:51:37 +00:00
|
|
|
int iommu_count; /* reference count of iommu */
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
int iommu_superpage;/* Level of superpages supported:
|
|
|
|
0 == 4KiB (no superpages), 1 == 2MiB,
|
|
|
|
2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
|
2008-12-08 14:51:37 +00:00
|
|
|
spinlock_t iommu_lock; /* protect iommu set in domain */
|
2008-12-08 15:10:23 +00:00
|
|
|
u64 max_addr; /* maximum mapped address */
|
2015-03-26 12:43:08 +00:00
|
|
|
|
|
|
|
struct iommu_domain domain; /* generic domain data structure for
|
|
|
|
iommu core */
|
2008-11-20 15:49:47 +00:00
|
|
|
};
|
|
|
|
|
2008-11-20 15:49:48 +00:00
|
|
|
/* PCI domain-device relationship */
|
|
|
|
struct device_domain_info {
|
|
|
|
struct list_head link; /* link to domain siblings */
|
|
|
|
struct list_head global; /* link to global list */
|
2009-04-04 00:45:37 +00:00
|
|
|
u8 bus; /* PCI bus number */
|
2008-11-20 15:49:48 +00:00
|
|
|
u8 devfn; /* PCI devfn number */
|
2014-03-06 17:12:03 +00:00
|
|
|
struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
|
2009-05-18 05:51:37 +00:00
|
|
|
struct intel_iommu *iommu; /* IOMMU used by this device */
|
2008-11-20 15:49:48 +00:00
|
|
|
struct dmar_domain *domain; /* pointer to domain */
|
|
|
|
};
|
|
|
|
|
2014-02-19 06:07:25 +00:00
|
|
|
struct dmar_rmrr_unit {
|
|
|
|
struct list_head list; /* list of rmrr units */
|
|
|
|
struct acpi_dmar_header *hdr; /* ACPI header */
|
|
|
|
u64 base_address; /* reserved base address*/
|
|
|
|
u64 end_address; /* reserved end address */
|
2014-03-07 15:08:36 +00:00
|
|
|
struct dmar_dev_scope *devices; /* target devices */
|
2014-02-19 06:07:25 +00:00
|
|
|
int devices_cnt; /* target device count */
|
|
|
|
};
|
|
|
|
|
|
|
|
struct dmar_atsr_unit {
|
|
|
|
struct list_head list; /* list of ATSR units */
|
|
|
|
struct acpi_dmar_header *hdr; /* ACPI header */
|
2014-03-07 15:08:36 +00:00
|
|
|
struct dmar_dev_scope *devices; /* target devices */
|
2014-02-19 06:07:25 +00:00
|
|
|
int devices_cnt; /* target device count */
|
|
|
|
u8 include_all:1; /* include all ports */
|
|
|
|
};
|
|
|
|
|
|
|
|
static LIST_HEAD(dmar_atsr_units);
|
|
|
|
static LIST_HEAD(dmar_rmrr_units);
|
|
|
|
|
|
|
|
#define for_each_rmrr_units(rmrr) \
|
|
|
|
list_for_each_entry(rmrr, &dmar_rmrr_units, list)
|
|
|
|
|
2008-03-04 23:22:08 +00:00
|
|
|
static void flush_unmaps_timeout(unsigned long data);
|
|
|
|
|
2014-01-06 06:18:26 +00:00
|
|
|
static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
|
2008-03-04 23:22:08 +00:00
|
|
|
|
2008-04-18 20:53:58 +00:00
|
|
|
#define HIGH_WATER_MARK 250
|
|
|
|
struct deferred_flush_tables {
|
|
|
|
int next;
|
|
|
|
struct iova *iova[HIGH_WATER_MARK];
|
|
|
|
struct dmar_domain *domain[HIGH_WATER_MARK];
|
2014-03-05 17:09:32 +00:00
|
|
|
struct page *freelist[HIGH_WATER_MARK];
|
2008-04-18 20:53:58 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct deferred_flush_tables *deferred_flush;
|
|
|
|
|
2008-03-04 23:22:08 +00:00
|
|
|
/* bitmap for indexing intel_iommus */
|
|
|
|
static int g_num_of_iommus;
|
|
|
|
|
|
|
|
static DEFINE_SPINLOCK(async_umap_flush_lock);
|
|
|
|
static LIST_HEAD(unmaps_to_do);
|
|
|
|
|
|
|
|
static int timer_on;
|
|
|
|
static long list_size;
|
|
|
|
|
2014-02-19 06:07:28 +00:00
|
|
|
static void domain_exit(struct dmar_domain *domain);
|
2007-10-21 23:41:49 +00:00
|
|
|
static void domain_remove_dev_info(struct dmar_domain *domain);
|
2014-02-19 06:07:25 +00:00
|
|
|
static void domain_remove_one_dev_info(struct dmar_domain *domain,
|
2014-03-09 23:19:13 +00:00
|
|
|
struct device *dev);
|
2014-02-19 06:07:28 +00:00
|
|
|
static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
|
2014-03-06 17:12:03 +00:00
|
|
|
struct device *dev);
|
2014-07-11 06:19:30 +00:00
|
|
|
static int domain_detach_iommu(struct dmar_domain *domain,
|
|
|
|
struct intel_iommu *iommu);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2011-08-24 00:05:25 +00:00
|
|
|
#ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
|
2009-02-04 22:29:19 +00:00
|
|
|
int dmar_disabled = 0;
|
|
|
|
#else
|
|
|
|
int dmar_disabled = 1;
|
2011-08-24 00:05:25 +00:00
|
|
|
#endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
|
2009-02-04 22:29:19 +00:00
|
|
|
|
2011-11-23 18:42:14 +00:00
|
|
|
int intel_iommu_enabled = 0;
|
|
|
|
EXPORT_SYMBOL_GPL(intel_iommu_enabled);
|
|
|
|
|
2010-06-15 09:57:57 +00:00
|
|
|
static int dmar_map_gfx = 1;
|
2007-10-21 23:41:53 +00:00
|
|
|
static int dmar_forcedac;
|
2008-03-04 23:22:08 +00:00
|
|
|
static int intel_iommu_strict;
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
static int intel_iommu_superpage = 1;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2011-10-14 19:59:46 +00:00
|
|
|
int intel_iommu_gfx_mapped;
|
|
|
|
EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
|
|
|
|
static DEFINE_SPINLOCK(device_domain_lock);
|
|
|
|
static LIST_HEAD(device_domain_list);
|
|
|
|
|
2014-06-27 07:03:12 +00:00
|
|
|
static const struct iommu_ops intel_iommu_ops;
|
2008-12-03 14:14:02 +00:00
|
|
|
|
2015-03-26 12:43:08 +00:00
|
|
|
/* Convert generic 'struct iommu_domain to private struct dmar_domain */
|
|
|
|
static struct dmar_domain *to_dmar_domain(struct iommu_domain *dom)
|
|
|
|
{
|
|
|
|
return container_of(dom, struct dmar_domain, domain);
|
|
|
|
}
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
static int __init intel_iommu_setup(char *str)
|
|
|
|
{
|
|
|
|
if (!str)
|
|
|
|
return -EINVAL;
|
|
|
|
while (*str) {
|
2009-02-04 22:29:19 +00:00
|
|
|
if (!strncmp(str, "on", 2)) {
|
|
|
|
dmar_disabled = 0;
|
|
|
|
printk(KERN_INFO "Intel-IOMMU: enabled\n");
|
|
|
|
} else if (!strncmp(str, "off", 3)) {
|
2007-10-21 23:41:49 +00:00
|
|
|
dmar_disabled = 1;
|
2009-02-04 22:29:19 +00:00
|
|
|
printk(KERN_INFO "Intel-IOMMU: disabled\n");
|
2007-10-21 23:41:49 +00:00
|
|
|
} else if (!strncmp(str, "igfx_off", 8)) {
|
|
|
|
dmar_map_gfx = 0;
|
|
|
|
printk(KERN_INFO
|
|
|
|
"Intel-IOMMU: disable GFX device mapping\n");
|
2007-10-21 23:41:53 +00:00
|
|
|
} else if (!strncmp(str, "forcedac", 8)) {
|
2008-03-04 23:22:08 +00:00
|
|
|
printk(KERN_INFO
|
2007-10-21 23:41:53 +00:00
|
|
|
"Intel-IOMMU: Forcing DAC for PCI devices\n");
|
|
|
|
dmar_forcedac = 1;
|
2008-03-04 23:22:08 +00:00
|
|
|
} else if (!strncmp(str, "strict", 6)) {
|
|
|
|
printk(KERN_INFO
|
|
|
|
"Intel-IOMMU: disable batched IOTLB flush\n");
|
|
|
|
intel_iommu_strict = 1;
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
} else if (!strncmp(str, "sp_off", 6)) {
|
|
|
|
printk(KERN_INFO
|
|
|
|
"Intel-IOMMU: disable supported super page\n");
|
|
|
|
intel_iommu_superpage = 0;
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
str += strcspn(str, ",");
|
|
|
|
while (*str == ',')
|
|
|
|
str++;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
__setup("intel_iommu=", intel_iommu_setup);
|
|
|
|
|
|
|
|
static struct kmem_cache *iommu_domain_cache;
|
|
|
|
static struct kmem_cache *iommu_devinfo_cache;
|
|
|
|
|
2009-10-02 18:01:24 +00:00
|
|
|
static inline void *alloc_pgtable_page(int node)
|
Intel IOMMU: Avoid memory allocation failures in dma map api calls
Intel IOMMU driver needs memory during DMA map calls to setup its internal
page tables and for other data structures. As we all know that these DMA map
calls are mostly called in the interrupt context or with the spinlock held by
the upper level drivers(network/storage drivers), so in order to avoid any
memory allocation failure due to low memory issues, this patch makes memory
allocation by temporarily setting PF_MEMALLOC flags for the current task
before making memory allocation calls.
We evaluated mempools as a backup when kmem_cache_alloc() fails
and found that mempools are really not useful here because
1) We don't know for sure how much to reserve in advance
2) And mempools are not useful for GFP_ATOMIC case (as we call
memory alloc functions with GFP_ATOMIC)
(akpm: point 2 is wrong...)
With PF_MEMALLOC flag set in the current->flags, the VM subsystem avoids any
watermark checks before allocating memory thus guarantee'ing the memory till
the last free page. Further, looking at the code in mm/page_alloc.c in
__alloc_pages() function, looks like this flag is useful only in the
non-interrupt context.
If we are in the interrupt context and memory allocation in IOMMU driver fails
for some reason, then the DMA map api's will return failure and it is up to
the higher level drivers to retry. Suppose, if upper level driver programs
the controller with the buggy DMA virtual address, the IOMMU will block that
DMA transaction when that happens thus preventing any corruption to main
memory.
So far in our test scenario, we were unable to create any memory allocation
failure inside dma map api calls.
Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Cc: Andi Kleen <ak@suse.de>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Muli Ben-Yehuda <muli@il.ibm.com>
Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com>
Cc: Arjan van de Ven <arjan@infradead.org>
Cc: Ashok Raj <ashok.raj@intel.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Christoph Lameter <clameter@sgi.com>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-21 23:41:52 +00:00
|
|
|
{
|
2009-10-02 18:01:24 +00:00
|
|
|
struct page *page;
|
|
|
|
void *vaddr = NULL;
|
Intel IOMMU: Avoid memory allocation failures in dma map api calls
Intel IOMMU driver needs memory during DMA map calls to setup its internal
page tables and for other data structures. As we all know that these DMA map
calls are mostly called in the interrupt context or with the spinlock held by
the upper level drivers(network/storage drivers), so in order to avoid any
memory allocation failure due to low memory issues, this patch makes memory
allocation by temporarily setting PF_MEMALLOC flags for the current task
before making memory allocation calls.
We evaluated mempools as a backup when kmem_cache_alloc() fails
and found that mempools are really not useful here because
1) We don't know for sure how much to reserve in advance
2) And mempools are not useful for GFP_ATOMIC case (as we call
memory alloc functions with GFP_ATOMIC)
(akpm: point 2 is wrong...)
With PF_MEMALLOC flag set in the current->flags, the VM subsystem avoids any
watermark checks before allocating memory thus guarantee'ing the memory till
the last free page. Further, looking at the code in mm/page_alloc.c in
__alloc_pages() function, looks like this flag is useful only in the
non-interrupt context.
If we are in the interrupt context and memory allocation in IOMMU driver fails
for some reason, then the DMA map api's will return failure and it is up to
the higher level drivers to retry. Suppose, if upper level driver programs
the controller with the buggy DMA virtual address, the IOMMU will block that
DMA transaction when that happens thus preventing any corruption to main
memory.
So far in our test scenario, we were unable to create any memory allocation
failure inside dma map api calls.
Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Cc: Andi Kleen <ak@suse.de>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Muli Ben-Yehuda <muli@il.ibm.com>
Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com>
Cc: Arjan van de Ven <arjan@infradead.org>
Cc: Ashok Raj <ashok.raj@intel.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Christoph Lameter <clameter@sgi.com>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-21 23:41:52 +00:00
|
|
|
|
2009-10-02 18:01:24 +00:00
|
|
|
page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
|
|
|
|
if (page)
|
|
|
|
vaddr = page_address(page);
|
Intel IOMMU: Avoid memory allocation failures in dma map api calls
Intel IOMMU driver needs memory during DMA map calls to setup its internal
page tables and for other data structures. As we all know that these DMA map
calls are mostly called in the interrupt context or with the spinlock held by
the upper level drivers(network/storage drivers), so in order to avoid any
memory allocation failure due to low memory issues, this patch makes memory
allocation by temporarily setting PF_MEMALLOC flags for the current task
before making memory allocation calls.
We evaluated mempools as a backup when kmem_cache_alloc() fails
and found that mempools are really not useful here because
1) We don't know for sure how much to reserve in advance
2) And mempools are not useful for GFP_ATOMIC case (as we call
memory alloc functions with GFP_ATOMIC)
(akpm: point 2 is wrong...)
With PF_MEMALLOC flag set in the current->flags, the VM subsystem avoids any
watermark checks before allocating memory thus guarantee'ing the memory till
the last free page. Further, looking at the code in mm/page_alloc.c in
__alloc_pages() function, looks like this flag is useful only in the
non-interrupt context.
If we are in the interrupt context and memory allocation in IOMMU driver fails
for some reason, then the DMA map api's will return failure and it is up to
the higher level drivers to retry. Suppose, if upper level driver programs
the controller with the buggy DMA virtual address, the IOMMU will block that
DMA transaction when that happens thus preventing any corruption to main
memory.
So far in our test scenario, we were unable to create any memory allocation
failure inside dma map api calls.
Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Cc: Andi Kleen <ak@suse.de>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Muli Ben-Yehuda <muli@il.ibm.com>
Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com>
Cc: Arjan van de Ven <arjan@infradead.org>
Cc: Ashok Raj <ashok.raj@intel.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Christoph Lameter <clameter@sgi.com>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-21 23:41:52 +00:00
|
|
|
return vaddr;
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void free_pgtable_page(void *vaddr)
|
|
|
|
{
|
|
|
|
free_page((unsigned long)vaddr);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void *alloc_domain_mem(void)
|
|
|
|
{
|
2009-11-17 07:21:09 +00:00
|
|
|
return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2008-09-09 15:37:29 +00:00
|
|
|
static void free_domain_mem(void *vaddr)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
|
|
|
kmem_cache_free(iommu_domain_cache, vaddr);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void * alloc_devinfo_mem(void)
|
|
|
|
{
|
2009-11-17 07:21:09 +00:00
|
|
|
return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void free_devinfo_mem(void *vaddr)
|
|
|
|
{
|
|
|
|
kmem_cache_free(iommu_devinfo_cache, vaddr);
|
|
|
|
}
|
|
|
|
|
2014-07-11 06:19:27 +00:00
|
|
|
static inline int domain_type_is_vm(struct dmar_domain *domain)
|
|
|
|
{
|
|
|
|
return domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int domain_type_is_vm_or_si(struct dmar_domain *domain)
|
|
|
|
{
|
|
|
|
return domain->flags & (DOMAIN_FLAG_VIRTUAL_MACHINE |
|
|
|
|
DOMAIN_FLAG_STATIC_IDENTITY);
|
|
|
|
}
|
2008-12-08 07:34:06 +00:00
|
|
|
|
2014-07-11 06:19:35 +00:00
|
|
|
static inline int domain_pfn_supported(struct dmar_domain *domain,
|
|
|
|
unsigned long pfn)
|
|
|
|
{
|
|
|
|
int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
|
|
|
|
|
|
|
|
return !(addr_width < BITS_PER_LONG && pfn >> addr_width);
|
|
|
|
}
|
|
|
|
|
2009-04-25 00:30:20 +00:00
|
|
|
static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
|
2008-12-08 07:34:06 +00:00
|
|
|
{
|
|
|
|
unsigned long sagaw;
|
|
|
|
int agaw = -1;
|
|
|
|
|
|
|
|
sagaw = cap_sagaw(iommu->cap);
|
2009-04-25 00:30:20 +00:00
|
|
|
for (agaw = width_to_agaw(max_gaw);
|
2008-12-08 07:34:06 +00:00
|
|
|
agaw >= 0; agaw--) {
|
|
|
|
if (test_bit(agaw, &sagaw))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return agaw;
|
|
|
|
}
|
|
|
|
|
2009-04-25 00:30:20 +00:00
|
|
|
/*
|
|
|
|
* Calculate max SAGAW for each iommu.
|
|
|
|
*/
|
|
|
|
int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* calculate agaw for each iommu.
|
|
|
|
* "SAGAW" may be different across iommus, use a default agaw, and
|
|
|
|
* get a supported less agaw for iommus that don't support the default agaw.
|
|
|
|
*/
|
|
|
|
int iommu_calculate_agaw(struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
|
|
|
|
}
|
|
|
|
|
2009-06-19 20:47:29 +00:00
|
|
|
/* This functionin only returns single iommu in a domain */
|
2008-12-08 07:29:22 +00:00
|
|
|
static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
|
|
|
|
{
|
|
|
|
int iommu_id;
|
|
|
|
|
2009-06-19 20:47:29 +00:00
|
|
|
/* si_domain and vm domain should not get here. */
|
2014-07-11 06:19:27 +00:00
|
|
|
BUG_ON(domain_type_is_vm_or_si(domain));
|
2012-03-05 23:05:16 +00:00
|
|
|
iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus);
|
2008-12-08 07:29:22 +00:00
|
|
|
if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
return g_iommus[iommu_id];
|
|
|
|
}
|
|
|
|
|
2008-12-08 07:49:06 +00:00
|
|
|
static void domain_update_iommu_coherency(struct dmar_domain *domain)
|
|
|
|
{
|
2014-03-12 00:10:29 +00:00
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
struct intel_iommu *iommu;
|
2015-02-06 09:59:53 +00:00
|
|
|
bool found = false;
|
|
|
|
int i;
|
2011-11-12 00:26:44 +00:00
|
|
|
|
2014-03-12 00:10:29 +00:00
|
|
|
domain->iommu_coherency = 1;
|
2008-12-08 07:49:06 +00:00
|
|
|
|
2012-03-05 23:05:16 +00:00
|
|
|
for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
|
2015-02-06 09:59:53 +00:00
|
|
|
found = true;
|
2008-12-08 07:49:06 +00:00
|
|
|
if (!ecap_coherent(g_iommus[i]->ecap)) {
|
|
|
|
domain->iommu_coherency = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2014-03-12 00:10:29 +00:00
|
|
|
if (found)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* No hardware attached; use lowest common denominator */
|
|
|
|
rcu_read_lock();
|
|
|
|
for_each_active_iommu(iommu, drhd) {
|
|
|
|
if (!ecap_coherent(iommu->ecap)) {
|
|
|
|
domain->iommu_coherency = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
rcu_read_unlock();
|
2008-12-08 07:49:06 +00:00
|
|
|
}
|
|
|
|
|
2014-07-11 06:19:37 +00:00
|
|
|
static int domain_update_iommu_snooping(struct intel_iommu *skip)
|
2009-03-18 07:33:05 +00:00
|
|
|
{
|
2014-07-11 06:19:37 +00:00
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
struct intel_iommu *iommu;
|
|
|
|
int ret = 1;
|
2009-03-18 07:33:05 +00:00
|
|
|
|
2014-07-11 06:19:37 +00:00
|
|
|
rcu_read_lock();
|
|
|
|
for_each_active_iommu(iommu, drhd) {
|
|
|
|
if (iommu != skip) {
|
|
|
|
if (!ecap_sc_support(iommu->ecap)) {
|
|
|
|
ret = 0;
|
|
|
|
break;
|
|
|
|
}
|
2009-03-18 07:33:05 +00:00
|
|
|
}
|
|
|
|
}
|
2014-07-11 06:19:37 +00:00
|
|
|
rcu_read_unlock();
|
|
|
|
|
|
|
|
return ret;
|
2009-03-18 07:33:05 +00:00
|
|
|
}
|
|
|
|
|
2014-07-11 06:19:37 +00:00
|
|
|
static int domain_update_iommu_superpage(struct intel_iommu *skip)
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
{
|
2011-10-14 19:32:17 +00:00
|
|
|
struct dmar_drhd_unit *drhd;
|
2014-07-11 06:19:37 +00:00
|
|
|
struct intel_iommu *iommu;
|
2011-10-14 19:32:17 +00:00
|
|
|
int mask = 0xf;
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
|
|
|
|
if (!intel_iommu_superpage) {
|
2014-07-11 06:19:37 +00:00
|
|
|
return 0;
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
}
|
|
|
|
|
2011-10-14 19:32:17 +00:00
|
|
|
/* set iommu_superpage to the smallest common denominator */
|
2014-02-19 06:07:34 +00:00
|
|
|
rcu_read_lock();
|
2011-10-14 19:32:17 +00:00
|
|
|
for_each_active_iommu(iommu, drhd) {
|
2014-07-11 06:19:37 +00:00
|
|
|
if (iommu != skip) {
|
|
|
|
mask &= cap_super_page_val(iommu->cap);
|
|
|
|
if (!mask)
|
|
|
|
break;
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
}
|
|
|
|
}
|
2014-02-19 06:07:34 +00:00
|
|
|
rcu_read_unlock();
|
|
|
|
|
2014-07-11 06:19:37 +00:00
|
|
|
return fls(mask);
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
}
|
|
|
|
|
2009-03-18 07:33:05 +00:00
|
|
|
/* Some capabilities may be different across iommus */
|
|
|
|
static void domain_update_iommu_cap(struct dmar_domain *domain)
|
|
|
|
{
|
|
|
|
domain_update_iommu_coherency(domain);
|
2014-07-11 06:19:37 +00:00
|
|
|
domain->iommu_snooping = domain_update_iommu_snooping(NULL);
|
|
|
|
domain->iommu_superpage = domain_update_iommu_superpage(NULL);
|
2009-03-18 07:33:05 +00:00
|
|
|
}
|
|
|
|
|
2015-02-13 14:35:21 +00:00
|
|
|
static inline struct context_entry *iommu_context_addr(struct intel_iommu *iommu,
|
|
|
|
u8 bus, u8 devfn, int alloc)
|
|
|
|
{
|
|
|
|
struct root_entry *root = &iommu->root_entry[bus];
|
|
|
|
struct context_entry *context;
|
|
|
|
u64 *entry;
|
|
|
|
|
|
|
|
if (ecap_ecs(iommu->ecap)) {
|
|
|
|
if (devfn >= 0x80) {
|
|
|
|
devfn -= 0x80;
|
|
|
|
entry = &root->hi;
|
|
|
|
}
|
|
|
|
devfn *= 2;
|
|
|
|
}
|
|
|
|
entry = &root->lo;
|
|
|
|
if (*entry & 1)
|
|
|
|
context = phys_to_virt(*entry & VTD_PAGE_MASK);
|
|
|
|
else {
|
|
|
|
unsigned long phy_addr;
|
|
|
|
if (!alloc)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
context = alloc_pgtable_page(iommu->node);
|
|
|
|
if (!context)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
__iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
|
|
|
|
phy_addr = virt_to_phys((void *)context);
|
|
|
|
*entry = phy_addr | 1;
|
|
|
|
__iommu_flush_cache(iommu, entry, sizeof(*entry));
|
|
|
|
}
|
|
|
|
return &context[devfn];
|
|
|
|
}
|
|
|
|
|
2014-03-09 21:00:57 +00:00
|
|
|
static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn)
|
2008-12-08 14:51:37 +00:00
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd = NULL;
|
2014-02-19 06:07:32 +00:00
|
|
|
struct intel_iommu *iommu;
|
2014-03-09 21:00:57 +00:00
|
|
|
struct device *tmp;
|
|
|
|
struct pci_dev *ptmp, *pdev = NULL;
|
2014-05-26 12:14:06 +00:00
|
|
|
u16 segment = 0;
|
2008-12-08 14:51:37 +00:00
|
|
|
int i;
|
|
|
|
|
2014-03-09 21:00:57 +00:00
|
|
|
if (dev_is_pci(dev)) {
|
|
|
|
pdev = to_pci_dev(dev);
|
|
|
|
segment = pci_domain_nr(pdev->bus);
|
2015-03-16 22:49:08 +00:00
|
|
|
} else if (has_acpi_companion(dev))
|
2014-03-09 21:00:57 +00:00
|
|
|
dev = &ACPI_COMPANION(dev)->dev;
|
|
|
|
|
2014-02-19 06:07:34 +00:00
|
|
|
rcu_read_lock();
|
2014-02-19 06:07:32 +00:00
|
|
|
for_each_active_iommu(iommu, drhd) {
|
2014-03-09 21:00:57 +00:00
|
|
|
if (pdev && segment != drhd->segment)
|
2009-04-04 00:45:37 +00:00
|
|
|
continue;
|
2008-12-08 14:51:37 +00:00
|
|
|
|
2014-02-19 06:07:32 +00:00
|
|
|
for_each_active_dev_scope(drhd->devices,
|
2014-03-09 21:00:57 +00:00
|
|
|
drhd->devices_cnt, i, tmp) {
|
|
|
|
if (tmp == dev) {
|
|
|
|
*bus = drhd->devices[i].bus;
|
|
|
|
*devfn = drhd->devices[i].devfn;
|
2014-02-19 06:07:32 +00:00
|
|
|
goto out;
|
2014-03-09 21:00:57 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!pdev || !dev_is_pci(tmp))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
ptmp = to_pci_dev(tmp);
|
|
|
|
if (ptmp->subordinate &&
|
|
|
|
ptmp->subordinate->number <= pdev->bus->number &&
|
|
|
|
ptmp->subordinate->busn_res.end >= pdev->bus->number)
|
|
|
|
goto got_pdev;
|
2009-04-03 23:39:25 +00:00
|
|
|
}
|
2008-12-08 14:51:37 +00:00
|
|
|
|
2014-03-09 21:00:57 +00:00
|
|
|
if (pdev && drhd->include_all) {
|
|
|
|
got_pdev:
|
|
|
|
*bus = pdev->bus->number;
|
|
|
|
*devfn = pdev->devfn;
|
2014-02-19 06:07:32 +00:00
|
|
|
goto out;
|
2014-03-09 21:00:57 +00:00
|
|
|
}
|
2008-12-08 14:51:37 +00:00
|
|
|
}
|
2014-02-19 06:07:32 +00:00
|
|
|
iommu = NULL;
|
2014-03-09 21:00:57 +00:00
|
|
|
out:
|
2014-02-19 06:07:34 +00:00
|
|
|
rcu_read_unlock();
|
2008-12-08 14:51:37 +00:00
|
|
|
|
2014-02-19 06:07:32 +00:00
|
|
|
return iommu;
|
2008-12-08 14:51:37 +00:00
|
|
|
}
|
|
|
|
|
2008-12-08 15:00:00 +00:00
|
|
|
static void domain_flush_cache(struct dmar_domain *domain,
|
|
|
|
void *addr, int size)
|
|
|
|
{
|
|
|
|
if (!domain->iommu_coherency)
|
|
|
|
clflush_cache_range(addr, size);
|
|
|
|
}
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
|
|
|
|
{
|
|
|
|
struct context_entry *context;
|
2015-02-13 14:35:21 +00:00
|
|
|
int ret = 0;
|
2007-10-21 23:41:49 +00:00
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
2015-02-13 14:35:21 +00:00
|
|
|
context = iommu_context_addr(iommu, bus, devfn, 0);
|
|
|
|
if (context)
|
|
|
|
ret = context_present(context);
|
2007-10-21 23:41:49 +00:00
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
|
|
|
|
{
|
|
|
|
struct context_entry *context;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
2015-02-13 14:35:21 +00:00
|
|
|
context = iommu_context_addr(iommu, bus, devfn, 0);
|
2007-10-21 23:41:49 +00:00
|
|
|
if (context) {
|
2015-02-13 14:35:21 +00:00
|
|
|
context_clear_entry(context);
|
|
|
|
__iommu_flush_cache(iommu, context, sizeof(*context));
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void free_context_table(struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
unsigned long flags;
|
|
|
|
struct context_entry *context;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
if (!iommu->root_entry) {
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
for (i = 0; i < ROOT_ENTRY_NR; i++) {
|
2015-02-13 14:35:21 +00:00
|
|
|
context = iommu_context_addr(iommu, i, 0, 0);
|
2007-10-21 23:41:49 +00:00
|
|
|
if (context)
|
|
|
|
free_pgtable_page(context);
|
2015-02-13 14:35:21 +00:00
|
|
|
|
|
|
|
if (!ecap_ecs(iommu->ecap))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
context = iommu_context_addr(iommu, i, 0x80, 0);
|
|
|
|
if (context)
|
|
|
|
free_pgtable_page(context);
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
free_pgtable_page(iommu->root_entry);
|
|
|
|
iommu->root_entry = NULL;
|
|
|
|
out:
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
}
|
|
|
|
|
2009-06-28 09:37:25 +00:00
|
|
|
static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
|
2014-03-19 16:07:49 +00:00
|
|
|
unsigned long pfn, int *target_level)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
|
|
|
struct dma_pte *parent, *pte = NULL;
|
|
|
|
int level = agaw_to_level(domain->agaw);
|
2011-10-14 19:32:46 +00:00
|
|
|
int offset;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
|
|
|
BUG_ON(!domain->pgd);
|
2013-10-09 08:03:52 +00:00
|
|
|
|
2014-07-11 06:19:35 +00:00
|
|
|
if (!domain_pfn_supported(domain, pfn))
|
2013-10-09 08:03:52 +00:00
|
|
|
/* Address beyond IOMMU's addressing capabilities. */
|
|
|
|
return NULL;
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
parent = domain->pgd;
|
|
|
|
|
2014-03-19 16:07:49 +00:00
|
|
|
while (1) {
|
2007-10-21 23:41:49 +00:00
|
|
|
void *tmp_page;
|
|
|
|
|
2009-06-28 09:37:25 +00:00
|
|
|
offset = pfn_level_offset(pfn, level);
|
2007-10-21 23:41:49 +00:00
|
|
|
pte = &parent[offset];
|
2014-03-19 16:07:49 +00:00
|
|
|
if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
break;
|
2014-03-19 16:07:49 +00:00
|
|
|
if (level == *target_level)
|
2007-10-21 23:41:49 +00:00
|
|
|
break;
|
|
|
|
|
2008-11-21 16:56:53 +00:00
|
|
|
if (!dma_pte_present(pte)) {
|
2009-07-01 18:21:24 +00:00
|
|
|
uint64_t pteval;
|
|
|
|
|
2009-10-02 18:01:24 +00:00
|
|
|
tmp_page = alloc_pgtable_page(domain->nid);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2009-07-01 18:30:28 +00:00
|
|
|
if (!tmp_page)
|
2007-10-21 23:41:49 +00:00
|
|
|
return NULL;
|
2009-07-01 18:30:28 +00:00
|
|
|
|
2009-07-01 18:21:24 +00:00
|
|
|
domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
|
2009-09-17 01:05:55 +00:00
|
|
|
pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
|
2014-05-26 12:13:47 +00:00
|
|
|
if (cmpxchg64(&pte->val, 0ULL, pteval))
|
2009-07-01 18:21:24 +00:00
|
|
|
/* Someone else set it while we were thinking; use theirs. */
|
|
|
|
free_pgtable_page(tmp_page);
|
2014-05-26 12:13:47 +00:00
|
|
|
else
|
2009-07-01 18:21:24 +00:00
|
|
|
domain_flush_cache(domain, pte, sizeof(*pte));
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
2014-03-19 16:07:49 +00:00
|
|
|
if (level == 1)
|
|
|
|
break;
|
|
|
|
|
2008-11-21 16:56:53 +00:00
|
|
|
parent = phys_to_virt(dma_pte_addr(pte));
|
2007-10-21 23:41:49 +00:00
|
|
|
level--;
|
|
|
|
}
|
|
|
|
|
2014-03-19 16:07:49 +00:00
|
|
|
if (!*target_level)
|
|
|
|
*target_level = level;
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
return pte;
|
|
|
|
}
|
|
|
|
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
/* return address's pte at specific level */
|
2009-06-27 16:14:59 +00:00
|
|
|
static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
|
|
|
|
unsigned long pfn,
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
int level, int *large_page)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
|
|
|
struct dma_pte *parent, *pte = NULL;
|
|
|
|
int total = agaw_to_level(domain->agaw);
|
|
|
|
int offset;
|
|
|
|
|
|
|
|
parent = domain->pgd;
|
|
|
|
while (level <= total) {
|
2009-06-27 16:14:59 +00:00
|
|
|
offset = pfn_level_offset(pfn, total);
|
2007-10-21 23:41:49 +00:00
|
|
|
pte = &parent[offset];
|
|
|
|
if (level == total)
|
|
|
|
return pte;
|
|
|
|
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
if (!dma_pte_present(pte)) {
|
|
|
|
*large_page = total;
|
2007-10-21 23:41:49 +00:00
|
|
|
break;
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
}
|
|
|
|
|
2014-05-20 12:37:51 +00:00
|
|
|
if (dma_pte_superpage(pte)) {
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
*large_page = total;
|
|
|
|
return pte;
|
|
|
|
}
|
|
|
|
|
2008-11-21 16:56:53 +00:00
|
|
|
parent = phys_to_virt(dma_pte_addr(pte));
|
2007-10-21 23:41:49 +00:00
|
|
|
total--;
|
|
|
|
}
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* clear last level pte, a tlb flush should be followed */
|
2014-03-19 16:07:49 +00:00
|
|
|
static void dma_pte_clear_range(struct dmar_domain *domain,
|
2009-06-27 21:09:11 +00:00
|
|
|
unsigned long start_pfn,
|
|
|
|
unsigned long last_pfn)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
unsigned int large_page = 1;
|
2009-06-28 17:52:20 +00:00
|
|
|
struct dma_pte *first_pte, *pte;
|
2009-06-27 18:00:32 +00:00
|
|
|
|
2014-07-11 06:19:35 +00:00
|
|
|
BUG_ON(!domain_pfn_supported(domain, start_pfn));
|
|
|
|
BUG_ON(!domain_pfn_supported(domain, last_pfn));
|
2009-09-19 14:36:28 +00:00
|
|
|
BUG_ON(start_pfn > last_pfn);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2009-06-27 18:15:01 +00:00
|
|
|
/* we don't need lock here; nobody else touches the iova range */
|
2009-09-19 14:36:28 +00:00
|
|
|
do {
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
large_page = 1;
|
|
|
|
first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
|
2009-06-28 17:52:20 +00:00
|
|
|
if (!pte) {
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
start_pfn = align_to_level(start_pfn + 1, large_page + 1);
|
2009-06-28 17:52:20 +00:00
|
|
|
continue;
|
|
|
|
}
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
do {
|
2009-06-28 17:52:20 +00:00
|
|
|
dma_clear_pte(pte);
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
start_pfn += lvl_to_nr_pages(large_page);
|
2009-06-28 17:52:20 +00:00
|
|
|
pte++;
|
2009-07-02 10:21:16 +00:00
|
|
|
} while (start_pfn <= last_pfn && !first_pte_in_page(pte));
|
|
|
|
|
2009-06-28 17:52:20 +00:00
|
|
|
domain_flush_cache(domain, first_pte,
|
|
|
|
(void *)pte - (void *)first_pte);
|
2009-09-19 14:36:28 +00:00
|
|
|
|
|
|
|
} while (start_pfn && start_pfn <= last_pfn);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2013-06-15 16:27:19 +00:00
|
|
|
static void dma_pte_free_level(struct dmar_domain *domain, int level,
|
|
|
|
struct dma_pte *pte, unsigned long pfn,
|
|
|
|
unsigned long start_pfn, unsigned long last_pfn)
|
|
|
|
{
|
|
|
|
pfn = max(start_pfn, pfn);
|
|
|
|
pte = &pte[pfn_level_offset(pfn, level)];
|
|
|
|
|
|
|
|
do {
|
|
|
|
unsigned long level_pfn;
|
|
|
|
struct dma_pte *level_pte;
|
|
|
|
|
|
|
|
if (!dma_pte_present(pte) || dma_pte_superpage(pte))
|
|
|
|
goto next;
|
|
|
|
|
|
|
|
level_pfn = pfn & level_mask(level - 1);
|
|
|
|
level_pte = phys_to_virt(dma_pte_addr(pte));
|
|
|
|
|
|
|
|
if (level > 2)
|
|
|
|
dma_pte_free_level(domain, level - 1, level_pte,
|
|
|
|
level_pfn, start_pfn, last_pfn);
|
|
|
|
|
|
|
|
/* If range covers entire pagetable, free it */
|
|
|
|
if (!(start_pfn > level_pfn ||
|
2014-01-21 23:48:18 +00:00
|
|
|
last_pfn < level_pfn + level_size(level) - 1)) {
|
2013-06-15 16:27:19 +00:00
|
|
|
dma_clear_pte(pte);
|
|
|
|
domain_flush_cache(domain, pte, sizeof(*pte));
|
|
|
|
free_pgtable_page(level_pte);
|
|
|
|
}
|
|
|
|
next:
|
|
|
|
pfn += level_size(level);
|
|
|
|
} while (!first_pte_in_page(++pte) && pfn <= last_pfn);
|
|
|
|
}
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
/* free page table pages. last level pte should already be cleared */
|
|
|
|
static void dma_pte_free_pagetable(struct dmar_domain *domain,
|
2009-06-27 23:27:49 +00:00
|
|
|
unsigned long start_pfn,
|
|
|
|
unsigned long last_pfn)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
2014-07-11 06:19:35 +00:00
|
|
|
BUG_ON(!domain_pfn_supported(domain, start_pfn));
|
|
|
|
BUG_ON(!domain_pfn_supported(domain, last_pfn));
|
2009-09-19 14:36:28 +00:00
|
|
|
BUG_ON(start_pfn > last_pfn);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2014-07-11 06:19:34 +00:00
|
|
|
dma_pte_clear_range(domain, start_pfn, last_pfn);
|
|
|
|
|
2009-06-30 02:40:07 +00:00
|
|
|
/* We don't need lock here; nobody else touches the iova range */
|
2013-06-15 16:27:19 +00:00
|
|
|
dma_pte_free_level(domain, agaw_to_level(domain->agaw),
|
|
|
|
domain->pgd, 0, start_pfn, last_pfn);
|
2009-06-27 21:41:00 +00:00
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
/* free pgd */
|
2009-06-27 23:27:49 +00:00
|
|
|
if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
|
2007-10-21 23:41:49 +00:00
|
|
|
free_pgtable_page(domain->pgd);
|
|
|
|
domain->pgd = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-03-05 17:09:32 +00:00
|
|
|
/* When a page at a given level is being unlinked from its parent, we don't
|
|
|
|
need to *modify* it at all. All we need to do is make a list of all the
|
|
|
|
pages which can be freed just as soon as we've flushed the IOTLB and we
|
|
|
|
know the hardware page-walk will no longer touch them.
|
|
|
|
The 'pte' argument is the *parent* PTE, pointing to the page that is to
|
|
|
|
be freed. */
|
|
|
|
static struct page *dma_pte_list_pagetables(struct dmar_domain *domain,
|
|
|
|
int level, struct dma_pte *pte,
|
|
|
|
struct page *freelist)
|
|
|
|
{
|
|
|
|
struct page *pg;
|
|
|
|
|
|
|
|
pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT);
|
|
|
|
pg->freelist = freelist;
|
|
|
|
freelist = pg;
|
|
|
|
|
|
|
|
if (level == 1)
|
|
|
|
return freelist;
|
|
|
|
|
2014-04-09 02:20:39 +00:00
|
|
|
pte = page_address(pg);
|
|
|
|
do {
|
2014-03-05 17:09:32 +00:00
|
|
|
if (dma_pte_present(pte) && !dma_pte_superpage(pte))
|
|
|
|
freelist = dma_pte_list_pagetables(domain, level - 1,
|
|
|
|
pte, freelist);
|
2014-04-09 02:20:39 +00:00
|
|
|
pte++;
|
|
|
|
} while (!first_pte_in_page(pte));
|
2014-03-05 17:09:32 +00:00
|
|
|
|
|
|
|
return freelist;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level,
|
|
|
|
struct dma_pte *pte, unsigned long pfn,
|
|
|
|
unsigned long start_pfn,
|
|
|
|
unsigned long last_pfn,
|
|
|
|
struct page *freelist)
|
|
|
|
{
|
|
|
|
struct dma_pte *first_pte = NULL, *last_pte = NULL;
|
|
|
|
|
|
|
|
pfn = max(start_pfn, pfn);
|
|
|
|
pte = &pte[pfn_level_offset(pfn, level)];
|
|
|
|
|
|
|
|
do {
|
|
|
|
unsigned long level_pfn;
|
|
|
|
|
|
|
|
if (!dma_pte_present(pte))
|
|
|
|
goto next;
|
|
|
|
|
|
|
|
level_pfn = pfn & level_mask(level);
|
|
|
|
|
|
|
|
/* If range covers entire pagetable, free it */
|
|
|
|
if (start_pfn <= level_pfn &&
|
|
|
|
last_pfn >= level_pfn + level_size(level) - 1) {
|
|
|
|
/* These suborbinate page tables are going away entirely. Don't
|
|
|
|
bother to clear them; we're just going to *free* them. */
|
|
|
|
if (level > 1 && !dma_pte_superpage(pte))
|
|
|
|
freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist);
|
|
|
|
|
|
|
|
dma_clear_pte(pte);
|
|
|
|
if (!first_pte)
|
|
|
|
first_pte = pte;
|
|
|
|
last_pte = pte;
|
|
|
|
} else if (level > 1) {
|
|
|
|
/* Recurse down into a level that isn't *entirely* obsolete */
|
|
|
|
freelist = dma_pte_clear_level(domain, level - 1,
|
|
|
|
phys_to_virt(dma_pte_addr(pte)),
|
|
|
|
level_pfn, start_pfn, last_pfn,
|
|
|
|
freelist);
|
|
|
|
}
|
|
|
|
next:
|
|
|
|
pfn += level_size(level);
|
|
|
|
} while (!first_pte_in_page(++pte) && pfn <= last_pfn);
|
|
|
|
|
|
|
|
if (first_pte)
|
|
|
|
domain_flush_cache(domain, first_pte,
|
|
|
|
(void *)++last_pte - (void *)first_pte);
|
|
|
|
|
|
|
|
return freelist;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We can't just free the pages because the IOMMU may still be walking
|
|
|
|
the page tables, and may have cached the intermediate levels. The
|
|
|
|
pages can only be freed after the IOTLB flush has been done. */
|
|
|
|
struct page *domain_unmap(struct dmar_domain *domain,
|
|
|
|
unsigned long start_pfn,
|
|
|
|
unsigned long last_pfn)
|
|
|
|
{
|
|
|
|
struct page *freelist = NULL;
|
|
|
|
|
2014-07-11 06:19:35 +00:00
|
|
|
BUG_ON(!domain_pfn_supported(domain, start_pfn));
|
|
|
|
BUG_ON(!domain_pfn_supported(domain, last_pfn));
|
2014-03-05 17:09:32 +00:00
|
|
|
BUG_ON(start_pfn > last_pfn);
|
|
|
|
|
|
|
|
/* we don't need lock here; nobody else touches the iova range */
|
|
|
|
freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw),
|
|
|
|
domain->pgd, 0, start_pfn, last_pfn, NULL);
|
|
|
|
|
|
|
|
/* free pgd */
|
|
|
|
if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
|
|
|
|
struct page *pgd_page = virt_to_page(domain->pgd);
|
|
|
|
pgd_page->freelist = freelist;
|
|
|
|
freelist = pgd_page;
|
|
|
|
|
|
|
|
domain->pgd = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return freelist;
|
|
|
|
}
|
|
|
|
|
|
|
|
void dma_free_pagelist(struct page *freelist)
|
|
|
|
{
|
|
|
|
struct page *pg;
|
|
|
|
|
|
|
|
while ((pg = freelist)) {
|
|
|
|
freelist = pg->freelist;
|
|
|
|
free_pgtable_page(page_address(pg));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
/* iommu handling */
|
|
|
|
static int iommu_alloc_root_entry(struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
struct root_entry *root;
|
|
|
|
unsigned long flags;
|
|
|
|
|
2009-10-02 18:01:24 +00:00
|
|
|
root = (struct root_entry *)alloc_pgtable_page(iommu->node);
|
2014-11-09 14:48:02 +00:00
|
|
|
if (!root) {
|
|
|
|
pr_err("IOMMU: allocating root entry for %s failed\n",
|
|
|
|
iommu->name);
|
2007-10-21 23:41:49 +00:00
|
|
|
return -ENOMEM;
|
2014-11-09 14:48:02 +00:00
|
|
|
}
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2008-10-17 01:02:32 +00:00
|
|
|
__iommu_flush_cache(iommu, root, ROOT_SIZE);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
iommu->root_entry = root;
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void iommu_set_root_entry(struct intel_iommu *iommu)
|
|
|
|
{
|
2015-02-13 14:35:21 +00:00
|
|
|
u64 addr;
|
2009-05-10 19:30:58 +00:00
|
|
|
u32 sts;
|
2007-10-21 23:41:49 +00:00
|
|
|
unsigned long flag;
|
|
|
|
|
2015-02-13 14:35:21 +00:00
|
|
|
addr = virt_to_phys(iommu->root_entry);
|
|
|
|
if (ecap_ecs(iommu->ecap))
|
|
|
|
addr |= DMA_RTADDR_RTT;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_lock_irqsave(&iommu->register_lock, flag);
|
2015-02-13 14:35:21 +00:00
|
|
|
dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2009-05-10 19:30:58 +00:00
|
|
|
writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
|
|
|
/* Make sure hardware complete it */
|
|
|
|
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
|
2009-05-10 19:30:58 +00:00
|
|
|
readl, (sts & DMA_GSTS_RTPS), sts);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void iommu_flush_write_buffer(struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
unsigned long flag;
|
|
|
|
|
2009-02-13 23:18:03 +00:00
|
|
|
if (!rwbf_quirk && !cap_rwbf(iommu->cap))
|
2007-10-21 23:41:49 +00:00
|
|
|
return;
|
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_lock_irqsave(&iommu->register_lock, flag);
|
2009-05-10 19:18:18 +00:00
|
|
|
writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
|
|
|
/* Make sure hardware complete it */
|
|
|
|
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
|
2009-05-10 19:30:58 +00:00
|
|
|
readl, (!(val & DMA_GSTS_WBFS)), val);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* return value determine if we need a write buffer flush */
|
2009-05-10 16:16:06 +00:00
|
|
|
static void __iommu_flush_context(struct intel_iommu *iommu,
|
|
|
|
u16 did, u16 source_id, u8 function_mask,
|
|
|
|
u64 type)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
|
|
|
u64 val = 0;
|
|
|
|
unsigned long flag;
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case DMA_CCMD_GLOBAL_INVL:
|
|
|
|
val = DMA_CCMD_GLOBAL_INVL;
|
|
|
|
break;
|
|
|
|
case DMA_CCMD_DOMAIN_INVL:
|
|
|
|
val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
|
|
|
|
break;
|
|
|
|
case DMA_CCMD_DEVICE_INVL:
|
|
|
|
val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
|
|
|
|
| DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
val |= DMA_CCMD_ICC;
|
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_lock_irqsave(&iommu->register_lock, flag);
|
2007-10-21 23:41:49 +00:00
|
|
|
dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
|
|
|
|
|
|
|
|
/* Make sure hardware complete it */
|
|
|
|
IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
|
|
|
|
dmar_readq, (!(val & DMA_CCMD_ICC)), val);
|
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* return value determine if we need a write buffer flush */
|
2009-05-10 18:58:49 +00:00
|
|
|
static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
|
|
|
|
u64 addr, unsigned int size_order, u64 type)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
|
|
|
int tlb_offset = ecap_iotlb_offset(iommu->ecap);
|
|
|
|
u64 val = 0, val_iva = 0;
|
|
|
|
unsigned long flag;
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case DMA_TLB_GLOBAL_FLUSH:
|
|
|
|
/* global flush doesn't need set IVA_REG */
|
|
|
|
val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
|
|
|
|
break;
|
|
|
|
case DMA_TLB_DSI_FLUSH:
|
|
|
|
val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
|
|
|
|
break;
|
|
|
|
case DMA_TLB_PSI_FLUSH:
|
|
|
|
val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
|
2014-03-05 17:09:32 +00:00
|
|
|
/* IH bit is passed in as part of address */
|
2007-10-21 23:41:49 +00:00
|
|
|
val_iva = size_order | addr;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
/* Note: set drain read/write */
|
|
|
|
#if 0
|
|
|
|
/*
|
|
|
|
* This is probably to be super secure.. Looks like we can
|
|
|
|
* ignore it without any impact.
|
|
|
|
*/
|
|
|
|
if (cap_read_drain(iommu->cap))
|
|
|
|
val |= DMA_TLB_READ_DRAIN;
|
|
|
|
#endif
|
|
|
|
if (cap_write_drain(iommu->cap))
|
|
|
|
val |= DMA_TLB_WRITE_DRAIN;
|
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_lock_irqsave(&iommu->register_lock, flag);
|
2007-10-21 23:41:49 +00:00
|
|
|
/* Note: Only uses first TLB reg currently */
|
|
|
|
if (val_iva)
|
|
|
|
dmar_writeq(iommu->reg + tlb_offset, val_iva);
|
|
|
|
dmar_writeq(iommu->reg + tlb_offset + 8, val);
|
|
|
|
|
|
|
|
/* Make sure hardware complete it */
|
|
|
|
IOMMU_WAIT_OP(iommu, tlb_offset + 8,
|
|
|
|
dmar_readq, (!(val & DMA_TLB_IVT)), val);
|
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
|
|
|
/* check IOTLB invalidation granularity */
|
|
|
|
if (DMA_TLB_IAIG(val) == 0)
|
|
|
|
printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
|
|
|
|
if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
|
|
|
|
pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
|
2008-10-17 01:02:32 +00:00
|
|
|
(unsigned long long)DMA_TLB_IIRG(type),
|
|
|
|
(unsigned long long)DMA_TLB_IAIG(val));
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2014-03-09 19:52:30 +00:00
|
|
|
static struct device_domain_info *
|
|
|
|
iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu,
|
|
|
|
u8 bus, u8 devfn)
|
2009-05-18 05:51:37 +00:00
|
|
|
{
|
2015-02-06 09:59:53 +00:00
|
|
|
bool found = false;
|
2009-05-18 05:51:37 +00:00
|
|
|
unsigned long flags;
|
|
|
|
struct device_domain_info *info;
|
2014-03-06 17:12:03 +00:00
|
|
|
struct pci_dev *pdev;
|
2009-05-18 05:51:37 +00:00
|
|
|
|
|
|
|
if (!ecap_dev_iotlb_support(iommu->ecap))
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
if (!iommu->qi)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&device_domain_lock, flags);
|
|
|
|
list_for_each_entry(info, &domain->devices, link)
|
2014-07-11 06:19:25 +00:00
|
|
|
if (info->iommu == iommu && info->bus == bus &&
|
|
|
|
info->devfn == devfn) {
|
2015-02-06 09:59:53 +00:00
|
|
|
found = true;
|
2009-05-18 05:51:37 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&device_domain_lock, flags);
|
|
|
|
|
2014-03-06 17:12:03 +00:00
|
|
|
if (!found || !info->dev || !dev_is_pci(info->dev))
|
2009-05-18 05:51:37 +00:00
|
|
|
return NULL;
|
|
|
|
|
2014-03-06 17:12:03 +00:00
|
|
|
pdev = to_pci_dev(info->dev);
|
|
|
|
|
|
|
|
if (!pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS))
|
2009-05-18 05:51:37 +00:00
|
|
|
return NULL;
|
|
|
|
|
2014-03-06 17:12:03 +00:00
|
|
|
if (!dmar_find_matched_atsr_unit(pdev))
|
2009-05-18 05:51:37 +00:00
|
|
|
return NULL;
|
|
|
|
|
|
|
|
return info;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void iommu_enable_dev_iotlb(struct device_domain_info *info)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
2014-03-06 17:12:03 +00:00
|
|
|
if (!info || !dev_is_pci(info->dev))
|
2009-05-18 05:51:37 +00:00
|
|
|
return;
|
|
|
|
|
2014-03-06 17:12:03 +00:00
|
|
|
pci_enable_ats(to_pci_dev(info->dev), VTD_PAGE_SHIFT);
|
2009-05-18 05:51:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void iommu_disable_dev_iotlb(struct device_domain_info *info)
|
|
|
|
{
|
2014-03-06 17:12:03 +00:00
|
|
|
if (!info->dev || !dev_is_pci(info->dev) ||
|
|
|
|
!pci_ats_enabled(to_pci_dev(info->dev)))
|
2009-05-18 05:51:37 +00:00
|
|
|
return;
|
|
|
|
|
2014-03-06 17:12:03 +00:00
|
|
|
pci_disable_ats(to_pci_dev(info->dev));
|
2009-05-18 05:51:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
|
|
|
|
u64 addr, unsigned mask)
|
|
|
|
{
|
|
|
|
u16 sid, qdep;
|
|
|
|
unsigned long flags;
|
|
|
|
struct device_domain_info *info;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&device_domain_lock, flags);
|
|
|
|
list_for_each_entry(info, &domain->devices, link) {
|
2014-03-06 17:12:03 +00:00
|
|
|
struct pci_dev *pdev;
|
|
|
|
if (!info->dev || !dev_is_pci(info->dev))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
pdev = to_pci_dev(info->dev);
|
|
|
|
if (!pci_ats_enabled(pdev))
|
2009-05-18 05:51:37 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
sid = info->bus << 8 | info->devfn;
|
2014-03-06 17:12:03 +00:00
|
|
|
qdep = pci_ats_queue_depth(pdev);
|
2009-05-18 05:51:37 +00:00
|
|
|
qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&device_domain_lock, flags);
|
|
|
|
}
|
|
|
|
|
2009-05-10 18:58:49 +00:00
|
|
|
static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
|
2014-03-05 17:09:32 +00:00
|
|
|
unsigned long pfn, unsigned int pages, int ih, int map)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
2009-05-18 05:51:36 +00:00
|
|
|
unsigned int mask = ilog2(__roundup_pow_of_two(pages));
|
2009-06-28 14:33:46 +00:00
|
|
|
uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
|
|
|
BUG_ON(pages == 0);
|
|
|
|
|
2014-03-05 17:09:32 +00:00
|
|
|
if (ih)
|
|
|
|
ih = 1 << 6;
|
2007-10-21 23:41:49 +00:00
|
|
|
/*
|
2009-05-18 05:51:36 +00:00
|
|
|
* Fallback to domain selective flush if no PSI support or the size is
|
|
|
|
* too big.
|
2007-10-21 23:41:49 +00:00
|
|
|
* PSI requires page size to be 2 ^ x, and the base address is naturally
|
|
|
|
* aligned to the size
|
|
|
|
*/
|
2009-05-18 05:51:36 +00:00
|
|
|
if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
|
|
|
|
iommu->flush.flush_iotlb(iommu, did, 0, 0,
|
2009-05-10 18:58:49 +00:00
|
|
|
DMA_TLB_DSI_FLUSH);
|
2009-05-18 05:51:36 +00:00
|
|
|
else
|
2014-03-05 17:09:32 +00:00
|
|
|
iommu->flush.flush_iotlb(iommu, did, addr | ih, mask,
|
2009-05-18 05:51:36 +00:00
|
|
|
DMA_TLB_PSI_FLUSH);
|
2009-06-29 03:31:45 +00:00
|
|
|
|
|
|
|
/*
|
2010-04-01 10:24:40 +00:00
|
|
|
* In caching mode, changes of pages from non-present to present require
|
|
|
|
* flush. However, device IOTLB doesn't need to be flushed in this case.
|
2009-06-29 03:31:45 +00:00
|
|
|
*/
|
2010-04-01 10:24:40 +00:00
|
|
|
if (!cap_caching_mode(iommu->cap) || !map)
|
2009-05-18 05:51:37 +00:00
|
|
|
iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2008-02-08 12:18:38 +00:00
|
|
|
static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
u32 pmen;
|
|
|
|
unsigned long flags;
|
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_lock_irqsave(&iommu->register_lock, flags);
|
2008-02-08 12:18:38 +00:00
|
|
|
pmen = readl(iommu->reg + DMAR_PMEN_REG);
|
|
|
|
pmen &= ~DMA_PMEN_EPM;
|
|
|
|
writel(pmen, iommu->reg + DMAR_PMEN_REG);
|
|
|
|
|
|
|
|
/* wait for the protected region status bit to clear */
|
|
|
|
IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
|
|
|
|
readl, !(pmen & DMA_PMEN_PRS), pmen);
|
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
|
2008-02-08 12:18:38 +00:00
|
|
|
}
|
|
|
|
|
2014-07-11 06:19:33 +00:00
|
|
|
static void iommu_enable_translation(struct intel_iommu *iommu)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
|
|
|
u32 sts;
|
|
|
|
unsigned long flags;
|
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_lock_irqsave(&iommu->register_lock, flags);
|
2009-05-10 19:30:58 +00:00
|
|
|
iommu->gcmd |= DMA_GCMD_TE;
|
|
|
|
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
|
|
|
/* Make sure hardware complete it */
|
|
|
|
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
|
2009-05-10 19:30:58 +00:00
|
|
|
readl, (sts & DMA_GSTS_TES), sts);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2014-07-11 06:19:33 +00:00
|
|
|
static void iommu_disable_translation(struct intel_iommu *iommu)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
|
|
|
u32 sts;
|
|
|
|
unsigned long flag;
|
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_lock_irqsave(&iommu->register_lock, flag);
|
2007-10-21 23:41:49 +00:00
|
|
|
iommu->gcmd &= ~DMA_GCMD_TE;
|
|
|
|
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
|
|
|
|
|
|
|
|
/* Make sure hardware complete it */
|
|
|
|
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
|
2009-05-10 19:30:58 +00:00
|
|
|
readl, (!(sts & DMA_GSTS_TES)), sts);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2007-10-21 23:41:54 +00:00
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
static int iommu_init_domains(struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
unsigned long ndomains;
|
|
|
|
unsigned long nlongs;
|
|
|
|
|
|
|
|
ndomains = cap_ndoms(iommu->cap);
|
2014-01-06 06:18:11 +00:00
|
|
|
pr_debug("IOMMU%d: Number of Domains supported <%ld>\n",
|
|
|
|
iommu->seq_id, ndomains);
|
2007-10-21 23:41:49 +00:00
|
|
|
nlongs = BITS_TO_LONGS(ndomains);
|
|
|
|
|
2009-08-20 20:51:34 +00:00
|
|
|
spin_lock_init(&iommu->lock);
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
/* TBD: there might be 64K domains,
|
|
|
|
* consider other allocation for future chip
|
|
|
|
*/
|
|
|
|
iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
|
|
|
|
if (!iommu->domain_ids) {
|
2014-01-06 06:18:11 +00:00
|
|
|
pr_err("IOMMU%d: allocating domain id array failed\n",
|
|
|
|
iommu->seq_id);
|
2007-10-21 23:41:49 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!iommu->domains) {
|
2014-01-06 06:18:11 +00:00
|
|
|
pr_err("IOMMU%d: allocating domain array failed\n",
|
|
|
|
iommu->seq_id);
|
|
|
|
kfree(iommu->domain_ids);
|
|
|
|
iommu->domain_ids = NULL;
|
2007-10-21 23:41:49 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* if Caching mode is set, then invalid translations are tagged
|
|
|
|
* with domainid 0. Hence we need to pre-allocate it.
|
|
|
|
*/
|
|
|
|
if (cap_caching_mode(iommu->cap))
|
|
|
|
set_bit(0, iommu->domain_ids);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-11-09 14:48:02 +00:00
|
|
|
static void disable_dmar_iommu(struct intel_iommu *iommu)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
|
|
|
struct dmar_domain *domain;
|
2014-07-11 06:19:30 +00:00
|
|
|
int i;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2009-08-20 20:51:34 +00:00
|
|
|
if ((iommu->domains) && (iommu->domain_ids)) {
|
2010-03-11 22:04:08 +00:00
|
|
|
for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
|
2014-02-19 06:07:30 +00:00
|
|
|
/*
|
|
|
|
* Domain id 0 is reserved for invalid translation
|
|
|
|
* if hardware supports caching mode.
|
|
|
|
*/
|
|
|
|
if (cap_caching_mode(iommu->cap) && i == 0)
|
|
|
|
continue;
|
|
|
|
|
2009-08-20 20:51:34 +00:00
|
|
|
domain = iommu->domains[i];
|
|
|
|
clear_bit(i, iommu->domain_ids);
|
2014-07-11 06:19:31 +00:00
|
|
|
if (domain_detach_iommu(domain, iommu) == 0 &&
|
|
|
|
!domain_type_is_vm(domain))
|
2014-02-19 06:07:28 +00:00
|
|
|
domain_exit(domain);
|
2008-12-08 15:03:27 +00:00
|
|
|
}
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (iommu->gcmd & DMA_GCMD_TE)
|
|
|
|
iommu_disable_translation(iommu);
|
2014-11-09 14:48:02 +00:00
|
|
|
}
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2014-11-09 14:48:02 +00:00
|
|
|
static void free_dmar_iommu(struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
if ((iommu->domains) && (iommu->domain_ids)) {
|
|
|
|
kfree(iommu->domains);
|
|
|
|
kfree(iommu->domain_ids);
|
|
|
|
iommu->domains = NULL;
|
|
|
|
iommu->domain_ids = NULL;
|
|
|
|
}
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2008-12-08 03:06:32 +00:00
|
|
|
g_iommus[iommu->seq_id] = NULL;
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
/* free context mapping */
|
|
|
|
free_context_table(iommu);
|
|
|
|
}
|
|
|
|
|
2014-07-11 06:19:27 +00:00
|
|
|
static struct dmar_domain *alloc_domain(int flags)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
2014-02-19 06:07:28 +00:00
|
|
|
/* domain id for virtual machine, it won't be set in context */
|
|
|
|
static atomic_t vm_domid = ATOMIC_INIT(0);
|
2007-10-21 23:41:49 +00:00
|
|
|
struct dmar_domain *domain;
|
|
|
|
|
|
|
|
domain = alloc_domain_mem();
|
|
|
|
if (!domain)
|
|
|
|
return NULL;
|
|
|
|
|
2014-07-11 06:19:27 +00:00
|
|
|
memset(domain, 0, sizeof(*domain));
|
2009-10-02 18:01:24 +00:00
|
|
|
domain->nid = -1;
|
2014-07-11 06:19:27 +00:00
|
|
|
domain->flags = flags;
|
2014-02-19 06:07:28 +00:00
|
|
|
spin_lock_init(&domain->iommu_lock);
|
|
|
|
INIT_LIST_HEAD(&domain->devices);
|
2014-07-11 06:19:27 +00:00
|
|
|
if (flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
|
2014-02-19 06:07:28 +00:00
|
|
|
domain->id = atomic_inc_return(&vm_domid);
|
2009-06-19 20:47:29 +00:00
|
|
|
|
|
|
|
return domain;
|
|
|
|
}
|
|
|
|
|
2014-07-11 06:19:28 +00:00
|
|
|
static int __iommu_attach_domain(struct dmar_domain *domain,
|
|
|
|
struct intel_iommu *iommu)
|
2009-06-19 20:47:29 +00:00
|
|
|
{
|
|
|
|
int num;
|
|
|
|
unsigned long ndomains;
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
ndomains = cap_ndoms(iommu->cap);
|
|
|
|
num = find_first_zero_bit(iommu->domain_ids, ndomains);
|
2014-07-11 06:19:28 +00:00
|
|
|
if (num < ndomains) {
|
|
|
|
set_bit(num, iommu->domain_ids);
|
|
|
|
iommu->domains[num] = domain;
|
|
|
|
} else {
|
|
|
|
num = -ENOSPC;
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2014-07-11 06:19:28 +00:00
|
|
|
return num;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int iommu_attach_domain(struct dmar_domain *domain,
|
|
|
|
struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
int num;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
num = __iommu_attach_domain(domain, iommu);
|
2014-07-11 06:19:29 +00:00
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
2014-07-11 06:19:28 +00:00
|
|
|
if (num < 0)
|
|
|
|
pr_err("IOMMU: no free domain ids\n");
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2014-07-11 06:19:28 +00:00
|
|
|
return num;
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2014-07-11 06:19:29 +00:00
|
|
|
static int iommu_attach_vm_domain(struct dmar_domain *domain,
|
|
|
|
struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
int num;
|
|
|
|
unsigned long ndomains;
|
|
|
|
|
|
|
|
ndomains = cap_ndoms(iommu->cap);
|
|
|
|
for_each_set_bit(num, iommu->domain_ids, ndomains)
|
|
|
|
if (iommu->domains[num] == domain)
|
|
|
|
return num;
|
|
|
|
|
|
|
|
return __iommu_attach_domain(domain, iommu);
|
|
|
|
}
|
|
|
|
|
2009-06-19 20:47:29 +00:00
|
|
|
static void iommu_detach_domain(struct dmar_domain *domain,
|
|
|
|
struct intel_iommu *iommu)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
|
|
|
unsigned long flags;
|
2009-06-19 20:47:29 +00:00
|
|
|
int num, ndomains;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2008-12-08 07:29:22 +00:00
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
2014-07-11 06:19:28 +00:00
|
|
|
if (domain_type_is_vm_or_si(domain)) {
|
|
|
|
ndomains = cap_ndoms(iommu->cap);
|
|
|
|
for_each_set_bit(num, iommu->domain_ids, ndomains) {
|
|
|
|
if (iommu->domains[num] == domain) {
|
|
|
|
clear_bit(num, iommu->domain_ids);
|
|
|
|
iommu->domains[num] = NULL;
|
|
|
|
break;
|
|
|
|
}
|
2009-06-19 20:47:29 +00:00
|
|
|
}
|
2014-07-11 06:19:28 +00:00
|
|
|
} else {
|
|
|
|
clear_bit(domain->id, iommu->domain_ids);
|
|
|
|
iommu->domains[domain->id] = NULL;
|
2009-06-19 20:47:29 +00:00
|
|
|
}
|
2008-12-08 07:29:22 +00:00
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2014-07-11 06:19:28 +00:00
|
|
|
static void domain_attach_iommu(struct dmar_domain *domain,
|
|
|
|
struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&domain->iommu_lock, flags);
|
|
|
|
if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) {
|
|
|
|
domain->iommu_count++;
|
|
|
|
if (domain->iommu_count == 1)
|
|
|
|
domain->nid = iommu->node;
|
|
|
|
domain_update_iommu_cap(domain);
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&domain->iommu_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int domain_detach_iommu(struct dmar_domain *domain,
|
|
|
|
struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
int count = INT_MAX;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&domain->iommu_lock, flags);
|
|
|
|
if (test_and_clear_bit(iommu->seq_id, domain->iommu_bmp)) {
|
|
|
|
count = --domain->iommu_count;
|
|
|
|
domain_update_iommu_cap(domain);
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&domain->iommu_lock, flags);
|
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
static struct iova_domain reserved_iova_list;
|
2008-03-04 22:59:31 +00:00
|
|
|
static struct lock_class_key reserved_rbtree_key;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2011-03-21 18:04:24 +00:00
|
|
|
static int dmar_init_reserved_ranges(void)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
|
|
|
struct pci_dev *pdev = NULL;
|
|
|
|
struct iova *iova;
|
|
|
|
int i;
|
|
|
|
|
2015-01-12 17:51:16 +00:00
|
|
|
init_iova_domain(&reserved_iova_list, VTD_PAGE_SIZE, IOVA_START_PFN,
|
|
|
|
DMA_32BIT_PFN);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2008-03-04 22:59:31 +00:00
|
|
|
lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
|
|
|
|
&reserved_rbtree_key);
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
/* IOAPIC ranges shouldn't be accessed by DMA */
|
|
|
|
iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
|
|
|
|
IOVA_PFN(IOAPIC_RANGE_END));
|
2011-03-21 18:04:24 +00:00
|
|
|
if (!iova) {
|
2007-10-21 23:41:49 +00:00
|
|
|
printk(KERN_ERR "Reserve IOAPIC range failed\n");
|
2011-03-21 18:04:24 +00:00
|
|
|
return -ENODEV;
|
|
|
|
}
|
2007-10-21 23:41:49 +00:00
|
|
|
|
|
|
|
/* Reserve all PCI MMIO to avoid peer-to-peer access */
|
|
|
|
for_each_pci_dev(pdev) {
|
|
|
|
struct resource *r;
|
|
|
|
|
|
|
|
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
|
|
|
|
r = &pdev->resource[i];
|
|
|
|
if (!r->flags || !(r->flags & IORESOURCE_MEM))
|
|
|
|
continue;
|
2009-06-28 15:00:42 +00:00
|
|
|
iova = reserve_iova(&reserved_iova_list,
|
|
|
|
IOVA_PFN(r->start),
|
|
|
|
IOVA_PFN(r->end));
|
2011-03-21 18:04:24 +00:00
|
|
|
if (!iova) {
|
2007-10-21 23:41:49 +00:00
|
|
|
printk(KERN_ERR "Reserve iova failed\n");
|
2011-03-21 18:04:24 +00:00
|
|
|
return -ENODEV;
|
|
|
|
}
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
}
|
2011-03-21 18:04:24 +00:00
|
|
|
return 0;
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void domain_reserve_special_ranges(struct dmar_domain *domain)
|
|
|
|
{
|
|
|
|
copy_reserved_iova(&reserved_iova_list, &domain->iovad);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int guestwidth_to_adjustwidth(int gaw)
|
|
|
|
{
|
|
|
|
int agaw;
|
|
|
|
int r = (gaw - 12) % 9;
|
|
|
|
|
|
|
|
if (r == 0)
|
|
|
|
agaw = gaw;
|
|
|
|
else
|
|
|
|
agaw = gaw + 9 - r;
|
|
|
|
if (agaw > 64)
|
|
|
|
agaw = 64;
|
|
|
|
return agaw;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int domain_init(struct dmar_domain *domain, int guest_width)
|
|
|
|
{
|
|
|
|
struct intel_iommu *iommu;
|
|
|
|
int adjust_width, agaw;
|
|
|
|
unsigned long sagaw;
|
|
|
|
|
2015-01-12 17:51:16 +00:00
|
|
|
init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN,
|
|
|
|
DMA_32BIT_PFN);
|
2007-10-21 23:41:49 +00:00
|
|
|
domain_reserve_special_ranges(domain);
|
|
|
|
|
|
|
|
/* calculate AGAW */
|
2008-12-08 07:29:22 +00:00
|
|
|
iommu = domain_get_iommu(domain);
|
2007-10-21 23:41:49 +00:00
|
|
|
if (guest_width > cap_mgaw(iommu->cap))
|
|
|
|
guest_width = cap_mgaw(iommu->cap);
|
|
|
|
domain->gaw = guest_width;
|
|
|
|
adjust_width = guestwidth_to_adjustwidth(guest_width);
|
|
|
|
agaw = width_to_agaw(adjust_width);
|
|
|
|
sagaw = cap_sagaw(iommu->cap);
|
|
|
|
if (!test_bit(agaw, &sagaw)) {
|
|
|
|
/* hardware doesn't support it, choose a bigger one */
|
|
|
|
pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
|
|
|
|
agaw = find_next_bit(&sagaw, 5, agaw);
|
|
|
|
if (agaw >= 5)
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
domain->agaw = agaw;
|
|
|
|
|
2008-12-08 07:49:06 +00:00
|
|
|
if (ecap_coherent(iommu->ecap))
|
|
|
|
domain->iommu_coherency = 1;
|
|
|
|
else
|
|
|
|
domain->iommu_coherency = 0;
|
|
|
|
|
2009-03-18 07:33:05 +00:00
|
|
|
if (ecap_sc_support(iommu->ecap))
|
|
|
|
domain->iommu_snooping = 1;
|
|
|
|
else
|
|
|
|
domain->iommu_snooping = 0;
|
|
|
|
|
2014-03-19 10:38:49 +00:00
|
|
|
if (intel_iommu_superpage)
|
|
|
|
domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
|
|
|
|
else
|
|
|
|
domain->iommu_superpage = 0;
|
|
|
|
|
2009-10-02 18:01:24 +00:00
|
|
|
domain->nid = iommu->node;
|
2008-12-08 14:51:37 +00:00
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
/* always allocate the top pgd */
|
2009-10-02 18:01:24 +00:00
|
|
|
domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
|
2007-10-21 23:41:49 +00:00
|
|
|
if (!domain->pgd)
|
|
|
|
return -ENOMEM;
|
2008-10-17 01:02:32 +00:00
|
|
|
__iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
|
2007-10-21 23:41:49 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void domain_exit(struct dmar_domain *domain)
|
|
|
|
{
|
2014-03-05 17:09:32 +00:00
|
|
|
struct page *freelist = NULL;
|
2015-03-04 18:30:10 +00:00
|
|
|
int i;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
|
|
|
/* Domain 0 is reserved, so dont process it */
|
|
|
|
if (!domain)
|
|
|
|
return;
|
|
|
|
|
2011-05-24 11:02:41 +00:00
|
|
|
/* Flush any lazy unmaps that may reference this domain */
|
|
|
|
if (!intel_iommu_strict)
|
|
|
|
flush_unmaps_timeout(0);
|
|
|
|
|
2014-02-19 06:07:28 +00:00
|
|
|
/* remove associated devices */
|
2007-10-21 23:41:49 +00:00
|
|
|
domain_remove_dev_info(domain);
|
2014-02-19 06:07:28 +00:00
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
/* destroy iovas */
|
|
|
|
put_iova_domain(&domain->iovad);
|
|
|
|
|
2014-03-05 17:09:32 +00:00
|
|
|
freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2014-02-19 06:07:28 +00:00
|
|
|
/* clear attached or cached domains */
|
2014-02-19 06:07:34 +00:00
|
|
|
rcu_read_lock();
|
2015-03-04 18:30:10 +00:00
|
|
|
for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus)
|
|
|
|
iommu_detach_domain(domain, g_iommus[i]);
|
2014-02-19 06:07:34 +00:00
|
|
|
rcu_read_unlock();
|
2009-06-19 20:47:29 +00:00
|
|
|
|
2014-03-05 17:09:32 +00:00
|
|
|
dma_free_pagelist(freelist);
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
free_domain_mem(domain);
|
|
|
|
}
|
|
|
|
|
2014-03-09 19:52:30 +00:00
|
|
|
static int domain_context_mapping_one(struct dmar_domain *domain,
|
|
|
|
struct intel_iommu *iommu,
|
|
|
|
u8 bus, u8 devfn, int translation)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
|
|
|
struct context_entry *context;
|
|
|
|
unsigned long flags;
|
2008-12-08 15:08:15 +00:00
|
|
|
struct dma_pte *pgd;
|
|
|
|
int id;
|
|
|
|
int agaw;
|
2009-05-18 05:51:37 +00:00
|
|
|
struct device_domain_info *info = NULL;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
|
|
|
pr_debug("Set context mapping for %02x:%02x.%d\n",
|
|
|
|
bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
|
2009-04-25 00:30:20 +00:00
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
BUG_ON(!domain->pgd);
|
2009-04-25 00:30:20 +00:00
|
|
|
BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
|
|
|
|
translation != CONTEXT_TT_MULTI_LEVEL);
|
2008-12-08 15:00:00 +00:00
|
|
|
|
2015-02-13 14:35:21 +00:00
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
context = iommu_context_addr(iommu, bus, devfn, 1);
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
2007-10-21 23:41:49 +00:00
|
|
|
if (!context)
|
|
|
|
return -ENOMEM;
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
2008-11-21 16:54:46 +00:00
|
|
|
if (context_present(context)) {
|
2007-10-21 23:41:49 +00:00
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-12-08 15:08:15 +00:00
|
|
|
id = domain->id;
|
|
|
|
pgd = domain->pgd;
|
|
|
|
|
2014-07-11 06:19:27 +00:00
|
|
|
if (domain_type_is_vm_or_si(domain)) {
|
2014-07-11 06:19:29 +00:00
|
|
|
if (domain_type_is_vm(domain)) {
|
|
|
|
id = iommu_attach_vm_domain(domain, iommu);
|
2014-07-11 06:19:28 +00:00
|
|
|
if (id < 0) {
|
2008-12-08 15:08:15 +00:00
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
2014-07-11 06:19:28 +00:00
|
|
|
pr_err("IOMMU: no free domain ids\n");
|
2008-12-08 15:08:15 +00:00
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Skip top levels of page tables for
|
|
|
|
* iommu which has less agaw than default.
|
2009-12-02 20:06:34 +00:00
|
|
|
* Unnecessary for PT mode.
|
2008-12-08 15:08:15 +00:00
|
|
|
*/
|
2009-12-02 20:06:34 +00:00
|
|
|
if (translation != CONTEXT_TT_PASS_THROUGH) {
|
|
|
|
for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
|
|
|
|
pgd = phys_to_virt(dma_pte_addr(pgd));
|
|
|
|
if (!dma_pte_present(pgd)) {
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
2008-12-08 15:08:15 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
context_set_domain_id(context, id);
|
2009-04-25 00:30:20 +00:00
|
|
|
|
2009-05-18 05:51:37 +00:00
|
|
|
if (translation != CONTEXT_TT_PASS_THROUGH) {
|
2014-03-09 19:52:30 +00:00
|
|
|
info = iommu_support_dev_iotlb(domain, iommu, bus, devfn);
|
2009-05-18 05:51:37 +00:00
|
|
|
translation = info ? CONTEXT_TT_DEV_IOTLB :
|
|
|
|
CONTEXT_TT_MULTI_LEVEL;
|
|
|
|
}
|
2009-04-25 00:30:20 +00:00
|
|
|
/*
|
|
|
|
* In pass through mode, AW must be programmed to indicate the largest
|
|
|
|
* AGAW value supported by hardware. And ASR is ignored by hardware.
|
|
|
|
*/
|
2009-05-18 05:51:37 +00:00
|
|
|
if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
|
2009-04-25 00:30:20 +00:00
|
|
|
context_set_address_width(context, iommu->msagaw);
|
2009-05-18 05:51:37 +00:00
|
|
|
else {
|
|
|
|
context_set_address_root(context, virt_to_phys(pgd));
|
|
|
|
context_set_address_width(context, iommu->agaw);
|
|
|
|
}
|
2009-04-25 00:30:20 +00:00
|
|
|
|
|
|
|
context_set_translation_type(context, translation);
|
2008-11-21 16:54:46 +00:00
|
|
|
context_set_fault_enable(context);
|
|
|
|
context_set_present(context);
|
2008-12-08 15:00:00 +00:00
|
|
|
domain_flush_cache(domain, context, sizeof(*context));
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2009-05-10 16:16:06 +00:00
|
|
|
/*
|
|
|
|
* It's a non-present to present mapping. If hardware doesn't cache
|
|
|
|
* non-present entry we only need to flush the write-buffer. If the
|
|
|
|
* _does_ cache non-present entries, then it does so in the special
|
|
|
|
* domain #0, which we have to flush:
|
|
|
|
*/
|
|
|
|
if (cap_caching_mode(iommu->cap)) {
|
|
|
|
iommu->flush.flush_context(iommu, 0,
|
|
|
|
(((u16)bus) << 8) | devfn,
|
|
|
|
DMA_CCMD_MASK_NOBIT,
|
|
|
|
DMA_CCMD_DEVICE_INVL);
|
2014-07-11 06:19:26 +00:00
|
|
|
iommu->flush.flush_iotlb(iommu, id, 0, 0, DMA_TLB_DSI_FLUSH);
|
2009-05-10 16:16:06 +00:00
|
|
|
} else {
|
2007-10-21 23:41:49 +00:00
|
|
|
iommu_flush_write_buffer(iommu);
|
2009-05-10 16:16:06 +00:00
|
|
|
}
|
2009-05-18 05:51:37 +00:00
|
|
|
iommu_enable_dev_iotlb(info);
|
2007-10-21 23:41:49 +00:00
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
2008-12-08 14:51:37 +00:00
|
|
|
|
2014-07-11 06:19:28 +00:00
|
|
|
domain_attach_iommu(domain, iommu);
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-07-03 15:51:43 +00:00
|
|
|
struct domain_context_mapping_data {
|
|
|
|
struct dmar_domain *domain;
|
|
|
|
struct intel_iommu *iommu;
|
|
|
|
int translation;
|
|
|
|
};
|
|
|
|
|
|
|
|
static int domain_context_mapping_cb(struct pci_dev *pdev,
|
|
|
|
u16 alias, void *opaque)
|
|
|
|
{
|
|
|
|
struct domain_context_mapping_data *data = opaque;
|
|
|
|
|
|
|
|
return domain_context_mapping_one(data->domain, data->iommu,
|
|
|
|
PCI_BUS_NUM(alias), alias & 0xff,
|
|
|
|
data->translation);
|
|
|
|
}
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
static int
|
2014-03-09 22:24:46 +00:00
|
|
|
domain_context_mapping(struct dmar_domain *domain, struct device *dev,
|
|
|
|
int translation)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
2014-03-09 19:52:30 +00:00
|
|
|
struct intel_iommu *iommu;
|
2014-03-09 21:00:57 +00:00
|
|
|
u8 bus, devfn;
|
2014-07-03 15:51:43 +00:00
|
|
|
struct domain_context_mapping_data data;
|
2014-03-09 19:52:30 +00:00
|
|
|
|
2014-03-09 22:24:46 +00:00
|
|
|
iommu = device_to_iommu(dev, &bus, &devfn);
|
2014-03-09 19:52:30 +00:00
|
|
|
if (!iommu)
|
|
|
|
return -ENODEV;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2014-07-03 15:51:43 +00:00
|
|
|
if (!dev_is_pci(dev))
|
|
|
|
return domain_context_mapping_one(domain, iommu, bus, devfn,
|
2009-04-25 00:30:20 +00:00
|
|
|
translation);
|
2014-07-03 15:51:43 +00:00
|
|
|
|
|
|
|
data.domain = domain;
|
|
|
|
data.iommu = iommu;
|
|
|
|
data.translation = translation;
|
|
|
|
|
|
|
|
return pci_for_each_dma_alias(to_pci_dev(dev),
|
|
|
|
&domain_context_mapping_cb, &data);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int domain_context_mapped_cb(struct pci_dev *pdev,
|
|
|
|
u16 alias, void *opaque)
|
|
|
|
{
|
|
|
|
struct intel_iommu *iommu = opaque;
|
|
|
|
|
|
|
|
return !device_context_mapped(iommu, PCI_BUS_NUM(alias), alias & 0xff);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2014-03-09 22:24:46 +00:00
|
|
|
static int domain_context_mapped(struct device *dev)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
2008-12-08 15:00:00 +00:00
|
|
|
struct intel_iommu *iommu;
|
2014-03-09 21:00:57 +00:00
|
|
|
u8 bus, devfn;
|
2008-12-08 15:00:00 +00:00
|
|
|
|
2014-03-09 22:24:46 +00:00
|
|
|
iommu = device_to_iommu(dev, &bus, &devfn);
|
2008-12-08 15:00:00 +00:00
|
|
|
if (!iommu)
|
|
|
|
return -ENODEV;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2014-07-03 15:51:43 +00:00
|
|
|
if (!dev_is_pci(dev))
|
|
|
|
return device_context_mapped(iommu, bus, devfn);
|
2014-03-09 22:24:46 +00:00
|
|
|
|
2014-07-03 15:51:43 +00:00
|
|
|
return !pci_for_each_dma_alias(to_pci_dev(dev),
|
|
|
|
domain_context_mapped_cb, iommu);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2009-08-04 22:09:37 +00:00
|
|
|
/* Returns a number of VTD pages, but aligned to MM page size */
|
|
|
|
static inline unsigned long aligned_nrpages(unsigned long host_addr,
|
|
|
|
size_t size)
|
|
|
|
{
|
|
|
|
host_addr &= ~PAGE_MASK;
|
|
|
|
return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
|
|
|
|
}
|
|
|
|
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
/* Return largest possible superpage level for a given mapping */
|
|
|
|
static inline int hardware_largepage_caps(struct dmar_domain *domain,
|
|
|
|
unsigned long iov_pfn,
|
|
|
|
unsigned long phy_pfn,
|
|
|
|
unsigned long pages)
|
|
|
|
{
|
|
|
|
int support, level = 1;
|
|
|
|
unsigned long pfnmerge;
|
|
|
|
|
|
|
|
support = domain->iommu_superpage;
|
|
|
|
|
|
|
|
/* To use a large page, the virtual *and* physical addresses
|
|
|
|
must be aligned to 2MiB/1GiB/etc. Lower bits set in either
|
|
|
|
of them will mean we have to use smaller pages. So just
|
|
|
|
merge them and check both at once. */
|
|
|
|
pfnmerge = iov_pfn | phy_pfn;
|
|
|
|
|
|
|
|
while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
|
|
|
|
pages >>= VTD_STRIDE_SHIFT;
|
|
|
|
if (!pages)
|
|
|
|
break;
|
|
|
|
pfnmerge >>= VTD_STRIDE_SHIFT;
|
|
|
|
level++;
|
|
|
|
support--;
|
|
|
|
}
|
|
|
|
return level;
|
|
|
|
}
|
|
|
|
|
2009-06-29 11:30:54 +00:00
|
|
|
static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
|
|
|
|
struct scatterlist *sg, unsigned long phys_pfn,
|
|
|
|
unsigned long nr_pages, int prot)
|
2009-06-29 10:17:38 +00:00
|
|
|
{
|
|
|
|
struct dma_pte *first_pte = NULL, *pte = NULL;
|
2009-06-29 11:30:54 +00:00
|
|
|
phys_addr_t uninitialized_var(pteval);
|
2014-11-26 01:42:10 +00:00
|
|
|
unsigned long sg_res = 0;
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
unsigned int largepage_lvl = 0;
|
|
|
|
unsigned long lvl_pages = 0;
|
2009-06-29 10:17:38 +00:00
|
|
|
|
2014-07-11 06:19:35 +00:00
|
|
|
BUG_ON(!domain_pfn_supported(domain, iov_pfn + nr_pages - 1));
|
2009-06-29 10:17:38 +00:00
|
|
|
|
|
|
|
if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
|
|
|
|
|
2014-11-26 01:42:10 +00:00
|
|
|
if (!sg) {
|
|
|
|
sg_res = nr_pages;
|
2009-06-29 11:30:54 +00:00
|
|
|
pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
|
|
|
|
}
|
|
|
|
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
while (nr_pages > 0) {
|
2009-07-01 18:21:24 +00:00
|
|
|
uint64_t tmp;
|
|
|
|
|
2009-06-29 10:17:38 +00:00
|
|
|
if (!sg_res) {
|
2009-08-04 22:09:37 +00:00
|
|
|
sg_res = aligned_nrpages(sg->offset, sg->length);
|
2009-06-29 10:17:38 +00:00
|
|
|
sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
|
|
|
|
sg->dma_length = sg->length;
|
|
|
|
pteval = page_to_phys(sg_page(sg)) | prot;
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
phys_pfn = pteval >> VTD_PAGE_SHIFT;
|
2009-06-29 10:17:38 +00:00
|
|
|
}
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
|
2009-06-29 10:17:38 +00:00
|
|
|
if (!pte) {
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);
|
|
|
|
|
2014-03-19 16:07:49 +00:00
|
|
|
first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl);
|
2009-06-29 10:17:38 +00:00
|
|
|
if (!pte)
|
|
|
|
return -ENOMEM;
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
/* It is large page*/
|
2012-12-19 13:25:35 +00:00
|
|
|
if (largepage_lvl > 1) {
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
pteval |= DMA_PTE_LARGE_PAGE;
|
2014-07-11 06:19:34 +00:00
|
|
|
lvl_pages = lvl_to_nr_pages(largepage_lvl);
|
|
|
|
/*
|
|
|
|
* Ensure that old small page tables are
|
|
|
|
* removed to make room for superpage,
|
|
|
|
* if they exist.
|
|
|
|
*/
|
2012-12-19 13:25:35 +00:00
|
|
|
dma_pte_free_pagetable(domain, iov_pfn,
|
2014-07-11 06:19:34 +00:00
|
|
|
iov_pfn + lvl_pages - 1);
|
2012-12-19 13:25:35 +00:00
|
|
|
} else {
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
|
2012-12-19 13:25:35 +00:00
|
|
|
}
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
|
2009-06-29 10:17:38 +00:00
|
|
|
}
|
|
|
|
/* We don't need lock here, nobody else
|
|
|
|
* touches the iova range
|
|
|
|
*/
|
2009-07-01 19:27:03 +00:00
|
|
|
tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
|
2009-07-01 18:21:24 +00:00
|
|
|
if (tmp) {
|
2009-06-29 21:06:43 +00:00
|
|
|
static int dumps = 5;
|
2009-07-01 18:21:24 +00:00
|
|
|
printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
|
|
|
|
iov_pfn, tmp, (unsigned long long)pteval);
|
2009-06-29 21:06:43 +00:00
|
|
|
if (dumps) {
|
|
|
|
dumps--;
|
|
|
|
debug_dma_dump_mappings(NULL);
|
|
|
|
}
|
|
|
|
WARN_ON(1);
|
|
|
|
}
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
|
|
|
|
lvl_pages = lvl_to_nr_pages(largepage_lvl);
|
|
|
|
|
|
|
|
BUG_ON(nr_pages < lvl_pages);
|
|
|
|
BUG_ON(sg_res < lvl_pages);
|
|
|
|
|
|
|
|
nr_pages -= lvl_pages;
|
|
|
|
iov_pfn += lvl_pages;
|
|
|
|
phys_pfn += lvl_pages;
|
|
|
|
pteval += lvl_pages * VTD_PAGE_SIZE;
|
|
|
|
sg_res -= lvl_pages;
|
|
|
|
|
|
|
|
/* If the next PTE would be the first in a new page, then we
|
|
|
|
need to flush the cache on the entries we've just written.
|
|
|
|
And then we'll need to recalculate 'pte', so clear it and
|
|
|
|
let it get set again in the if (!pte) block above.
|
|
|
|
|
|
|
|
If we're done (!nr_pages) we need to flush the cache too.
|
|
|
|
|
|
|
|
Also if we've been setting superpages, we may need to
|
|
|
|
recalculate 'pte' and switch back to smaller pages for the
|
|
|
|
end of the mapping, if the trailing size is not enough to
|
|
|
|
use another superpage (i.e. sg_res < lvl_pages). */
|
2009-06-29 10:17:38 +00:00
|
|
|
pte++;
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
if (!nr_pages || first_pte_in_page(pte) ||
|
|
|
|
(largepage_lvl > 1 && sg_res < lvl_pages)) {
|
2009-06-29 10:17:38 +00:00
|
|
|
domain_flush_cache(domain, first_pte,
|
|
|
|
(void *)pte - (void *)first_pte);
|
|
|
|
pte = NULL;
|
|
|
|
}
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
|
|
|
|
if (!sg_res && nr_pages)
|
2009-06-29 10:17:38 +00:00
|
|
|
sg = sg_next(sg);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-06-29 11:30:54 +00:00
|
|
|
static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
|
|
|
|
struct scatterlist *sg, unsigned long nr_pages,
|
|
|
|
int prot)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
2009-06-29 11:30:54 +00:00
|
|
|
return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
|
|
|
|
}
|
2009-06-28 19:38:49 +00:00
|
|
|
|
2009-06-29 11:30:54 +00:00
|
|
|
static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
|
|
|
|
unsigned long phys_pfn, unsigned long nr_pages,
|
|
|
|
int prot)
|
|
|
|
{
|
|
|
|
return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2008-12-08 14:51:37 +00:00
|
|
|
static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
2008-12-08 14:51:37 +00:00
|
|
|
if (!iommu)
|
|
|
|
return;
|
2008-12-08 07:29:22 +00:00
|
|
|
|
|
|
|
clear_context_table(iommu, bus, devfn);
|
|
|
|
iommu->flush.flush_context(iommu, 0, 0, 0,
|
2009-05-10 16:16:06 +00:00
|
|
|
DMA_CCMD_GLOBAL_INVL);
|
2009-05-10 18:58:49 +00:00
|
|
|
iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2012-05-25 16:43:02 +00:00
|
|
|
static inline void unlink_domain_info(struct device_domain_info *info)
|
|
|
|
{
|
|
|
|
assert_spin_locked(&device_domain_lock);
|
|
|
|
list_del(&info->link);
|
|
|
|
list_del(&info->global);
|
|
|
|
if (info->dev)
|
2014-03-06 17:12:03 +00:00
|
|
|
info->dev->archdata.iommu = NULL;
|
2012-05-25 16:43:02 +00:00
|
|
|
}
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
static void domain_remove_dev_info(struct dmar_domain *domain)
|
|
|
|
{
|
2014-05-20 12:37:47 +00:00
|
|
|
struct device_domain_info *info, *tmp;
|
2014-07-11 06:19:28 +00:00
|
|
|
unsigned long flags;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
|
|
|
spin_lock_irqsave(&device_domain_lock, flags);
|
2014-05-20 12:37:47 +00:00
|
|
|
list_for_each_entry_safe(info, tmp, &domain->devices, link) {
|
2012-05-25 16:43:02 +00:00
|
|
|
unlink_domain_info(info);
|
2007-10-21 23:41:49 +00:00
|
|
|
spin_unlock_irqrestore(&device_domain_lock, flags);
|
|
|
|
|
2009-05-18 05:51:37 +00:00
|
|
|
iommu_disable_dev_iotlb(info);
|
2014-03-09 20:33:06 +00:00
|
|
|
iommu_detach_dev(info->iommu, info->bus, info->devfn);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2014-07-11 06:19:27 +00:00
|
|
|
if (domain_type_is_vm(domain)) {
|
2014-03-09 20:33:06 +00:00
|
|
|
iommu_detach_dependent_devices(info->iommu, info->dev);
|
2014-07-11 06:19:28 +00:00
|
|
|
domain_detach_iommu(domain, info->iommu);
|
2014-02-19 06:07:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
free_devinfo_mem(info);
|
2007-10-21 23:41:49 +00:00
|
|
|
spin_lock_irqsave(&device_domain_lock, flags);
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&device_domain_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* find_domain
|
2014-03-06 16:19:30 +00:00
|
|
|
* Note: we use struct device->archdata.iommu stores the info
|
2007-10-21 23:41:49 +00:00
|
|
|
*/
|
2014-03-06 16:19:30 +00:00
|
|
|
static struct dmar_domain *find_domain(struct device *dev)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
|
|
|
struct device_domain_info *info;
|
|
|
|
|
|
|
|
/* No lock here, assumes no domain exit in normal case */
|
2014-03-06 16:19:30 +00:00
|
|
|
info = dev->archdata.iommu;
|
2007-10-21 23:41:49 +00:00
|
|
|
if (info)
|
|
|
|
return info->domain;
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2014-03-09 20:31:18 +00:00
|
|
|
static inline struct device_domain_info *
|
2014-02-19 06:07:26 +00:00
|
|
|
dmar_search_domain_by_dev_info(int segment, int bus, int devfn)
|
|
|
|
{
|
|
|
|
struct device_domain_info *info;
|
|
|
|
|
|
|
|
list_for_each_entry(info, &device_domain_list, global)
|
2014-03-09 20:55:54 +00:00
|
|
|
if (info->iommu->segment == segment && info->bus == bus &&
|
2014-02-19 06:07:26 +00:00
|
|
|
info->devfn == devfn)
|
2014-03-09 20:31:18 +00:00
|
|
|
return info;
|
2014-02-19 06:07:26 +00:00
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2014-03-09 20:31:18 +00:00
|
|
|
static struct dmar_domain *dmar_insert_dev_info(struct intel_iommu *iommu,
|
2014-03-09 20:55:54 +00:00
|
|
|
int bus, int devfn,
|
2014-03-09 20:11:33 +00:00
|
|
|
struct device *dev,
|
|
|
|
struct dmar_domain *domain)
|
2014-02-19 06:07:26 +00:00
|
|
|
{
|
2014-03-09 20:31:18 +00:00
|
|
|
struct dmar_domain *found = NULL;
|
2014-02-19 06:07:26 +00:00
|
|
|
struct device_domain_info *info;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
info = alloc_devinfo_mem();
|
|
|
|
if (!info)
|
2014-03-09 20:11:33 +00:00
|
|
|
return NULL;
|
2014-02-19 06:07:26 +00:00
|
|
|
|
|
|
|
info->bus = bus;
|
|
|
|
info->devfn = devfn;
|
|
|
|
info->dev = dev;
|
|
|
|
info->domain = domain;
|
2014-03-09 20:31:18 +00:00
|
|
|
info->iommu = iommu;
|
2014-02-19 06:07:26 +00:00
|
|
|
|
|
|
|
spin_lock_irqsave(&device_domain_lock, flags);
|
|
|
|
if (dev)
|
2014-03-06 17:12:03 +00:00
|
|
|
found = find_domain(dev);
|
2014-03-09 20:31:18 +00:00
|
|
|
else {
|
|
|
|
struct device_domain_info *info2;
|
2014-03-09 20:55:54 +00:00
|
|
|
info2 = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn);
|
2014-03-09 20:31:18 +00:00
|
|
|
if (info2)
|
|
|
|
found = info2->domain;
|
|
|
|
}
|
2014-02-19 06:07:26 +00:00
|
|
|
if (found) {
|
|
|
|
spin_unlock_irqrestore(&device_domain_lock, flags);
|
|
|
|
free_devinfo_mem(info);
|
2014-03-09 20:11:33 +00:00
|
|
|
/* Caller must free the original domain */
|
|
|
|
return found;
|
2014-02-19 06:07:26 +00:00
|
|
|
}
|
|
|
|
|
2014-03-09 20:11:33 +00:00
|
|
|
list_add(&info->link, &domain->devices);
|
|
|
|
list_add(&info->global, &device_domain_list);
|
|
|
|
if (dev)
|
|
|
|
dev->archdata.iommu = info;
|
|
|
|
spin_unlock_irqrestore(&device_domain_lock, flags);
|
|
|
|
|
|
|
|
return domain;
|
2014-02-19 06:07:26 +00:00
|
|
|
}
|
|
|
|
|
2014-07-03 15:51:43 +00:00
|
|
|
static int get_last_alias(struct pci_dev *pdev, u16 alias, void *opaque)
|
|
|
|
{
|
|
|
|
*(u16 *)opaque = alias;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
/* domain is initialized */
|
2014-03-09 22:44:17 +00:00
|
|
|
static struct dmar_domain *get_domain_for_dev(struct device *dev, int gaw)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
2014-07-03 15:51:43 +00:00
|
|
|
struct dmar_domain *domain, *tmp;
|
|
|
|
struct intel_iommu *iommu;
|
2014-03-09 20:31:18 +00:00
|
|
|
struct device_domain_info *info;
|
2014-07-03 15:51:43 +00:00
|
|
|
u16 dma_alias;
|
2007-10-21 23:41:49 +00:00
|
|
|
unsigned long flags;
|
2014-05-26 12:14:06 +00:00
|
|
|
u8 bus, devfn;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2014-03-09 22:44:17 +00:00
|
|
|
domain = find_domain(dev);
|
2007-10-21 23:41:49 +00:00
|
|
|
if (domain)
|
|
|
|
return domain;
|
|
|
|
|
2014-07-03 15:51:43 +00:00
|
|
|
iommu = device_to_iommu(dev, &bus, &devfn);
|
|
|
|
if (!iommu)
|
|
|
|
return NULL;
|
|
|
|
|
2014-03-09 22:44:17 +00:00
|
|
|
if (dev_is_pci(dev)) {
|
|
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
2009-04-04 00:45:37 +00:00
|
|
|
|
2014-07-03 15:51:43 +00:00
|
|
|
pci_for_each_dma_alias(pdev, get_last_alias, &dma_alias);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&device_domain_lock, flags);
|
|
|
|
info = dmar_search_domain_by_dev_info(pci_domain_nr(pdev->bus),
|
|
|
|
PCI_BUS_NUM(dma_alias),
|
|
|
|
dma_alias & 0xff);
|
|
|
|
if (info) {
|
|
|
|
iommu = info->iommu;
|
|
|
|
domain = info->domain;
|
2014-03-09 20:31:18 +00:00
|
|
|
}
|
2014-07-03 15:51:43 +00:00
|
|
|
spin_unlock_irqrestore(&device_domain_lock, flags);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2014-07-03 15:51:43 +00:00
|
|
|
/* DMA alias already has a domain, uses it */
|
|
|
|
if (info)
|
|
|
|
goto found_domain;
|
|
|
|
}
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2014-03-09 22:44:17 +00:00
|
|
|
/* Allocate and initialize new domain for the device */
|
2014-07-11 06:19:27 +00:00
|
|
|
domain = alloc_domain(0);
|
2014-02-19 06:07:26 +00:00
|
|
|
if (!domain)
|
2014-07-03 15:51:43 +00:00
|
|
|
return NULL;
|
2014-07-11 06:19:29 +00:00
|
|
|
domain->id = iommu_attach_domain(domain, iommu);
|
|
|
|
if (domain->id < 0) {
|
2011-03-04 21:52:30 +00:00
|
|
|
free_domain_mem(domain);
|
2014-07-03 15:51:43 +00:00
|
|
|
return NULL;
|
2009-06-19 20:47:29 +00:00
|
|
|
}
|
2014-07-11 06:19:28 +00:00
|
|
|
domain_attach_iommu(domain, iommu);
|
2014-07-03 15:51:43 +00:00
|
|
|
if (domain_init(domain, gaw)) {
|
|
|
|
domain_exit(domain);
|
|
|
|
return NULL;
|
2009-06-19 20:47:29 +00:00
|
|
|
}
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2014-07-03 15:51:43 +00:00
|
|
|
/* register PCI DMA alias device */
|
|
|
|
if (dev_is_pci(dev)) {
|
|
|
|
tmp = dmar_insert_dev_info(iommu, PCI_BUS_NUM(dma_alias),
|
|
|
|
dma_alias & 0xff, NULL, domain);
|
|
|
|
|
|
|
|
if (!tmp || tmp != domain) {
|
|
|
|
domain_exit(domain);
|
|
|
|
domain = tmp;
|
|
|
|
}
|
|
|
|
|
2014-03-09 20:11:33 +00:00
|
|
|
if (!domain)
|
2014-07-03 15:51:43 +00:00
|
|
|
return NULL;
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
found_domain:
|
2014-07-03 15:51:43 +00:00
|
|
|
tmp = dmar_insert_dev_info(iommu, bus, devfn, dev, domain);
|
|
|
|
|
|
|
|
if (!tmp || tmp != domain) {
|
|
|
|
domain_exit(domain);
|
|
|
|
domain = tmp;
|
|
|
|
}
|
2014-03-09 20:11:33 +00:00
|
|
|
|
|
|
|
return domain;
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2009-06-19 20:47:29 +00:00
|
|
|
static int iommu_identity_mapping;
|
2009-09-30 16:12:17 +00:00
|
|
|
#define IDENTMAP_ALL 1
|
|
|
|
#define IDENTMAP_GFX 2
|
|
|
|
#define IDENTMAP_AZALIA 4
|
2009-06-19 20:47:29 +00:00
|
|
|
|
2009-06-26 17:50:28 +00:00
|
|
|
static int iommu_domain_identity_map(struct dmar_domain *domain,
|
|
|
|
unsigned long long start,
|
|
|
|
unsigned long long end)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
2009-06-28 15:35:56 +00:00
|
|
|
unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
|
|
|
|
unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
|
|
|
|
|
|
|
|
if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
|
|
|
|
dma_to_mm_pfn(last_vpfn))) {
|
2007-10-21 23:41:49 +00:00
|
|
|
printk(KERN_ERR "IOMMU: reserve iova failed\n");
|
2009-06-26 17:50:28 +00:00
|
|
|
return -ENOMEM;
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2009-06-28 15:35:56 +00:00
|
|
|
pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
|
|
|
|
start, end, domain->id);
|
2007-10-21 23:41:49 +00:00
|
|
|
/*
|
|
|
|
* RMRR range might have overlap with physical memory range,
|
|
|
|
* clear it first
|
|
|
|
*/
|
2009-06-28 15:35:56 +00:00
|
|
|
dma_pte_clear_range(domain, first_vpfn, last_vpfn);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2009-06-28 15:35:56 +00:00
|
|
|
return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
|
|
|
|
last_vpfn - first_vpfn + 1,
|
2009-06-28 10:55:58 +00:00
|
|
|
DMA_PTE_READ|DMA_PTE_WRITE);
|
2009-06-26 17:50:28 +00:00
|
|
|
}
|
|
|
|
|
2014-03-09 22:48:15 +00:00
|
|
|
static int iommu_prepare_identity_map(struct device *dev,
|
2009-06-26 17:50:28 +00:00
|
|
|
unsigned long long start,
|
|
|
|
unsigned long long end)
|
|
|
|
{
|
|
|
|
struct dmar_domain *domain;
|
|
|
|
int ret;
|
|
|
|
|
2014-03-09 22:48:15 +00:00
|
|
|
domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
|
2009-06-26 17:50:28 +00:00
|
|
|
if (!domain)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2009-08-04 15:19:20 +00:00
|
|
|
/* For _hardware_ passthrough, don't bother. But for software
|
|
|
|
passthrough, we do it anyway -- it may indicate a memory
|
|
|
|
range which is reserved in E820, so which didn't get set
|
|
|
|
up to start with in si_domain */
|
|
|
|
if (domain == si_domain && hw_pass_through) {
|
|
|
|
printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
|
2014-03-09 22:48:15 +00:00
|
|
|
dev_name(dev), start, end);
|
2009-08-04 15:19:20 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
printk(KERN_INFO
|
|
|
|
"IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
|
2014-03-09 22:48:15 +00:00
|
|
|
dev_name(dev), start, end);
|
2009-08-26 13:25:41 +00:00
|
|
|
|
2009-12-02 09:21:55 +00:00
|
|
|
if (end < start) {
|
|
|
|
WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
|
|
|
|
"BIOS vendor: %s; Ver: %s; Product Version: %s\n",
|
|
|
|
dmi_get_system_info(DMI_BIOS_VENDOR),
|
|
|
|
dmi_get_system_info(DMI_BIOS_VERSION),
|
|
|
|
dmi_get_system_info(DMI_PRODUCT_VERSION));
|
|
|
|
ret = -EIO;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2009-08-26 13:25:41 +00:00
|
|
|
if (end >> agaw_to_width(domain->agaw)) {
|
|
|
|
WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
|
|
|
|
"BIOS vendor: %s; Ver: %s; Product Version: %s\n",
|
|
|
|
agaw_to_width(domain->agaw),
|
|
|
|
dmi_get_system_info(DMI_BIOS_VENDOR),
|
|
|
|
dmi_get_system_info(DMI_BIOS_VERSION),
|
|
|
|
dmi_get_system_info(DMI_PRODUCT_VERSION));
|
|
|
|
ret = -EIO;
|
|
|
|
goto error;
|
|
|
|
}
|
2009-08-04 15:19:20 +00:00
|
|
|
|
2009-06-26 17:50:28 +00:00
|
|
|
ret = iommu_domain_identity_map(domain, start, end);
|
2007-10-21 23:41:49 +00:00
|
|
|
if (ret)
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
/* context entry init */
|
2014-03-09 22:48:15 +00:00
|
|
|
ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL);
|
2009-06-26 17:50:28 +00:00
|
|
|
if (ret)
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
error:
|
2007-10-21 23:41:49 +00:00
|
|
|
domain_exit(domain);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
|
2014-03-09 22:48:15 +00:00
|
|
|
struct device *dev)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
2014-03-09 22:48:15 +00:00
|
|
|
if (dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
|
2007-10-21 23:41:49 +00:00
|
|
|
return 0;
|
2014-03-09 22:48:15 +00:00
|
|
|
return iommu_prepare_identity_map(dev, rmrr->base_address,
|
|
|
|
rmrr->end_address);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2011-08-24 00:05:25 +00:00
|
|
|
#ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
|
2007-10-21 23:41:57 +00:00
|
|
|
static inline void iommu_prepare_isa(void)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
|
|
|
|
if (!pdev)
|
|
|
|
return;
|
|
|
|
|
2009-06-26 18:10:36 +00:00
|
|
|
printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
|
2014-03-09 22:48:15 +00:00
|
|
|
ret = iommu_prepare_identity_map(&pdev->dev, 0, 16*1024*1024 - 1);
|
2007-10-21 23:41:57 +00:00
|
|
|
|
|
|
|
if (ret)
|
2009-06-26 18:10:36 +00:00
|
|
|
printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
|
|
|
|
"floppy might not work\n");
|
2007-10-21 23:41:57 +00:00
|
|
|
|
2014-05-20 12:37:52 +00:00
|
|
|
pci_dev_put(pdev);
|
2007-10-21 23:41:57 +00:00
|
|
|
}
|
|
|
|
#else
|
|
|
|
static inline void iommu_prepare_isa(void)
|
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
2011-08-24 00:05:25 +00:00
|
|
|
#endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
|
2007-10-21 23:41:57 +00:00
|
|
|
|
2009-06-19 20:47:29 +00:00
|
|
|
static int md_domain_init(struct dmar_domain *domain, int guest_width);
|
2009-06-26 18:10:36 +00:00
|
|
|
|
2009-08-24 05:30:22 +00:00
|
|
|
static int __init si_domain_init(int hw)
|
2009-06-19 20:47:29 +00:00
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
struct intel_iommu *iommu;
|
2009-06-26 18:10:36 +00:00
|
|
|
int nid, ret = 0;
|
2014-07-11 06:19:29 +00:00
|
|
|
bool first = true;
|
2009-06-19 20:47:29 +00:00
|
|
|
|
2014-07-11 06:19:27 +00:00
|
|
|
si_domain = alloc_domain(DOMAIN_FLAG_STATIC_IDENTITY);
|
2009-06-19 20:47:29 +00:00
|
|
|
if (!si_domain)
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
for_each_active_iommu(iommu, drhd) {
|
|
|
|
ret = iommu_attach_domain(si_domain, iommu);
|
2014-07-11 06:19:28 +00:00
|
|
|
if (ret < 0) {
|
2009-06-19 20:47:29 +00:00
|
|
|
domain_exit(si_domain);
|
|
|
|
return -EFAULT;
|
2014-07-11 06:19:29 +00:00
|
|
|
} else if (first) {
|
|
|
|
si_domain->id = ret;
|
|
|
|
first = false;
|
|
|
|
} else if (si_domain->id != ret) {
|
|
|
|
domain_exit(si_domain);
|
|
|
|
return -EFAULT;
|
2009-06-19 20:47:29 +00:00
|
|
|
}
|
2014-07-11 06:19:28 +00:00
|
|
|
domain_attach_iommu(si_domain, iommu);
|
2009-06-19 20:47:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
|
|
|
|
domain_exit(si_domain);
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
|
2014-01-06 06:18:13 +00:00
|
|
|
pr_debug("IOMMU: identity mapping domain is domain %d\n",
|
|
|
|
si_domain->id);
|
2009-06-19 20:47:29 +00:00
|
|
|
|
2009-08-04 15:19:20 +00:00
|
|
|
if (hw)
|
|
|
|
return 0;
|
|
|
|
|
2009-06-26 18:10:36 +00:00
|
|
|
for_each_online_node(nid) {
|
2011-07-14 07:46:10 +00:00
|
|
|
unsigned long start_pfn, end_pfn;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) {
|
|
|
|
ret = iommu_domain_identity_map(si_domain,
|
|
|
|
PFN_PHYS(start_pfn), PFN_PHYS(end_pfn));
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2009-06-26 18:10:36 +00:00
|
|
|
}
|
|
|
|
|
2009-06-19 20:47:29 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-03-09 21:03:28 +00:00
|
|
|
static int identity_mapping(struct device *dev)
|
2009-06-19 20:47:29 +00:00
|
|
|
{
|
|
|
|
struct device_domain_info *info;
|
|
|
|
|
|
|
|
if (likely(!iommu_identity_mapping))
|
|
|
|
return 0;
|
|
|
|
|
2014-03-09 21:03:28 +00:00
|
|
|
info = dev->archdata.iommu;
|
2011-05-28 18:15:03 +00:00
|
|
|
if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
|
|
|
|
return (info->domain == si_domain);
|
2009-06-19 20:47:29 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int domain_add_dev_info(struct dmar_domain *domain,
|
2014-03-09 23:27:31 +00:00
|
|
|
struct device *dev, int translation)
|
2009-06-19 20:47:29 +00:00
|
|
|
{
|
2014-03-09 20:19:22 +00:00
|
|
|
struct dmar_domain *ndomain;
|
2014-03-09 20:31:18 +00:00
|
|
|
struct intel_iommu *iommu;
|
2014-03-09 21:00:57 +00:00
|
|
|
u8 bus, devfn;
|
2009-08-09 09:53:41 +00:00
|
|
|
int ret;
|
2009-06-19 20:47:29 +00:00
|
|
|
|
2014-03-09 23:27:31 +00:00
|
|
|
iommu = device_to_iommu(dev, &bus, &devfn);
|
2014-03-09 20:31:18 +00:00
|
|
|
if (!iommu)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2014-03-09 23:27:31 +00:00
|
|
|
ndomain = dmar_insert_dev_info(iommu, bus, devfn, dev, domain);
|
2014-03-09 20:19:22 +00:00
|
|
|
if (ndomain != domain)
|
|
|
|
return -EBUSY;
|
2009-06-19 20:47:29 +00:00
|
|
|
|
2014-03-09 23:27:31 +00:00
|
|
|
ret = domain_context_mapping(domain, dev, translation);
|
2012-05-25 16:42:54 +00:00
|
|
|
if (ret) {
|
2014-03-09 23:27:31 +00:00
|
|
|
domain_remove_one_dev_info(domain, dev);
|
2012-05-25 16:42:54 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-06-19 20:47:29 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-03-09 22:48:15 +00:00
|
|
|
static bool device_has_rmrr(struct device *dev)
|
2012-11-20 19:43:17 +00:00
|
|
|
{
|
|
|
|
struct dmar_rmrr_unit *rmrr;
|
2014-03-07 15:08:36 +00:00
|
|
|
struct device *tmp;
|
2012-11-20 19:43:17 +00:00
|
|
|
int i;
|
|
|
|
|
2014-02-19 06:07:34 +00:00
|
|
|
rcu_read_lock();
|
2012-11-20 19:43:17 +00:00
|
|
|
for_each_rmrr_units(rmrr) {
|
2014-02-19 06:07:32 +00:00
|
|
|
/*
|
|
|
|
* Return TRUE if this RMRR contains the device that
|
|
|
|
* is passed in.
|
|
|
|
*/
|
|
|
|
for_each_active_dev_scope(rmrr->devices,
|
|
|
|
rmrr->devices_cnt, i, tmp)
|
2014-03-09 22:48:15 +00:00
|
|
|
if (tmp == dev) {
|
2014-02-19 06:07:34 +00:00
|
|
|
rcu_read_unlock();
|
2012-11-20 19:43:17 +00:00
|
|
|
return true;
|
2014-02-19 06:07:32 +00:00
|
|
|
}
|
2012-11-20 19:43:17 +00:00
|
|
|
}
|
2014-02-19 06:07:34 +00:00
|
|
|
rcu_read_unlock();
|
2012-11-20 19:43:17 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-07-03 15:57:02 +00:00
|
|
|
/*
|
|
|
|
* There are a couple cases where we need to restrict the functionality of
|
|
|
|
* devices associated with RMRRs. The first is when evaluating a device for
|
|
|
|
* identity mapping because problems exist when devices are moved in and out
|
|
|
|
* of domains and their respective RMRR information is lost. This means that
|
|
|
|
* a device with associated RMRRs will never be in a "passthrough" domain.
|
|
|
|
* The second is use of the device through the IOMMU API. This interface
|
|
|
|
* expects to have full control of the IOVA space for the device. We cannot
|
|
|
|
* satisfy both the requirement that RMRR access is maintained and have an
|
|
|
|
* unencumbered IOVA space. We also have no ability to quiesce the device's
|
|
|
|
* use of the RMRR space or even inform the IOMMU API user of the restriction.
|
|
|
|
* We therefore prevent devices associated with an RMRR from participating in
|
|
|
|
* the IOMMU API, which eliminates them from device assignment.
|
|
|
|
*
|
|
|
|
* In both cases we assume that PCI USB devices with RMRRs have them largely
|
|
|
|
* for historical reasons and that the RMRR space is not actively used post
|
|
|
|
* boot. This exclusion may change if vendors begin to abuse it.
|
2015-03-25 15:05:47 +00:00
|
|
|
*
|
|
|
|
* The same exception is made for graphics devices, with the requirement that
|
|
|
|
* any use of the RMRR regions will be torn down before assigning the device
|
|
|
|
* to a guest.
|
2014-07-03 15:57:02 +00:00
|
|
|
*/
|
|
|
|
static bool device_is_rmrr_locked(struct device *dev)
|
|
|
|
{
|
|
|
|
if (!device_has_rmrr(dev))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (dev_is_pci(dev)) {
|
|
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
|
|
|
2015-03-25 15:05:47 +00:00
|
|
|
if (IS_USB_DEVICE(pdev) || IS_GFX_DEVICE(pdev))
|
2014-07-03 15:57:02 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2014-03-09 23:03:08 +00:00
|
|
|
static int iommu_should_identity_map(struct device *dev, int startup)
|
2009-07-04 17:24:27 +00:00
|
|
|
{
|
2012-11-20 19:43:17 +00:00
|
|
|
|
2014-03-09 23:03:08 +00:00
|
|
|
if (dev_is_pci(dev)) {
|
|
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
2012-11-20 19:43:17 +00:00
|
|
|
|
2014-07-03 15:57:02 +00:00
|
|
|
if (device_is_rmrr_locked(dev))
|
2014-03-09 23:03:08 +00:00
|
|
|
return 0;
|
2009-09-30 16:12:17 +00:00
|
|
|
|
2014-03-09 23:03:08 +00:00
|
|
|
if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
|
|
|
|
return 1;
|
2009-09-30 16:12:17 +00:00
|
|
|
|
2014-03-09 23:03:08 +00:00
|
|
|
if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
|
|
|
|
return 1;
|
2009-07-04 17:24:27 +00:00
|
|
|
|
2014-03-09 23:03:08 +00:00
|
|
|
if (!(iommu_identity_mapping & IDENTMAP_ALL))
|
intel-iommu: Don't use identity mapping for PCI devices behind bridges
Our current strategy for pass-through mode is to put all devices into
the 1:1 domain at startup (which is before we know what their dma_mask
will be), and only _later_ take them out of that domain, if it turns out
that they really can't address all of memory.
However, when there are a bunch of PCI devices behind a bridge, they all
end up with the same source-id on their DMA transactions, and hence in
the same IOMMU domain. This means that we _can't_ easily move them from
the 1:1 domain into their own domain at runtime, because there might be DMA
in-flight from their siblings.
So we have to adjust our pass-through strategy: For PCI devices not on
the root bus, and for the bridges which will take responsibility for
their transactions, we have to start up _out_ of the 1:1 domain, just in
case.
This fixes the BUG() we see when we have 32-bit-capable devices behind a
PCI-PCI bridge, and use the software identity mapping.
It does mean that we might end up using 'normal' mapping mode for some
devices which could actually live with the faster 1:1 mapping -- but
this is only for PCI devices behind bridges, which presumably aren't the
devices for which people are most concerned about performance.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-07-04 18:11:08 +00:00
|
|
|
return 0;
|
2014-03-09 23:03:08 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* We want to start off with all devices in the 1:1 domain, and
|
|
|
|
* take them out later if we find they can't access all of memory.
|
|
|
|
*
|
|
|
|
* However, we can't do this for PCI devices behind bridges,
|
|
|
|
* because all PCI devices behind the same bridge will end up
|
|
|
|
* with the same source-id on their transactions.
|
|
|
|
*
|
|
|
|
* Practically speaking, we can't change things around for these
|
|
|
|
* devices at run-time, because we can't be sure there'll be no
|
|
|
|
* DMA transactions in flight for any of their siblings.
|
|
|
|
*
|
|
|
|
* So PCI devices (unless they're on the root bus) as well as
|
|
|
|
* their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
|
|
|
|
* the 1:1 domain, just in _case_ one of their siblings turns out
|
|
|
|
* not to be able to map all of memory.
|
|
|
|
*/
|
|
|
|
if (!pci_is_pcie(pdev)) {
|
|
|
|
if (!pci_is_root_bus(pdev->bus))
|
|
|
|
return 0;
|
|
|
|
if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
|
|
|
|
return 0;
|
|
|
|
} else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE)
|
intel-iommu: Don't use identity mapping for PCI devices behind bridges
Our current strategy for pass-through mode is to put all devices into
the 1:1 domain at startup (which is before we know what their dma_mask
will be), and only _later_ take them out of that domain, if it turns out
that they really can't address all of memory.
However, when there are a bunch of PCI devices behind a bridge, they all
end up with the same source-id on their DMA transactions, and hence in
the same IOMMU domain. This means that we _can't_ easily move them from
the 1:1 domain into their own domain at runtime, because there might be DMA
in-flight from their siblings.
So we have to adjust our pass-through strategy: For PCI devices not on
the root bus, and for the bridges which will take responsibility for
their transactions, we have to start up _out_ of the 1:1 domain, just in
case.
This fixes the BUG() we see when we have 32-bit-capable devices behind a
PCI-PCI bridge, and use the software identity mapping.
It does mean that we might end up using 'normal' mapping mode for some
devices which could actually live with the faster 1:1 mapping -- but
this is only for PCI devices behind bridges, which presumably aren't the
devices for which people are most concerned about performance.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-07-04 18:11:08 +00:00
|
|
|
return 0;
|
2014-03-09 23:03:08 +00:00
|
|
|
} else {
|
|
|
|
if (device_has_rmrr(dev))
|
|
|
|
return 0;
|
|
|
|
}
|
intel-iommu: Don't use identity mapping for PCI devices behind bridges
Our current strategy for pass-through mode is to put all devices into
the 1:1 domain at startup (which is before we know what their dma_mask
will be), and only _later_ take them out of that domain, if it turns out
that they really can't address all of memory.
However, when there are a bunch of PCI devices behind a bridge, they all
end up with the same source-id on their DMA transactions, and hence in
the same IOMMU domain. This means that we _can't_ easily move them from
the 1:1 domain into their own domain at runtime, because there might be DMA
in-flight from their siblings.
So we have to adjust our pass-through strategy: For PCI devices not on
the root bus, and for the bridges which will take responsibility for
their transactions, we have to start up _out_ of the 1:1 domain, just in
case.
This fixes the BUG() we see when we have 32-bit-capable devices behind a
PCI-PCI bridge, and use the software identity mapping.
It does mean that we might end up using 'normal' mapping mode for some
devices which could actually live with the faster 1:1 mapping -- but
this is only for PCI devices behind bridges, which presumably aren't the
devices for which people are most concerned about performance.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-07-04 18:11:08 +00:00
|
|
|
|
2014-03-09 23:03:08 +00:00
|
|
|
/*
|
intel-iommu: Don't use identity mapping for PCI devices behind bridges
Our current strategy for pass-through mode is to put all devices into
the 1:1 domain at startup (which is before we know what their dma_mask
will be), and only _later_ take them out of that domain, if it turns out
that they really can't address all of memory.
However, when there are a bunch of PCI devices behind a bridge, they all
end up with the same source-id on their DMA transactions, and hence in
the same IOMMU domain. This means that we _can't_ easily move them from
the 1:1 domain into their own domain at runtime, because there might be DMA
in-flight from their siblings.
So we have to adjust our pass-through strategy: For PCI devices not on
the root bus, and for the bridges which will take responsibility for
their transactions, we have to start up _out_ of the 1:1 domain, just in
case.
This fixes the BUG() we see when we have 32-bit-capable devices behind a
PCI-PCI bridge, and use the software identity mapping.
It does mean that we might end up using 'normal' mapping mode for some
devices which could actually live with the faster 1:1 mapping -- but
this is only for PCI devices behind bridges, which presumably aren't the
devices for which people are most concerned about performance.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-07-04 18:11:08 +00:00
|
|
|
* At boot time, we don't yet know if devices will be 64-bit capable.
|
2014-03-09 23:03:08 +00:00
|
|
|
* Assume that they will — if they turn out not to be, then we can
|
intel-iommu: Don't use identity mapping for PCI devices behind bridges
Our current strategy for pass-through mode is to put all devices into
the 1:1 domain at startup (which is before we know what their dma_mask
will be), and only _later_ take them out of that domain, if it turns out
that they really can't address all of memory.
However, when there are a bunch of PCI devices behind a bridge, they all
end up with the same source-id on their DMA transactions, and hence in
the same IOMMU domain. This means that we _can't_ easily move them from
the 1:1 domain into their own domain at runtime, because there might be DMA
in-flight from their siblings.
So we have to adjust our pass-through strategy: For PCI devices not on
the root bus, and for the bridges which will take responsibility for
their transactions, we have to start up _out_ of the 1:1 domain, just in
case.
This fixes the BUG() we see when we have 32-bit-capable devices behind a
PCI-PCI bridge, and use the software identity mapping.
It does mean that we might end up using 'normal' mapping mode for some
devices which could actually live with the faster 1:1 mapping -- but
this is only for PCI devices behind bridges, which presumably aren't the
devices for which people are most concerned about performance.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-07-04 18:11:08 +00:00
|
|
|
* take them out of the 1:1 domain later.
|
|
|
|
*/
|
2011-05-28 18:15:02 +00:00
|
|
|
if (!startup) {
|
|
|
|
/*
|
|
|
|
* If the device's dma_mask is less than the system's memory
|
|
|
|
* size then this is not a candidate for identity mapping.
|
|
|
|
*/
|
2014-03-09 23:03:08 +00:00
|
|
|
u64 dma_mask = *dev->dma_mask;
|
2011-05-28 18:15:02 +00:00
|
|
|
|
2014-03-09 23:03:08 +00:00
|
|
|
if (dev->coherent_dma_mask &&
|
|
|
|
dev->coherent_dma_mask < dma_mask)
|
|
|
|
dma_mask = dev->coherent_dma_mask;
|
2011-05-28 18:15:02 +00:00
|
|
|
|
2014-03-09 23:03:08 +00:00
|
|
|
return dma_mask >= dma_get_required_mask(dev);
|
2011-05-28 18:15:02 +00:00
|
|
|
}
|
2009-07-04 17:24:27 +00:00
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2014-03-21 16:49:04 +00:00
|
|
|
static int __init dev_prepare_static_identity_mapping(struct device *dev, int hw)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!iommu_should_identity_map(dev, 1))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
ret = domain_add_dev_info(si_domain, dev,
|
|
|
|
hw ? CONTEXT_TT_PASS_THROUGH :
|
|
|
|
CONTEXT_TT_MULTI_LEVEL);
|
|
|
|
if (!ret)
|
|
|
|
pr_info("IOMMU: %s identity mapping for device %s\n",
|
|
|
|
hw ? "hardware" : "software", dev_name(dev));
|
|
|
|
else if (ret == -ENODEV)
|
|
|
|
/* device not associated with an iommu */
|
|
|
|
ret = 0;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2009-08-24 05:30:22 +00:00
|
|
|
static int __init iommu_prepare_static_identity_mapping(int hw)
|
2009-06-19 20:47:29 +00:00
|
|
|
{
|
|
|
|
struct pci_dev *pdev = NULL;
|
2014-03-21 16:49:04 +00:00
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
struct intel_iommu *iommu;
|
|
|
|
struct device *dev;
|
|
|
|
int i;
|
|
|
|
int ret = 0;
|
2009-06-19 20:47:29 +00:00
|
|
|
|
2009-08-04 15:19:20 +00:00
|
|
|
ret = si_domain_init(hw);
|
2009-06-19 20:47:29 +00:00
|
|
|
if (ret)
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
for_each_pci_dev(pdev) {
|
2014-03-21 16:49:04 +00:00
|
|
|
ret = dev_prepare_static_identity_mapping(&pdev->dev, hw);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
for_each_active_iommu(iommu, drhd)
|
|
|
|
for_each_active_dev_scope(drhd->devices, drhd->devices_cnt, i, dev) {
|
|
|
|
struct acpi_device_physical_node *pn;
|
|
|
|
struct acpi_device *adev;
|
|
|
|
|
|
|
|
if (dev->bus != &acpi_bus_type)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
adev= to_acpi_device(dev);
|
|
|
|
mutex_lock(&adev->physical_node_lock);
|
|
|
|
list_for_each_entry(pn, &adev->physical_node_list, node) {
|
|
|
|
ret = dev_prepare_static_identity_mapping(pn->dev, hw);
|
|
|
|
if (ret)
|
|
|
|
break;
|
2012-03-05 23:05:16 +00:00
|
|
|
}
|
2014-03-21 16:49:04 +00:00
|
|
|
mutex_unlock(&adev->physical_node_lock);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2009-07-04 09:59:46 +00:00
|
|
|
}
|
2009-06-19 20:47:29 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-11-09 14:48:02 +00:00
|
|
|
static void intel_iommu_init_qi(struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Start from the sane iommu hardware state.
|
|
|
|
* If the queued invalidation is already initialized by us
|
|
|
|
* (for example, while enabling interrupt-remapping) then
|
|
|
|
* we got the things already rolling from a sane state.
|
|
|
|
*/
|
|
|
|
if (!iommu->qi) {
|
|
|
|
/*
|
|
|
|
* Clear any previous faults.
|
|
|
|
*/
|
|
|
|
dmar_fault(-1, iommu);
|
|
|
|
/*
|
|
|
|
* Disable queued invalidation if supported and already enabled
|
|
|
|
* before OS handover.
|
|
|
|
*/
|
|
|
|
dmar_disable_qi(iommu);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dmar_enable_qi(iommu)) {
|
|
|
|
/*
|
|
|
|
* Queued Invalidate not enabled, use Register Based Invalidate
|
|
|
|
*/
|
|
|
|
iommu->flush.flush_context = __iommu_flush_context;
|
|
|
|
iommu->flush.flush_iotlb = __iommu_flush_iotlb;
|
|
|
|
pr_info("IOMMU: %s using Register based invalidation\n",
|
|
|
|
iommu->name);
|
|
|
|
} else {
|
|
|
|
iommu->flush.flush_context = qi_flush_context;
|
|
|
|
iommu->flush.flush_iotlb = qi_flush_iotlb;
|
|
|
|
pr_info("IOMMU: %s using Queued invalidation\n", iommu->name);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-05-03 07:08:37 +00:00
|
|
|
static int __init init_dmars(void)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
struct dmar_rmrr_unit *rmrr;
|
2014-03-07 15:08:36 +00:00
|
|
|
struct device *dev;
|
2007-10-21 23:41:49 +00:00
|
|
|
struct intel_iommu *iommu;
|
2009-03-17 00:04:55 +00:00
|
|
|
int i, ret;
|
2009-06-19 20:47:29 +00:00
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
/*
|
|
|
|
* for each drhd
|
|
|
|
* allocate root
|
|
|
|
* initialize and program root entry to not present
|
|
|
|
* endfor
|
|
|
|
*/
|
|
|
|
for_each_drhd_unit(drhd) {
|
2008-03-04 23:22:08 +00:00
|
|
|
/*
|
|
|
|
* lock not needed as this is only incremented in the single
|
|
|
|
* threaded kernel __init code path all other access are read
|
|
|
|
* only
|
|
|
|
*/
|
2014-11-09 14:47:57 +00:00
|
|
|
if (g_num_of_iommus < DMAR_UNITS_SUPPORTED) {
|
2012-03-05 23:05:16 +00:00
|
|
|
g_num_of_iommus++;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
printk_once(KERN_ERR "intel-iommu: exceeded %d IOMMUs\n",
|
2014-11-09 14:47:57 +00:00
|
|
|
DMAR_UNITS_SUPPORTED);
|
2008-03-04 23:22:08 +00:00
|
|
|
}
|
|
|
|
|
2014-11-09 14:48:02 +00:00
|
|
|
/* Preallocate enough resources for IOMMU hot-addition */
|
|
|
|
if (g_num_of_iommus < DMAR_UNITS_SUPPORTED)
|
|
|
|
g_num_of_iommus = DMAR_UNITS_SUPPORTED;
|
|
|
|
|
2008-12-08 03:06:32 +00:00
|
|
|
g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!g_iommus) {
|
|
|
|
printk(KERN_ERR "Allocating global iommu array failed\n");
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2008-04-18 20:53:58 +00:00
|
|
|
deferred_flush = kzalloc(g_num_of_iommus *
|
|
|
|
sizeof(struct deferred_flush_tables), GFP_KERNEL);
|
|
|
|
if (!deferred_flush) {
|
2008-03-04 23:22:08 +00:00
|
|
|
ret = -ENOMEM;
|
2014-02-19 06:07:21 +00:00
|
|
|
goto free_g_iommus;
|
2008-03-04 23:22:08 +00:00
|
|
|
}
|
|
|
|
|
2014-01-06 06:18:18 +00:00
|
|
|
for_each_active_iommu(iommu, drhd) {
|
2008-12-08 03:06:32 +00:00
|
|
|
g_iommus[iommu->seq_id] = iommu;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2008-07-10 18:16:35 +00:00
|
|
|
ret = iommu_init_domains(iommu);
|
|
|
|
if (ret)
|
2014-02-19 06:07:21 +00:00
|
|
|
goto free_iommu;
|
2008-07-10 18:16:35 +00:00
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
/*
|
|
|
|
* TBD:
|
|
|
|
* we could share the same root & context tables
|
2011-03-31 01:57:33 +00:00
|
|
|
* among all IOMMU's. Need to Split it later.
|
2007-10-21 23:41:49 +00:00
|
|
|
*/
|
|
|
|
ret = iommu_alloc_root_entry(iommu);
|
2014-11-09 14:48:02 +00:00
|
|
|
if (ret)
|
2014-02-19 06:07:21 +00:00
|
|
|
goto free_iommu;
|
2009-04-25 00:30:20 +00:00
|
|
|
if (!ecap_pass_through(iommu->ecap))
|
2009-08-04 15:19:20 +00:00
|
|
|
hw_pass_through = 0;
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2014-11-09 14:48:02 +00:00
|
|
|
for_each_active_iommu(iommu, drhd)
|
|
|
|
intel_iommu_init_qi(iommu);
|
2008-10-16 23:31:56 +00:00
|
|
|
|
2009-08-04 15:19:20 +00:00
|
|
|
if (iommu_pass_through)
|
2009-09-30 16:12:17 +00:00
|
|
|
iommu_identity_mapping |= IDENTMAP_ALL;
|
|
|
|
|
2011-08-24 00:05:25 +00:00
|
|
|
#ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
|
2009-09-30 16:12:17 +00:00
|
|
|
iommu_identity_mapping |= IDENTMAP_GFX;
|
2009-08-04 15:19:20 +00:00
|
|
|
#endif
|
2009-09-30 16:12:17 +00:00
|
|
|
|
|
|
|
check_tylersburg_isoch();
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
/*
|
2009-08-04 15:19:20 +00:00
|
|
|
* If pass through is not set or not enabled, setup context entries for
|
|
|
|
* identity mappings for rmrr, gfx, and isa and may fall back to static
|
|
|
|
* identity mapping if iommu_identity_mapping is set.
|
2007-10-21 23:41:49 +00:00
|
|
|
*/
|
2009-08-04 15:19:20 +00:00
|
|
|
if (iommu_identity_mapping) {
|
|
|
|
ret = iommu_prepare_static_identity_mapping(hw_pass_through);
|
2009-04-25 00:30:20 +00:00
|
|
|
if (ret) {
|
2009-08-04 15:19:20 +00:00
|
|
|
printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
|
2014-02-19 06:07:21 +00:00
|
|
|
goto free_iommu;
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
/*
|
2009-08-04 15:19:20 +00:00
|
|
|
* For each rmrr
|
|
|
|
* for each dev attached to rmrr
|
|
|
|
* do
|
|
|
|
* locate drhd for dev, alloc domain for dev
|
|
|
|
* allocate free domain
|
|
|
|
* allocate page table entries for rmrr
|
|
|
|
* if context not allocated for bus
|
|
|
|
* allocate and init context
|
|
|
|
* set present in root table for this bus
|
|
|
|
* init context with domain, translation etc
|
|
|
|
* endfor
|
|
|
|
* endfor
|
2007-10-21 23:41:49 +00:00
|
|
|
*/
|
2009-08-04 15:19:20 +00:00
|
|
|
printk(KERN_INFO "IOMMU: Setting RMRR:\n");
|
|
|
|
for_each_rmrr_units(rmrr) {
|
2014-02-19 06:07:32 +00:00
|
|
|
/* some BIOS lists non-exist devices in DMAR table. */
|
|
|
|
for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
|
2014-03-07 15:08:36 +00:00
|
|
|
i, dev) {
|
2014-03-09 22:48:15 +00:00
|
|
|
ret = iommu_prepare_rmrr_dev(rmrr, dev);
|
2009-08-04 15:19:20 +00:00
|
|
|
if (ret)
|
|
|
|
printk(KERN_ERR
|
|
|
|
"IOMMU: mapping reserved region failed\n");
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
2009-04-25 00:30:20 +00:00
|
|
|
}
|
2007-10-21 23:41:57 +00:00
|
|
|
|
2009-08-04 15:19:20 +00:00
|
|
|
iommu_prepare_isa();
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
/*
|
|
|
|
* for each drhd
|
|
|
|
* enable fault log
|
|
|
|
* global invalidate context cache
|
|
|
|
* global invalidate iotlb
|
|
|
|
* enable translation
|
|
|
|
*/
|
2014-01-06 06:18:18 +00:00
|
|
|
for_each_iommu(iommu, drhd) {
|
2011-03-21 18:04:24 +00:00
|
|
|
if (drhd->ignored) {
|
|
|
|
/*
|
|
|
|
* we always have to disable PMRs or DMA may fail on
|
|
|
|
* this device
|
|
|
|
*/
|
|
|
|
if (force_on)
|
2014-01-06 06:18:18 +00:00
|
|
|
iommu_disable_protect_mem_regions(iommu);
|
2007-10-21 23:41:49 +00:00
|
|
|
continue;
|
2011-03-21 18:04:24 +00:00
|
|
|
}
|
2007-10-21 23:41:49 +00:00
|
|
|
|
|
|
|
iommu_flush_write_buffer(iommu);
|
|
|
|
|
2007-10-21 23:41:54 +00:00
|
|
|
ret = dmar_set_interrupt(iommu);
|
|
|
|
if (ret)
|
2014-02-19 06:07:21 +00:00
|
|
|
goto free_iommu;
|
2007-10-21 23:41:54 +00:00
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
iommu_set_root_entry(iommu);
|
|
|
|
|
2009-05-10 16:16:06 +00:00
|
|
|
iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
|
2009-05-10 18:58:49 +00:00
|
|
|
iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
|
2014-07-11 06:19:33 +00:00
|
|
|
iommu_enable_translation(iommu);
|
2009-09-19 22:28:12 +00:00
|
|
|
iommu_disable_protect_mem_regions(iommu);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2014-02-19 06:07:21 +00:00
|
|
|
|
|
|
|
free_iommu:
|
2014-11-09 14:48:02 +00:00
|
|
|
for_each_active_iommu(iommu, drhd) {
|
|
|
|
disable_dmar_iommu(iommu);
|
2014-01-06 06:18:20 +00:00
|
|
|
free_dmar_iommu(iommu);
|
2014-11-09 14:48:02 +00:00
|
|
|
}
|
2014-01-06 06:18:27 +00:00
|
|
|
kfree(deferred_flush);
|
2014-02-19 06:07:21 +00:00
|
|
|
free_g_iommus:
|
2008-12-08 03:06:32 +00:00
|
|
|
kfree(g_iommus);
|
2014-02-19 06:07:21 +00:00
|
|
|
error:
|
2007-10-21 23:41:49 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-07-04 08:35:44 +00:00
|
|
|
/* This takes a number of _MM_ pages, not VTD pages */
|
2009-06-28 20:20:51 +00:00
|
|
|
static struct iova *intel_alloc_iova(struct device *dev,
|
|
|
|
struct dmar_domain *domain,
|
|
|
|
unsigned long nrpages, uint64_t dma_mask)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
|
|
|
struct iova *iova = NULL;
|
|
|
|
|
2009-06-28 20:20:51 +00:00
|
|
|
/* Restrict dma_mask to the width that the iommu can handle */
|
|
|
|
dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
|
|
|
|
|
|
|
|
if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
|
2007-10-21 23:41:49 +00:00
|
|
|
/*
|
|
|
|
* First try to allocate an io virtual address in
|
2009-04-07 02:01:15 +00:00
|
|
|
* DMA_BIT_MASK(32) and if that fails then try allocating
|
2007-12-17 19:40:11 +00:00
|
|
|
* from higher range
|
2007-10-21 23:41:49 +00:00
|
|
|
*/
|
2009-06-28 20:20:51 +00:00
|
|
|
iova = alloc_iova(&domain->iovad, nrpages,
|
|
|
|
IOVA_PFN(DMA_BIT_MASK(32)), 1);
|
|
|
|
if (iova)
|
|
|
|
return iova;
|
|
|
|
}
|
|
|
|
iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
|
|
|
|
if (unlikely(!iova)) {
|
|
|
|
printk(KERN_ERR "Allocating %ld-page iova for %s failed",
|
2014-03-09 23:12:32 +00:00
|
|
|
nrpages, dev_name(dev));
|
2007-10-21 23:41:58 +00:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return iova;
|
|
|
|
}
|
|
|
|
|
2014-03-09 23:07:40 +00:00
|
|
|
static struct dmar_domain *__get_valid_domain_for_dev(struct device *dev)
|
2007-10-21 23:41:58 +00:00
|
|
|
{
|
|
|
|
struct dmar_domain *domain;
|
|
|
|
int ret;
|
|
|
|
|
2014-03-09 23:07:40 +00:00
|
|
|
domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
|
2007-10-21 23:41:58 +00:00
|
|
|
if (!domain) {
|
2014-03-09 23:07:40 +00:00
|
|
|
printk(KERN_ERR "Allocating domain for %s failed",
|
|
|
|
dev_name(dev));
|
2007-10-29 04:51:16 +00:00
|
|
|
return NULL;
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* make sure context mapping is ok */
|
2014-03-09 23:07:40 +00:00
|
|
|
if (unlikely(!domain_context_mapped(dev))) {
|
|
|
|
ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL);
|
2007-10-21 23:41:58 +00:00
|
|
|
if (ret) {
|
2014-03-09 23:07:40 +00:00
|
|
|
printk(KERN_ERR "Domain context map for %s failed",
|
|
|
|
dev_name(dev));
|
2007-10-29 04:51:16 +00:00
|
|
|
return NULL;
|
2007-10-21 23:41:58 +00:00
|
|
|
}
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2007-10-21 23:41:58 +00:00
|
|
|
return domain;
|
|
|
|
}
|
|
|
|
|
2014-03-09 23:07:40 +00:00
|
|
|
static inline struct dmar_domain *get_valid_domain_for_dev(struct device *dev)
|
2009-07-07 18:43:20 +00:00
|
|
|
{
|
|
|
|
struct device_domain_info *info;
|
|
|
|
|
|
|
|
/* No lock here, assumes no domain exit in normal case */
|
2014-03-09 23:07:40 +00:00
|
|
|
info = dev->archdata.iommu;
|
2009-07-07 18:43:20 +00:00
|
|
|
if (likely(info))
|
|
|
|
return info->domain;
|
|
|
|
|
|
|
|
return __get_valid_domain_for_dev(dev);
|
|
|
|
}
|
|
|
|
|
2014-03-06 15:59:26 +00:00
|
|
|
static int iommu_dummy(struct device *dev)
|
2009-06-19 20:47:29 +00:00
|
|
|
{
|
2014-03-06 15:59:26 +00:00
|
|
|
return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
|
2009-06-19 20:47:29 +00:00
|
|
|
}
|
|
|
|
|
2014-03-09 23:29:55 +00:00
|
|
|
/* Check if the dev needs to go through non-identity map and unmap process.*/
|
2009-07-04 13:08:36 +00:00
|
|
|
static int iommu_no_mapping(struct device *dev)
|
2009-06-19 20:47:29 +00:00
|
|
|
{
|
|
|
|
int found;
|
|
|
|
|
2014-03-06 15:59:26 +00:00
|
|
|
if (iommu_dummy(dev))
|
2009-07-04 09:40:38 +00:00
|
|
|
return 1;
|
|
|
|
|
2009-06-19 20:47:29 +00:00
|
|
|
if (!iommu_identity_mapping)
|
2009-07-04 09:40:38 +00:00
|
|
|
return 0;
|
2009-06-19 20:47:29 +00:00
|
|
|
|
2014-03-09 21:03:28 +00:00
|
|
|
found = identity_mapping(dev);
|
2009-06-19 20:47:29 +00:00
|
|
|
if (found) {
|
2014-03-09 23:29:55 +00:00
|
|
|
if (iommu_should_identity_map(dev, 0))
|
2009-06-19 20:47:29 +00:00
|
|
|
return 1;
|
|
|
|
else {
|
|
|
|
/*
|
|
|
|
* 32 bit DMA is removed from si_domain and fall back
|
|
|
|
* to non-identity mapping.
|
|
|
|
*/
|
2014-03-09 23:19:13 +00:00
|
|
|
domain_remove_one_dev_info(si_domain, dev);
|
2009-06-19 20:47:29 +00:00
|
|
|
printk(KERN_INFO "32bit %s uses non-identity mapping\n",
|
2014-03-09 23:29:55 +00:00
|
|
|
dev_name(dev));
|
2009-06-19 20:47:29 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* In case of a detached 64 bit DMA device from vm, the device
|
|
|
|
* is put into si_domain for identity mapping.
|
|
|
|
*/
|
2014-03-09 23:29:55 +00:00
|
|
|
if (iommu_should_identity_map(dev, 0)) {
|
2009-06-19 20:47:29 +00:00
|
|
|
int ret;
|
2014-03-09 23:27:31 +00:00
|
|
|
ret = domain_add_dev_info(si_domain, dev,
|
2009-08-09 09:53:41 +00:00
|
|
|
hw_pass_through ?
|
|
|
|
CONTEXT_TT_PASS_THROUGH :
|
|
|
|
CONTEXT_TT_MULTI_LEVEL);
|
2009-06-19 20:47:29 +00:00
|
|
|
if (!ret) {
|
|
|
|
printk(KERN_INFO "64bit %s uses identity mapping\n",
|
2014-03-09 23:29:55 +00:00
|
|
|
dev_name(dev));
|
2009-06-19 20:47:29 +00:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-07-04 09:40:38 +00:00
|
|
|
return 0;
|
2009-06-19 20:47:29 +00:00
|
|
|
}
|
|
|
|
|
2014-03-09 23:14:00 +00:00
|
|
|
static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr,
|
2008-10-15 07:08:28 +00:00
|
|
|
size_t size, int dir, u64 dma_mask)
|
2007-10-21 23:41:58 +00:00
|
|
|
{
|
|
|
|
struct dmar_domain *domain;
|
2008-10-17 01:02:32 +00:00
|
|
|
phys_addr_t start_paddr;
|
2007-10-21 23:41:58 +00:00
|
|
|
struct iova *iova;
|
|
|
|
int prot = 0;
|
2008-04-22 09:09:04 +00:00
|
|
|
int ret;
|
2008-12-08 07:29:22 +00:00
|
|
|
struct intel_iommu *iommu;
|
2009-08-04 22:10:59 +00:00
|
|
|
unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
|
2007-10-21 23:41:58 +00:00
|
|
|
|
|
|
|
BUG_ON(dir == DMA_NONE);
|
2009-06-19 20:47:29 +00:00
|
|
|
|
2014-03-09 23:14:00 +00:00
|
|
|
if (iommu_no_mapping(dev))
|
2008-04-22 09:09:04 +00:00
|
|
|
return paddr;
|
2007-10-21 23:41:58 +00:00
|
|
|
|
2014-03-09 23:14:00 +00:00
|
|
|
domain = get_valid_domain_for_dev(dev);
|
2007-10-21 23:41:58 +00:00
|
|
|
if (!domain)
|
|
|
|
return 0;
|
|
|
|
|
2008-12-08 07:29:22 +00:00
|
|
|
iommu = domain_get_iommu(domain);
|
2009-06-28 14:03:06 +00:00
|
|
|
size = aligned_nrpages(paddr, size);
|
2007-10-21 23:41:58 +00:00
|
|
|
|
2014-03-09 23:14:00 +00:00
|
|
|
iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), dma_mask);
|
2007-10-21 23:41:58 +00:00
|
|
|
if (!iova)
|
|
|
|
goto error;
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
/*
|
|
|
|
* Check if DMAR supports zero-length reads on write only
|
|
|
|
* mappings..
|
|
|
|
*/
|
|
|
|
if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
|
2008-12-08 07:29:22 +00:00
|
|
|
!cap_zlr(iommu->cap))
|
2007-10-21 23:41:49 +00:00
|
|
|
prot |= DMA_PTE_READ;
|
|
|
|
if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
|
|
|
|
prot |= DMA_PTE_WRITE;
|
|
|
|
/*
|
2008-04-22 09:09:04 +00:00
|
|
|
* paddr - (paddr + size) might be partial page, we should map the whole
|
2007-10-21 23:41:49 +00:00
|
|
|
* page. Note: if two part of one page are separately mapped, we
|
2008-04-22 09:09:04 +00:00
|
|
|
* might have two guest_addr mapping to the same host paddr, but this
|
2007-10-21 23:41:49 +00:00
|
|
|
* is not a big problem
|
|
|
|
*/
|
2009-06-28 13:01:43 +00:00
|
|
|
ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
|
2009-08-04 22:10:59 +00:00
|
|
|
mm_to_dma_pfn(paddr_pfn), size, prot);
|
2007-10-21 23:41:49 +00:00
|
|
|
if (ret)
|
|
|
|
goto error;
|
|
|
|
|
2009-05-10 18:58:49 +00:00
|
|
|
/* it's a non-present to present mapping. Only flush if caching mode */
|
|
|
|
if (cap_caching_mode(iommu->cap))
|
2014-03-05 17:09:32 +00:00
|
|
|
iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 0, 1);
|
2009-05-10 18:58:49 +00:00
|
|
|
else
|
2008-12-08 07:29:22 +00:00
|
|
|
iommu_flush_write_buffer(iommu);
|
2007-10-21 23:41:58 +00:00
|
|
|
|
2009-06-28 14:33:46 +00:00
|
|
|
start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
|
|
|
|
start_paddr += paddr & ~PAGE_MASK;
|
|
|
|
return start_paddr;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
|
|
|
error:
|
2007-10-21 23:41:58 +00:00
|
|
|
if (iova)
|
|
|
|
__free_iova(&domain->iovad, iova);
|
2009-02-11 17:23:43 +00:00
|
|
|
printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
|
2014-03-09 23:14:00 +00:00
|
|
|
dev_name(dev), size, (unsigned long long)paddr, dir);
|
2007-10-21 23:41:49 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-01-05 14:47:26 +00:00
|
|
|
static dma_addr_t intel_map_page(struct device *dev, struct page *page,
|
|
|
|
unsigned long offset, size_t size,
|
|
|
|
enum dma_data_direction dir,
|
|
|
|
struct dma_attrs *attrs)
|
2008-10-15 07:08:28 +00:00
|
|
|
{
|
2009-01-05 14:47:26 +00:00
|
|
|
return __intel_map_single(dev, page_to_phys(page) + offset, size,
|
2014-03-11 03:01:21 +00:00
|
|
|
dir, *dev->dma_mask);
|
2008-10-15 07:08:28 +00:00
|
|
|
}
|
|
|
|
|
2008-03-04 23:22:08 +00:00
|
|
|
static void flush_unmaps(void)
|
|
|
|
{
|
2008-04-18 20:53:58 +00:00
|
|
|
int i, j;
|
2008-03-04 23:22:08 +00:00
|
|
|
|
|
|
|
timer_on = 0;
|
|
|
|
|
|
|
|
/* just flush them all */
|
|
|
|
for (i = 0; i < g_num_of_iommus; i++) {
|
2008-12-08 03:24:12 +00:00
|
|
|
struct intel_iommu *iommu = g_iommus[i];
|
|
|
|
if (!iommu)
|
|
|
|
continue;
|
2008-07-10 18:16:36 +00:00
|
|
|
|
2009-05-18 05:51:36 +00:00
|
|
|
if (!deferred_flush[i].next)
|
|
|
|
continue;
|
|
|
|
|
2010-04-08 20:00:41 +00:00
|
|
|
/* In caching mode, global flushes turn emulation expensive */
|
|
|
|
if (!cap_caching_mode(iommu->cap))
|
|
|
|
iommu->flush.flush_iotlb(iommu, 0, 0, 0,
|
2009-05-18 05:51:37 +00:00
|
|
|
DMA_TLB_GLOBAL_FLUSH);
|
2009-05-18 05:51:36 +00:00
|
|
|
for (j = 0; j < deferred_flush[i].next; j++) {
|
2009-05-18 05:51:37 +00:00
|
|
|
unsigned long mask;
|
|
|
|
struct iova *iova = deferred_flush[i].iova[j];
|
2010-04-08 20:00:41 +00:00
|
|
|
struct dmar_domain *domain = deferred_flush[i].domain[j];
|
|
|
|
|
|
|
|
/* On real hardware multiple invalidations are expensive */
|
|
|
|
if (cap_caching_mode(iommu->cap))
|
|
|
|
iommu_flush_iotlb_psi(iommu, domain->id,
|
2014-07-11 06:19:36 +00:00
|
|
|
iova->pfn_lo, iova_size(iova),
|
2014-03-05 17:09:32 +00:00
|
|
|
!deferred_flush[i].freelist[j], 0);
|
2010-04-08 20:00:41 +00:00
|
|
|
else {
|
2014-07-11 06:19:36 +00:00
|
|
|
mask = ilog2(mm_to_dma_pfn(iova_size(iova)));
|
2010-04-08 20:00:41 +00:00
|
|
|
iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
|
|
|
|
(uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
|
|
|
|
}
|
2009-05-18 05:51:37 +00:00
|
|
|
__free_iova(&deferred_flush[i].domain[j]->iovad, iova);
|
2014-03-05 17:09:32 +00:00
|
|
|
if (deferred_flush[i].freelist[j])
|
|
|
|
dma_free_pagelist(deferred_flush[i].freelist[j]);
|
2008-04-18 20:53:58 +00:00
|
|
|
}
|
2009-05-18 05:51:36 +00:00
|
|
|
deferred_flush[i].next = 0;
|
2008-03-04 23:22:08 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
list_size = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void flush_unmaps_timeout(unsigned long data)
|
|
|
|
{
|
2008-04-18 20:53:58 +00:00
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&async_umap_flush_lock, flags);
|
2008-03-04 23:22:08 +00:00
|
|
|
flush_unmaps();
|
2008-04-18 20:53:58 +00:00
|
|
|
spin_unlock_irqrestore(&async_umap_flush_lock, flags);
|
2008-03-04 23:22:08 +00:00
|
|
|
}
|
|
|
|
|
2014-03-05 17:09:32 +00:00
|
|
|
static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist)
|
2008-03-04 23:22:08 +00:00
|
|
|
{
|
|
|
|
unsigned long flags;
|
2008-04-18 20:53:58 +00:00
|
|
|
int next, iommu_id;
|
2008-12-08 07:29:22 +00:00
|
|
|
struct intel_iommu *iommu;
|
2008-03-04 23:22:08 +00:00
|
|
|
|
|
|
|
spin_lock_irqsave(&async_umap_flush_lock, flags);
|
2008-04-18 20:53:58 +00:00
|
|
|
if (list_size == HIGH_WATER_MARK)
|
|
|
|
flush_unmaps();
|
|
|
|
|
2008-12-08 07:29:22 +00:00
|
|
|
iommu = domain_get_iommu(dom);
|
|
|
|
iommu_id = iommu->seq_id;
|
2008-07-10 18:16:36 +00:00
|
|
|
|
2008-04-18 20:53:58 +00:00
|
|
|
next = deferred_flush[iommu_id].next;
|
|
|
|
deferred_flush[iommu_id].domain[next] = dom;
|
|
|
|
deferred_flush[iommu_id].iova[next] = iova;
|
2014-03-05 17:09:32 +00:00
|
|
|
deferred_flush[iommu_id].freelist[next] = freelist;
|
2008-04-18 20:53:58 +00:00
|
|
|
deferred_flush[iommu_id].next++;
|
2008-03-04 23:22:08 +00:00
|
|
|
|
|
|
|
if (!timer_on) {
|
|
|
|
mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
|
|
|
|
timer_on = 1;
|
|
|
|
}
|
|
|
|
list_size++;
|
|
|
|
spin_unlock_irqrestore(&async_umap_flush_lock, flags);
|
|
|
|
}
|
|
|
|
|
2014-07-11 06:19:34 +00:00
|
|
|
static void intel_unmap(struct device *dev, dma_addr_t dev_addr)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
2007-10-21 23:41:58 +00:00
|
|
|
struct dmar_domain *domain;
|
2009-06-27 23:27:49 +00:00
|
|
|
unsigned long start_pfn, last_pfn;
|
2007-10-21 23:41:49 +00:00
|
|
|
struct iova *iova;
|
2008-12-08 07:29:22 +00:00
|
|
|
struct intel_iommu *iommu;
|
2014-03-05 17:09:32 +00:00
|
|
|
struct page *freelist;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2009-07-04 13:08:36 +00:00
|
|
|
if (iommu_no_mapping(dev))
|
2007-10-21 23:41:58 +00:00
|
|
|
return;
|
2009-06-19 20:47:29 +00:00
|
|
|
|
2014-03-06 16:19:30 +00:00
|
|
|
domain = find_domain(dev);
|
2007-10-21 23:41:49 +00:00
|
|
|
BUG_ON(!domain);
|
|
|
|
|
2008-12-08 07:29:22 +00:00
|
|
|
iommu = domain_get_iommu(domain);
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
|
2009-07-01 18:27:53 +00:00
|
|
|
if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
|
|
|
|
(unsigned long long)dev_addr))
|
2007-10-21 23:41:49 +00:00
|
|
|
return;
|
|
|
|
|
2009-06-27 23:27:49 +00:00
|
|
|
start_pfn = mm_to_dma_pfn(iova->pfn_lo);
|
|
|
|
last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2009-06-27 23:27:49 +00:00
|
|
|
pr_debug("Device %s unmapping: pfn %lx-%lx\n",
|
2014-03-09 23:12:32 +00:00
|
|
|
dev_name(dev), start_pfn, last_pfn);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2014-03-05 17:09:32 +00:00
|
|
|
freelist = domain_unmap(domain, start_pfn, last_pfn);
|
2009-06-27 23:27:49 +00:00
|
|
|
|
2008-03-04 23:22:08 +00:00
|
|
|
if (intel_iommu_strict) {
|
2009-06-28 14:33:46 +00:00
|
|
|
iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
|
2014-03-05 17:09:32 +00:00
|
|
|
last_pfn - start_pfn + 1, !freelist, 0);
|
2008-03-04 23:22:08 +00:00
|
|
|
/* free iova */
|
|
|
|
__free_iova(&domain->iovad, iova);
|
2014-03-05 17:09:32 +00:00
|
|
|
dma_free_pagelist(freelist);
|
2008-03-04 23:22:08 +00:00
|
|
|
} else {
|
2014-03-05 17:09:32 +00:00
|
|
|
add_unmap(domain, iova, freelist);
|
2008-03-04 23:22:08 +00:00
|
|
|
/*
|
|
|
|
* queue up the release of the unmap to save the 1/6th of the
|
|
|
|
* cpu used up by the iotlb flush operation...
|
|
|
|
*/
|
|
|
|
}
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2014-07-11 06:19:34 +00:00
|
|
|
static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
|
|
|
|
size_t size, enum dma_data_direction dir,
|
|
|
|
struct dma_attrs *attrs)
|
|
|
|
{
|
|
|
|
intel_unmap(dev, dev_addr);
|
|
|
|
}
|
|
|
|
|
2014-03-09 23:14:00 +00:00
|
|
|
static void *intel_alloc_coherent(struct device *dev, size_t size,
|
2012-03-27 12:28:18 +00:00
|
|
|
dma_addr_t *dma_handle, gfp_t flags,
|
|
|
|
struct dma_attrs *attrs)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
2014-06-04 23:06:51 +00:00
|
|
|
struct page *page = NULL;
|
2007-10-21 23:41:49 +00:00
|
|
|
int order;
|
|
|
|
|
2008-10-17 01:02:32 +00:00
|
|
|
size = PAGE_ALIGN(size);
|
2007-10-21 23:41:49 +00:00
|
|
|
order = get_order(size);
|
intel-iommu: Obey coherent_dma_mask for alloc_coherent on passthrough
The model for IOMMU passthrough is that decent devices that can cope
with DMA to all of memory get passthrough; crappy devices with a limited
dma_mask don't -- they get to use the IOMMU anyway.
This is done on the basis that IOMMU passthrough is usually wanted for
performance reasons, and it's only the decent PCI devices that you
really care about performance for, while the crappy 32-bit ones like
your USB controller can just use the IOMMU and you won't really care.
Unfortunately, the check for this was only looking at dev->dma_mask, not
at dev->coherent_dma_mask. And some devices have a 32-bit
coherent_dma_mask even though they have a full 64-bit dma_mask.
Even more unfortunately, fixing that simple oversight would upset
certain broken HP devices. Not only do they have a 32-bit
coherent_dma_mask, but they also have a tendency to do stray DMA to
unmapped addresses. And then they die when they take the DMA fault they
so richly deserve.
So if we do the 'correct' fix, it'll mean that affected users have to
disable IOMMU support completely on "a large percentage of servers from
a major vendor."
Personally, I have little sympathy -- given that this is the _same_
'major vendor' who is shipping machines which claim to have IOMMU
support but have obviously never _once_ booted a VT-d capable OS to do
any form of QA. But strictly speaking, it _would_ be a regression even
though it only ever worked by fluke.
For 2.6.33, we'll come up with a quirk which gives swiotlb support
for this particular device, and other devices with an inadequate
coherent_dma_mask will just get normal IOMMU mapping.
The simplest fix for 2.6.32, though, is just to jump through some hoops
to try to allocate coherent DMA memory for such devices in a place that
they can reach. We'd use dma_generic_alloc_coherent() for this if it
existed on IA64.
Signed-off-by: Alex Williamson <alex.williamson@hp.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-11-04 22:59:34 +00:00
|
|
|
|
2014-03-09 23:14:00 +00:00
|
|
|
if (!iommu_no_mapping(dev))
|
intel-iommu: Obey coherent_dma_mask for alloc_coherent on passthrough
The model for IOMMU passthrough is that decent devices that can cope
with DMA to all of memory get passthrough; crappy devices with a limited
dma_mask don't -- they get to use the IOMMU anyway.
This is done on the basis that IOMMU passthrough is usually wanted for
performance reasons, and it's only the decent PCI devices that you
really care about performance for, while the crappy 32-bit ones like
your USB controller can just use the IOMMU and you won't really care.
Unfortunately, the check for this was only looking at dev->dma_mask, not
at dev->coherent_dma_mask. And some devices have a 32-bit
coherent_dma_mask even though they have a full 64-bit dma_mask.
Even more unfortunately, fixing that simple oversight would upset
certain broken HP devices. Not only do they have a 32-bit
coherent_dma_mask, but they also have a tendency to do stray DMA to
unmapped addresses. And then they die when they take the DMA fault they
so richly deserve.
So if we do the 'correct' fix, it'll mean that affected users have to
disable IOMMU support completely on "a large percentage of servers from
a major vendor."
Personally, I have little sympathy -- given that this is the _same_
'major vendor' who is shipping machines which claim to have IOMMU
support but have obviously never _once_ booted a VT-d capable OS to do
any form of QA. But strictly speaking, it _would_ be a regression even
though it only ever worked by fluke.
For 2.6.33, we'll come up with a quirk which gives swiotlb support
for this particular device, and other devices with an inadequate
coherent_dma_mask will just get normal IOMMU mapping.
The simplest fix for 2.6.32, though, is just to jump through some hoops
to try to allocate coherent DMA memory for such devices in a place that
they can reach. We'd use dma_generic_alloc_coherent() for this if it
existed on IA64.
Signed-off-by: Alex Williamson <alex.williamson@hp.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-11-04 22:59:34 +00:00
|
|
|
flags &= ~(GFP_DMA | GFP_DMA32);
|
2014-03-09 23:14:00 +00:00
|
|
|
else if (dev->coherent_dma_mask < dma_get_required_mask(dev)) {
|
|
|
|
if (dev->coherent_dma_mask < DMA_BIT_MASK(32))
|
intel-iommu: Obey coherent_dma_mask for alloc_coherent on passthrough
The model for IOMMU passthrough is that decent devices that can cope
with DMA to all of memory get passthrough; crappy devices with a limited
dma_mask don't -- they get to use the IOMMU anyway.
This is done on the basis that IOMMU passthrough is usually wanted for
performance reasons, and it's only the decent PCI devices that you
really care about performance for, while the crappy 32-bit ones like
your USB controller can just use the IOMMU and you won't really care.
Unfortunately, the check for this was only looking at dev->dma_mask, not
at dev->coherent_dma_mask. And some devices have a 32-bit
coherent_dma_mask even though they have a full 64-bit dma_mask.
Even more unfortunately, fixing that simple oversight would upset
certain broken HP devices. Not only do they have a 32-bit
coherent_dma_mask, but they also have a tendency to do stray DMA to
unmapped addresses. And then they die when they take the DMA fault they
so richly deserve.
So if we do the 'correct' fix, it'll mean that affected users have to
disable IOMMU support completely on "a large percentage of servers from
a major vendor."
Personally, I have little sympathy -- given that this is the _same_
'major vendor' who is shipping machines which claim to have IOMMU
support but have obviously never _once_ booted a VT-d capable OS to do
any form of QA. But strictly speaking, it _would_ be a regression even
though it only ever worked by fluke.
For 2.6.33, we'll come up with a quirk which gives swiotlb support
for this particular device, and other devices with an inadequate
coherent_dma_mask will just get normal IOMMU mapping.
The simplest fix for 2.6.32, though, is just to jump through some hoops
to try to allocate coherent DMA memory for such devices in a place that
they can reach. We'd use dma_generic_alloc_coherent() for this if it
existed on IA64.
Signed-off-by: Alex Williamson <alex.williamson@hp.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-11-04 22:59:34 +00:00
|
|
|
flags |= GFP_DMA;
|
|
|
|
else
|
|
|
|
flags |= GFP_DMA32;
|
|
|
|
}
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2014-06-04 23:06:51 +00:00
|
|
|
if (flags & __GFP_WAIT) {
|
|
|
|
unsigned int count = size >> PAGE_SHIFT;
|
|
|
|
|
|
|
|
page = dma_alloc_from_contiguous(dev, count, order);
|
|
|
|
if (page && iommu_no_mapping(dev) &&
|
|
|
|
page_to_phys(page) + size > dev->coherent_dma_mask) {
|
|
|
|
dma_release_from_contiguous(dev, page, count);
|
|
|
|
page = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!page)
|
|
|
|
page = alloc_pages(flags, order);
|
|
|
|
if (!page)
|
2007-10-21 23:41:49 +00:00
|
|
|
return NULL;
|
2014-06-04 23:06:51 +00:00
|
|
|
memset(page_address(page), 0, size);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2014-06-04 23:06:51 +00:00
|
|
|
*dma_handle = __intel_map_single(dev, page_to_phys(page), size,
|
2008-10-15 07:08:28 +00:00
|
|
|
DMA_BIDIRECTIONAL,
|
2014-03-09 23:14:00 +00:00
|
|
|
dev->coherent_dma_mask);
|
2007-10-21 23:41:49 +00:00
|
|
|
if (*dma_handle)
|
2014-06-04 23:06:51 +00:00
|
|
|
return page_address(page);
|
|
|
|
if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
|
|
|
|
__free_pages(page, order);
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2014-03-09 23:14:00 +00:00
|
|
|
static void intel_free_coherent(struct device *dev, size_t size, void *vaddr,
|
2012-03-27 12:28:18 +00:00
|
|
|
dma_addr_t dma_handle, struct dma_attrs *attrs)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
|
|
|
int order;
|
2014-06-04 23:06:51 +00:00
|
|
|
struct page *page = virt_to_page(vaddr);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2008-10-17 01:02:32 +00:00
|
|
|
size = PAGE_ALIGN(size);
|
2007-10-21 23:41:49 +00:00
|
|
|
order = get_order(size);
|
|
|
|
|
2014-07-11 06:19:34 +00:00
|
|
|
intel_unmap(dev, dma_handle);
|
2014-06-04 23:06:51 +00:00
|
|
|
if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
|
|
|
|
__free_pages(page, order);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2014-03-09 23:14:00 +00:00
|
|
|
static void intel_unmap_sg(struct device *dev, struct scatterlist *sglist,
|
2009-01-28 12:53:18 +00:00
|
|
|
int nelems, enum dma_data_direction dir,
|
|
|
|
struct dma_attrs *attrs)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
2014-07-11 06:19:34 +00:00
|
|
|
intel_unmap(dev, sglist[0].dma_address);
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int intel_nontranslate_map_sg(struct device *hddev,
|
2007-10-21 23:42:00 +00:00
|
|
|
struct scatterlist *sglist, int nelems, int dir)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
|
|
|
int i;
|
2007-10-21 23:42:00 +00:00
|
|
|
struct scatterlist *sg;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2007-10-21 23:42:00 +00:00
|
|
|
for_each_sg(sglist, sg, nelems, i) {
|
2007-10-23 07:32:25 +00:00
|
|
|
BUG_ON(!sg_page(sg));
|
2009-02-11 17:23:43 +00:00
|
|
|
sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
|
2007-10-21 23:42:00 +00:00
|
|
|
sg->dma_length = sg->length;
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
return nelems;
|
|
|
|
}
|
|
|
|
|
2014-03-09 23:14:00 +00:00
|
|
|
static int intel_map_sg(struct device *dev, struct scatterlist *sglist, int nelems,
|
2009-01-28 12:53:18 +00:00
|
|
|
enum dma_data_direction dir, struct dma_attrs *attrs)
|
2007-10-21 23:41:49 +00:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
struct dmar_domain *domain;
|
2007-10-21 23:41:58 +00:00
|
|
|
size_t size = 0;
|
|
|
|
int prot = 0;
|
|
|
|
struct iova *iova = NULL;
|
|
|
|
int ret;
|
2007-10-21 23:42:00 +00:00
|
|
|
struct scatterlist *sg;
|
2009-06-28 13:49:31 +00:00
|
|
|
unsigned long start_vpfn;
|
2008-12-08 07:29:22 +00:00
|
|
|
struct intel_iommu *iommu;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
|
|
|
BUG_ON(dir == DMA_NONE);
|
2014-03-09 23:14:00 +00:00
|
|
|
if (iommu_no_mapping(dev))
|
|
|
|
return intel_nontranslate_map_sg(dev, sglist, nelems, dir);
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2014-03-09 23:14:00 +00:00
|
|
|
domain = get_valid_domain_for_dev(dev);
|
2007-10-21 23:41:58 +00:00
|
|
|
if (!domain)
|
|
|
|
return 0;
|
|
|
|
|
2008-12-08 07:29:22 +00:00
|
|
|
iommu = domain_get_iommu(domain);
|
|
|
|
|
2009-06-28 13:49:31 +00:00
|
|
|
for_each_sg(sglist, sg, nelems, i)
|
2009-06-28 14:03:06 +00:00
|
|
|
size += aligned_nrpages(sg->offset, sg->length);
|
2007-10-21 23:41:58 +00:00
|
|
|
|
2014-03-09 23:14:00 +00:00
|
|
|
iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size),
|
|
|
|
*dev->dma_mask);
|
2007-10-21 23:41:58 +00:00
|
|
|
if (!iova) {
|
2007-10-21 23:42:00 +00:00
|
|
|
sglist->dma_length = 0;
|
2007-10-21 23:41:58 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check if DMAR supports zero-length reads on write only
|
|
|
|
* mappings..
|
|
|
|
*/
|
|
|
|
if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
|
2008-12-08 07:29:22 +00:00
|
|
|
!cap_zlr(iommu->cap))
|
2007-10-21 23:41:58 +00:00
|
|
|
prot |= DMA_PTE_READ;
|
|
|
|
if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
|
|
|
|
prot |= DMA_PTE_WRITE;
|
|
|
|
|
2009-06-28 13:49:31 +00:00
|
|
|
start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
|
2009-06-29 10:17:38 +00:00
|
|
|
|
2009-08-04 22:09:37 +00:00
|
|
|
ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
|
2009-06-29 10:17:38 +00:00
|
|
|
if (unlikely(ret)) {
|
|
|
|
dma_pte_free_pagetable(domain, start_vpfn,
|
|
|
|
start_vpfn + size - 1);
|
|
|
|
__free_iova(&domain->iovad, iova);
|
|
|
|
return 0;
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2009-05-10 18:58:49 +00:00
|
|
|
/* it's a non-present to present mapping. Only flush if caching mode */
|
|
|
|
if (cap_caching_mode(iommu->cap))
|
2014-03-05 17:09:32 +00:00
|
|
|
iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 0, 1);
|
2009-05-10 18:58:49 +00:00
|
|
|
else
|
2008-12-08 07:29:22 +00:00
|
|
|
iommu_flush_write_buffer(iommu);
|
2009-05-10 18:58:49 +00:00
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
return nelems;
|
|
|
|
}
|
|
|
|
|
2009-01-28 12:53:17 +00:00
|
|
|
static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
|
|
|
|
{
|
|
|
|
return !dma_addr;
|
|
|
|
}
|
|
|
|
|
2009-01-05 14:59:02 +00:00
|
|
|
struct dma_map_ops intel_dma_ops = {
|
2012-03-27 12:28:18 +00:00
|
|
|
.alloc = intel_alloc_coherent,
|
|
|
|
.free = intel_free_coherent,
|
2007-10-21 23:41:49 +00:00
|
|
|
.map_sg = intel_map_sg,
|
|
|
|
.unmap_sg = intel_unmap_sg,
|
2009-01-05 14:47:26 +00:00
|
|
|
.map_page = intel_map_page,
|
|
|
|
.unmap_page = intel_unmap_page,
|
2009-01-28 12:53:17 +00:00
|
|
|
.mapping_error = intel_mapping_error,
|
2007-10-21 23:41:49 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static inline int iommu_domain_cache_init(void)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
iommu_domain_cache = kmem_cache_create("iommu_domain",
|
|
|
|
sizeof(struct dmar_domain),
|
|
|
|
0,
|
|
|
|
SLAB_HWCACHE_ALIGN,
|
|
|
|
|
|
|
|
NULL);
|
|
|
|
if (!iommu_domain_cache) {
|
|
|
|
printk(KERN_ERR "Couldn't create iommu_domain cache\n");
|
|
|
|
ret = -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int iommu_devinfo_cache_init(void)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
|
|
|
|
sizeof(struct device_domain_info),
|
|
|
|
0,
|
|
|
|
SLAB_HWCACHE_ALIGN,
|
|
|
|
NULL);
|
|
|
|
if (!iommu_devinfo_cache) {
|
|
|
|
printk(KERN_ERR "Couldn't create devinfo cache\n");
|
|
|
|
ret = -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __init iommu_init_mempool(void)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
ret = iommu_iova_cache_init();
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = iommu_domain_cache_init();
|
|
|
|
if (ret)
|
|
|
|
goto domain_error;
|
|
|
|
|
|
|
|
ret = iommu_devinfo_cache_init();
|
|
|
|
if (!ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
kmem_cache_destroy(iommu_domain_cache);
|
|
|
|
domain_error:
|
2015-01-12 17:51:14 +00:00
|
|
|
iommu_iova_cache_destroy();
|
2007-10-21 23:41:49 +00:00
|
|
|
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __init iommu_exit_mempool(void)
|
|
|
|
{
|
|
|
|
kmem_cache_destroy(iommu_devinfo_cache);
|
|
|
|
kmem_cache_destroy(iommu_domain_cache);
|
2015-01-12 17:51:14 +00:00
|
|
|
iommu_iova_cache_destroy();
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
|
2010-07-23 22:47:56 +00:00
|
|
|
static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
u32 vtbar;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
/* We know that this device on this chipset has its own IOMMU.
|
|
|
|
* If we find it under a different IOMMU, then the BIOS is lying
|
|
|
|
* to us. Hope that the IOMMU for this device is actually
|
|
|
|
* disabled, and it needs no translation...
|
|
|
|
*/
|
|
|
|
rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
|
|
|
|
if (rc) {
|
|
|
|
/* "can't" happen */
|
|
|
|
dev_info(&pdev->dev, "failed to run vt-d quirk\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
vtbar &= 0xffff0000;
|
|
|
|
|
|
|
|
/* we know that the this iommu should be at offset 0xa000 from vtbar */
|
|
|
|
drhd = dmar_find_matched_drhd_unit(pdev);
|
|
|
|
if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
|
|
|
|
TAINT_FIRMWARE_WORKAROUND,
|
|
|
|
"BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
|
|
|
|
pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
|
|
|
|
}
|
|
|
|
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
static void __init init_no_remapping_devices(void)
|
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
2014-03-07 15:08:36 +00:00
|
|
|
struct device *dev;
|
2014-02-19 06:07:32 +00:00
|
|
|
int i;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
|
|
|
for_each_drhd_unit(drhd) {
|
|
|
|
if (!drhd->include_all) {
|
2014-02-19 06:07:32 +00:00
|
|
|
for_each_active_dev_scope(drhd->devices,
|
|
|
|
drhd->devices_cnt, i, dev)
|
|
|
|
break;
|
2014-03-07 15:08:36 +00:00
|
|
|
/* ignore DMAR unit if no devices exist */
|
2007-10-21 23:41:49 +00:00
|
|
|
if (i == drhd->devices_cnt)
|
|
|
|
drhd->ignored = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-01-06 06:18:18 +00:00
|
|
|
for_each_active_drhd_unit(drhd) {
|
|
|
|
if (drhd->include_all)
|
2007-10-21 23:41:49 +00:00
|
|
|
continue;
|
|
|
|
|
2014-02-19 06:07:32 +00:00
|
|
|
for_each_active_dev_scope(drhd->devices,
|
|
|
|
drhd->devices_cnt, i, dev)
|
2014-03-07 15:08:36 +00:00
|
|
|
if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev)))
|
2007-10-21 23:41:49 +00:00
|
|
|
break;
|
|
|
|
if (i < drhd->devices_cnt)
|
|
|
|
continue;
|
|
|
|
|
2011-10-14 19:59:46 +00:00
|
|
|
/* This IOMMU has *only* gfx devices. Either bypass it or
|
|
|
|
set the gfx_mapped flag, as appropriate */
|
|
|
|
if (dmar_map_gfx) {
|
|
|
|
intel_iommu_gfx_mapped = 1;
|
|
|
|
} else {
|
|
|
|
drhd->ignored = 1;
|
2014-02-19 06:07:32 +00:00
|
|
|
for_each_active_dev_scope(drhd->devices,
|
|
|
|
drhd->devices_cnt, i, dev)
|
2014-03-07 15:08:36 +00:00
|
|
|
dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-03-27 21:22:42 +00:00
|
|
|
#ifdef CONFIG_SUSPEND
|
|
|
|
static int init_iommu_hw(void)
|
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
struct intel_iommu *iommu = NULL;
|
|
|
|
|
|
|
|
for_each_active_iommu(iommu, drhd)
|
|
|
|
if (iommu->qi)
|
|
|
|
dmar_reenable_qi(iommu);
|
|
|
|
|
2011-05-03 07:08:37 +00:00
|
|
|
for_each_iommu(iommu, drhd) {
|
|
|
|
if (drhd->ignored) {
|
|
|
|
/*
|
|
|
|
* we always have to disable PMRs or DMA may fail on
|
|
|
|
* this device
|
|
|
|
*/
|
|
|
|
if (force_on)
|
|
|
|
iommu_disable_protect_mem_regions(iommu);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2009-03-27 21:22:42 +00:00
|
|
|
iommu_flush_write_buffer(iommu);
|
|
|
|
|
|
|
|
iommu_set_root_entry(iommu);
|
|
|
|
|
|
|
|
iommu->flush.flush_context(iommu, 0, 0, 0,
|
2009-05-10 18:58:49 +00:00
|
|
|
DMA_CCMD_GLOBAL_INVL);
|
2014-07-11 06:19:33 +00:00
|
|
|
iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
|
|
|
|
iommu_enable_translation(iommu);
|
2009-09-19 22:28:12 +00:00
|
|
|
iommu_disable_protect_mem_regions(iommu);
|
2009-03-27 21:22:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void iommu_flush_all(void)
|
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
struct intel_iommu *iommu;
|
|
|
|
|
|
|
|
for_each_active_iommu(iommu, drhd) {
|
|
|
|
iommu->flush.flush_context(iommu, 0, 0, 0,
|
2009-05-10 18:58:49 +00:00
|
|
|
DMA_CCMD_GLOBAL_INVL);
|
2009-03-27 21:22:42 +00:00
|
|
|
iommu->flush.flush_iotlb(iommu, 0, 0, 0,
|
2009-05-10 18:58:49 +00:00
|
|
|
DMA_TLB_GLOBAL_FLUSH);
|
2009-03-27 21:22:42 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-03-23 21:16:14 +00:00
|
|
|
static int iommu_suspend(void)
|
2009-03-27 21:22:42 +00:00
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
struct intel_iommu *iommu = NULL;
|
|
|
|
unsigned long flag;
|
|
|
|
|
|
|
|
for_each_active_iommu(iommu, drhd) {
|
|
|
|
iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
|
|
|
|
GFP_ATOMIC);
|
|
|
|
if (!iommu->iommu_state)
|
|
|
|
goto nomem;
|
|
|
|
}
|
|
|
|
|
|
|
|
iommu_flush_all();
|
|
|
|
|
|
|
|
for_each_active_iommu(iommu, drhd) {
|
|
|
|
iommu_disable_translation(iommu);
|
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_lock_irqsave(&iommu->register_lock, flag);
|
2009-03-27 21:22:42 +00:00
|
|
|
|
|
|
|
iommu->iommu_state[SR_DMAR_FECTL_REG] =
|
|
|
|
readl(iommu->reg + DMAR_FECTL_REG);
|
|
|
|
iommu->iommu_state[SR_DMAR_FEDATA_REG] =
|
|
|
|
readl(iommu->reg + DMAR_FEDATA_REG);
|
|
|
|
iommu->iommu_state[SR_DMAR_FEADDR_REG] =
|
|
|
|
readl(iommu->reg + DMAR_FEADDR_REG);
|
|
|
|
iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
|
|
|
|
readl(iommu->reg + DMAR_FEUADDR_REG);
|
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
|
2009-03-27 21:22:42 +00:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
nomem:
|
|
|
|
for_each_active_iommu(iommu, drhd)
|
|
|
|
kfree(iommu->iommu_state);
|
|
|
|
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2011-03-23 21:16:14 +00:00
|
|
|
static void iommu_resume(void)
|
2009-03-27 21:22:42 +00:00
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
struct intel_iommu *iommu = NULL;
|
|
|
|
unsigned long flag;
|
|
|
|
|
|
|
|
if (init_iommu_hw()) {
|
2011-05-03 07:08:37 +00:00
|
|
|
if (force_on)
|
|
|
|
panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
|
|
|
|
else
|
|
|
|
WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
|
2011-03-23 21:16:14 +00:00
|
|
|
return;
|
2009-03-27 21:22:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
for_each_active_iommu(iommu, drhd) {
|
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_lock_irqsave(&iommu->register_lock, flag);
|
2009-03-27 21:22:42 +00:00
|
|
|
|
|
|
|
writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
|
|
|
|
iommu->reg + DMAR_FECTL_REG);
|
|
|
|
writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
|
|
|
|
iommu->reg + DMAR_FEDATA_REG);
|
|
|
|
writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
|
|
|
|
iommu->reg + DMAR_FEADDR_REG);
|
|
|
|
writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
|
|
|
|
iommu->reg + DMAR_FEUADDR_REG);
|
|
|
|
|
2011-07-19 14:19:51 +00:00
|
|
|
raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
|
2009-03-27 21:22:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
for_each_active_iommu(iommu, drhd)
|
|
|
|
kfree(iommu->iommu_state);
|
|
|
|
}
|
|
|
|
|
2011-03-23 21:16:14 +00:00
|
|
|
static struct syscore_ops iommu_syscore_ops = {
|
2009-03-27 21:22:42 +00:00
|
|
|
.resume = iommu_resume,
|
|
|
|
.suspend = iommu_suspend,
|
|
|
|
};
|
|
|
|
|
2011-03-23 21:16:14 +00:00
|
|
|
static void __init init_iommu_pm_ops(void)
|
2009-03-27 21:22:42 +00:00
|
|
|
{
|
2011-03-23 21:16:14 +00:00
|
|
|
register_syscore_ops(&iommu_syscore_ops);
|
2009-03-27 21:22:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
2011-06-07 19:32:31 +00:00
|
|
|
static inline void init_iommu_pm_ops(void) {}
|
2009-03-27 21:22:42 +00:00
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
|
2011-08-24 00:05:20 +00:00
|
|
|
|
2014-11-09 14:47:56 +00:00
|
|
|
int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg)
|
2011-08-24 00:05:20 +00:00
|
|
|
{
|
|
|
|
struct acpi_dmar_reserved_memory *rmrr;
|
|
|
|
struct dmar_rmrr_unit *rmrru;
|
|
|
|
|
|
|
|
rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
|
|
|
|
if (!rmrru)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
rmrru->hdr = header;
|
|
|
|
rmrr = (struct acpi_dmar_reserved_memory *)header;
|
|
|
|
rmrru->base_address = rmrr->base_address;
|
|
|
|
rmrru->end_address = rmrr->end_address;
|
2014-02-19 06:07:36 +00:00
|
|
|
rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1),
|
|
|
|
((void *)rmrr) + rmrr->header.length,
|
|
|
|
&rmrru->devices_cnt);
|
|
|
|
if (rmrru->devices_cnt && rmrru->devices == NULL) {
|
|
|
|
kfree(rmrru);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
2011-08-24 00:05:20 +00:00
|
|
|
|
2014-02-19 06:07:36 +00:00
|
|
|
list_add(&rmrru->list, &dmar_rmrr_units);
|
2011-08-24 00:05:20 +00:00
|
|
|
|
2014-02-19 06:07:36 +00:00
|
|
|
return 0;
|
2011-08-24 00:05:20 +00:00
|
|
|
}
|
|
|
|
|
2014-11-09 14:47:58 +00:00
|
|
|
static struct dmar_atsr_unit *dmar_find_atsr(struct acpi_dmar_atsr *atsr)
|
|
|
|
{
|
|
|
|
struct dmar_atsr_unit *atsru;
|
|
|
|
struct acpi_dmar_atsr *tmp;
|
|
|
|
|
|
|
|
list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
|
|
|
|
tmp = (struct acpi_dmar_atsr *)atsru->hdr;
|
|
|
|
if (atsr->segment != tmp->segment)
|
|
|
|
continue;
|
|
|
|
if (atsr->header.length != tmp->header.length)
|
|
|
|
continue;
|
|
|
|
if (memcmp(atsr, tmp, atsr->header.length) == 0)
|
|
|
|
return atsru;
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
int dmar_parse_one_atsr(struct acpi_dmar_header *hdr, void *arg)
|
2011-08-24 00:05:20 +00:00
|
|
|
{
|
|
|
|
struct acpi_dmar_atsr *atsr;
|
|
|
|
struct dmar_atsr_unit *atsru;
|
|
|
|
|
2014-11-09 14:47:58 +00:00
|
|
|
if (system_state != SYSTEM_BOOTING && !intel_iommu_enabled)
|
|
|
|
return 0;
|
|
|
|
|
2011-08-24 00:05:20 +00:00
|
|
|
atsr = container_of(hdr, struct acpi_dmar_atsr, header);
|
2014-11-09 14:47:58 +00:00
|
|
|
atsru = dmar_find_atsr(atsr);
|
|
|
|
if (atsru)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
atsru = kzalloc(sizeof(*atsru) + hdr->length, GFP_KERNEL);
|
2011-08-24 00:05:20 +00:00
|
|
|
if (!atsru)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2014-11-09 14:47:58 +00:00
|
|
|
/*
|
|
|
|
* If memory is allocated from slab by ACPI _DSM method, we need to
|
|
|
|
* copy the memory content because the memory buffer will be freed
|
|
|
|
* on return.
|
|
|
|
*/
|
|
|
|
atsru->hdr = (void *)(atsru + 1);
|
|
|
|
memcpy(atsru->hdr, hdr, hdr->length);
|
2011-08-24 00:05:20 +00:00
|
|
|
atsru->include_all = atsr->flags & 0x1;
|
2014-02-19 06:07:36 +00:00
|
|
|
if (!atsru->include_all) {
|
|
|
|
atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1),
|
|
|
|
(void *)atsr + atsr->header.length,
|
|
|
|
&atsru->devices_cnt);
|
|
|
|
if (atsru->devices_cnt && atsru->devices == NULL) {
|
|
|
|
kfree(atsru);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
}
|
2011-08-24 00:05:20 +00:00
|
|
|
|
2014-02-19 06:07:34 +00:00
|
|
|
list_add_rcu(&atsru->list, &dmar_atsr_units);
|
2011-08-24 00:05:20 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-01-06 06:18:27 +00:00
|
|
|
static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru)
|
|
|
|
{
|
|
|
|
dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt);
|
|
|
|
kfree(atsru);
|
|
|
|
}
|
|
|
|
|
2014-11-09 14:47:58 +00:00
|
|
|
int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg)
|
|
|
|
{
|
|
|
|
struct acpi_dmar_atsr *atsr;
|
|
|
|
struct dmar_atsr_unit *atsru;
|
|
|
|
|
|
|
|
atsr = container_of(hdr, struct acpi_dmar_atsr, header);
|
|
|
|
atsru = dmar_find_atsr(atsr);
|
|
|
|
if (atsru) {
|
|
|
|
list_del_rcu(&atsru->list);
|
|
|
|
synchronize_rcu();
|
|
|
|
intel_iommu_free_atsr(atsru);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
struct device *dev;
|
|
|
|
struct acpi_dmar_atsr *atsr;
|
|
|
|
struct dmar_atsr_unit *atsru;
|
|
|
|
|
|
|
|
atsr = container_of(hdr, struct acpi_dmar_atsr, header);
|
|
|
|
atsru = dmar_find_atsr(atsr);
|
|
|
|
if (!atsru)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (!atsru->include_all && atsru->devices && atsru->devices_cnt)
|
|
|
|
for_each_active_dev_scope(atsru->devices, atsru->devices_cnt,
|
|
|
|
i, dev)
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-11-09 14:48:02 +00:00
|
|
|
static int intel_iommu_add(struct dmar_drhd_unit *dmaru)
|
|
|
|
{
|
|
|
|
int sp, ret = 0;
|
|
|
|
struct intel_iommu *iommu = dmaru->iommu;
|
|
|
|
|
|
|
|
if (g_iommus[iommu->seq_id])
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (hw_pass_through && !ecap_pass_through(iommu->ecap)) {
|
|
|
|
pr_warn("IOMMU: %s doesn't support hardware pass through.\n",
|
|
|
|
iommu->name);
|
|
|
|
return -ENXIO;
|
|
|
|
}
|
|
|
|
if (!ecap_sc_support(iommu->ecap) &&
|
|
|
|
domain_update_iommu_snooping(iommu)) {
|
|
|
|
pr_warn("IOMMU: %s doesn't support snooping.\n",
|
|
|
|
iommu->name);
|
|
|
|
return -ENXIO;
|
|
|
|
}
|
|
|
|
sp = domain_update_iommu_superpage(iommu) - 1;
|
|
|
|
if (sp >= 0 && !(cap_super_page_val(iommu->cap) & (1 << sp))) {
|
|
|
|
pr_warn("IOMMU: %s doesn't support large page.\n",
|
|
|
|
iommu->name);
|
|
|
|
return -ENXIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable translation if already enabled prior to OS handover.
|
|
|
|
*/
|
|
|
|
if (iommu->gcmd & DMA_GCMD_TE)
|
|
|
|
iommu_disable_translation(iommu);
|
|
|
|
|
|
|
|
g_iommus[iommu->seq_id] = iommu;
|
|
|
|
ret = iommu_init_domains(iommu);
|
|
|
|
if (ret == 0)
|
|
|
|
ret = iommu_alloc_root_entry(iommu);
|
|
|
|
if (ret)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
if (dmaru->ignored) {
|
|
|
|
/*
|
|
|
|
* we always have to disable PMRs or DMA may fail on this device
|
|
|
|
*/
|
|
|
|
if (force_on)
|
|
|
|
iommu_disable_protect_mem_regions(iommu);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
intel_iommu_init_qi(iommu);
|
|
|
|
iommu_flush_write_buffer(iommu);
|
|
|
|
ret = dmar_set_interrupt(iommu);
|
|
|
|
if (ret)
|
|
|
|
goto disable_iommu;
|
|
|
|
|
|
|
|
iommu_set_root_entry(iommu);
|
|
|
|
iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
|
|
|
|
iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
|
|
|
|
iommu_enable_translation(iommu);
|
|
|
|
|
|
|
|
if (si_domain) {
|
|
|
|
ret = iommu_attach_domain(si_domain, iommu);
|
|
|
|
if (ret < 0 || si_domain->id != ret)
|
|
|
|
goto disable_iommu;
|
|
|
|
domain_attach_iommu(si_domain, iommu);
|
|
|
|
}
|
|
|
|
|
|
|
|
iommu_disable_protect_mem_regions(iommu);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
disable_iommu:
|
|
|
|
disable_dmar_iommu(iommu);
|
|
|
|
out:
|
|
|
|
free_dmar_iommu(iommu);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-11-09 14:47:58 +00:00
|
|
|
int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
|
|
|
|
{
|
2014-11-09 14:48:02 +00:00
|
|
|
int ret = 0;
|
|
|
|
struct intel_iommu *iommu = dmaru->iommu;
|
|
|
|
|
|
|
|
if (!intel_iommu_enabled)
|
|
|
|
return 0;
|
|
|
|
if (iommu == NULL)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (insert) {
|
|
|
|
ret = intel_iommu_add(dmaru);
|
|
|
|
} else {
|
|
|
|
disable_dmar_iommu(iommu);
|
|
|
|
free_dmar_iommu(iommu);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
2014-11-09 14:47:58 +00:00
|
|
|
}
|
|
|
|
|
2014-01-06 06:18:27 +00:00
|
|
|
static void intel_iommu_free_dmars(void)
|
|
|
|
{
|
|
|
|
struct dmar_rmrr_unit *rmrru, *rmrr_n;
|
|
|
|
struct dmar_atsr_unit *atsru, *atsr_n;
|
|
|
|
|
|
|
|
list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) {
|
|
|
|
list_del(&rmrru->list);
|
|
|
|
dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt);
|
|
|
|
kfree(rmrru);
|
2011-08-24 00:05:20 +00:00
|
|
|
}
|
|
|
|
|
2014-01-06 06:18:27 +00:00
|
|
|
list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) {
|
|
|
|
list_del(&atsru->list);
|
|
|
|
intel_iommu_free_atsr(atsru);
|
|
|
|
}
|
2011-08-24 00:05:20 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int dmar_find_matched_atsr_unit(struct pci_dev *dev)
|
|
|
|
{
|
2014-02-19 06:07:32 +00:00
|
|
|
int i, ret = 1;
|
2011-08-24 00:05:20 +00:00
|
|
|
struct pci_bus *bus;
|
2014-03-07 15:08:36 +00:00
|
|
|
struct pci_dev *bridge = NULL;
|
|
|
|
struct device *tmp;
|
2011-08-24 00:05:20 +00:00
|
|
|
struct acpi_dmar_atsr *atsr;
|
|
|
|
struct dmar_atsr_unit *atsru;
|
|
|
|
|
|
|
|
dev = pci_physfn(dev);
|
|
|
|
for (bus = dev->bus; bus; bus = bus->parent) {
|
iommu/vt-d: Fix error in detect ATS capability
Current Intel IOMMU driver only matches a PCIe root port with the first
DRHD unit with the samge segment number. It will report false result
if there are multiple DRHD units with the same segment number, thus fail
to detect ATS capability for some PCIe devices.
This patch refines function dmar_find_matched_atsr_unit() to search all
DRHD units with the same segment number.
An example DMAR table entries as below:
[1D0h 0464 2] Subtable Type : 0002 <Root Port ATS Capability>
[1D2h 0466 2] Length : 0028
[1D4h 0468 1] Flags : 00
[1D5h 0469 1] Reserved : 00
[1D6h 0470 2] PCI Segment Number : 0000
[1D8h 0472 1] Device Scope Entry Type : 02
[1D9h 0473 1] Entry Length : 08
[1DAh 0474 2] Reserved : 0000
[1DCh 0476 1] Enumeration ID : 00
[1DDh 0477 1] PCI Bus Number : 00
[1DEh 0478 2] PCI Path : [02, 00]
[1E0h 0480 1] Device Scope Entry Type : 02
[1E1h 0481 1] Entry Length : 08
[1E2h 0482 2] Reserved : 0000
[1E4h 0484 1] Enumeration ID : 00
[1E5h 0485 1] PCI Bus Number : 00
[1E6h 0486 2] PCI Path : [03, 00]
[1E8h 0488 1] Device Scope Entry Type : 02
[1E9h 0489 1] Entry Length : 08
[1EAh 0490 2] Reserved : 0000
[1ECh 0492 1] Enumeration ID : 00
[1EDh 0493 1] PCI Bus Number : 00
[1EEh 0494 2] PCI Path : [03, 02]
[1F0h 0496 1] Device Scope Entry Type : 02
[1F1h 0497 1] Entry Length : 08
[1F2h 0498 2] Reserved : 0000
[1F4h 0500 1] Enumeration ID : 00
[1F5h 0501 1] PCI Bus Number : 00
[1F6h 0502 2] PCI Path : [03, 03]
[1F8h 0504 2] Subtable Type : 0002 <Root Port ATS Capability>
[1FAh 0506 2] Length : 0020
[1FCh 0508 1] Flags : 00
[1FDh 0509 1] Reserved : 00
[1FEh 0510 2] PCI Segment Number : 0000
[200h 0512 1] Device Scope Entry Type : 02
[201h 0513 1] Entry Length : 08
[202h 0514 2] Reserved : 0000
[204h 0516 1] Enumeration ID : 00
[205h 0517 1] PCI Bus Number : 40
[206h 0518 2] PCI Path : [02, 00]
[208h 0520 1] Device Scope Entry Type : 02
[209h 0521 1] Entry Length : 08
[20Ah 0522 2] Reserved : 0000
[20Ch 0524 1] Enumeration ID : 00
[20Dh 0525 1] PCI Bus Number : 40
[20Eh 0526 2] PCI Path : [02, 02]
[210h 0528 1] Device Scope Entry Type : 02
[211h 0529 1] Entry Length : 08
[212h 0530 2] Reserved : 0000
[214h 0532 1] Enumeration ID : 00
[215h 0533 1] PCI Bus Number : 40
[216h 0534 2] PCI Path : [03, 00]
[218h 0536 2] Subtable Type : 0002 <Root Port ATS Capability>
[21Ah 0538 2] Length : 0020
[21Ch 0540 1] Flags : 00
[21Dh 0541 1] Reserved : 00
[21Eh 0542 2] PCI Segment Number : 0000
[220h 0544 1] Device Scope Entry Type : 02
[221h 0545 1] Entry Length : 08
[222h 0546 2] Reserved : 0000
[224h 0548 1] Enumeration ID : 00
[225h 0549 1] PCI Bus Number : 80
[226h 0550 2] PCI Path : [02, 00]
[228h 0552 1] Device Scope Entry Type : 02
[229h 0553 1] Entry Length : 08
[22Ah 0554 2] Reserved : 0000
[22Ch 0556 1] Enumeration ID : 00
[22Dh 0557 1] PCI Bus Number : 80
[22Eh 0558 2] PCI Path : [02, 02]
[230h 0560 1] Device Scope Entry Type : 02
[231h 0561 1] Entry Length : 08
[232h 0562 2] Reserved : 0000
[234h 0564 1] Enumeration ID : 00
[235h 0565 1] PCI Bus Number : 80
[236h 0566 2] PCI Path : [03, 00]
[238h 0568 2] Subtable Type : 0002 <Root Port ATS Capability>
[23Ah 0570 2] Length : 0020
[23Ch 0572 1] Flags : 00
[23Dh 0573 1] Reserved : 00
[23Eh 0574 2] PCI Segment Number : 0000
[240h 0576 1] Device Scope Entry Type : 02
[241h 0577 1] Entry Length : 08
[242h 0578 2] Reserved : 0000
[244h 0580 1] Enumeration ID : 00
[245h 0581 1] PCI Bus Number : C0
[246h 0582 2] PCI Path : [02, 00]
[248h 0584 1] Device Scope Entry Type : 02
[249h 0585 1] Entry Length : 08
[24Ah 0586 2] Reserved : 0000
[24Ch 0588 1] Enumeration ID : 00
[24Dh 0589 1] PCI Bus Number : C0
[24Eh 0590 2] PCI Path : [02, 02]
[250h 0592 1] Device Scope Entry Type : 02
[251h 0593 1] Entry Length : 08
[252h 0594 2] Reserved : 0000
[254h 0596 1] Enumeration ID : 00
[255h 0597 1] PCI Bus Number : C0
[256h 0598 2] PCI Path : [03, 00]
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:31 +00:00
|
|
|
bridge = bus->self;
|
2011-08-24 00:05:20 +00:00
|
|
|
if (!bridge || !pci_is_pcie(bridge) ||
|
2012-07-24 09:20:03 +00:00
|
|
|
pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
|
2011-08-24 00:05:20 +00:00
|
|
|
return 0;
|
iommu/vt-d: Fix error in detect ATS capability
Current Intel IOMMU driver only matches a PCIe root port with the first
DRHD unit with the samge segment number. It will report false result
if there are multiple DRHD units with the same segment number, thus fail
to detect ATS capability for some PCIe devices.
This patch refines function dmar_find_matched_atsr_unit() to search all
DRHD units with the same segment number.
An example DMAR table entries as below:
[1D0h 0464 2] Subtable Type : 0002 <Root Port ATS Capability>
[1D2h 0466 2] Length : 0028
[1D4h 0468 1] Flags : 00
[1D5h 0469 1] Reserved : 00
[1D6h 0470 2] PCI Segment Number : 0000
[1D8h 0472 1] Device Scope Entry Type : 02
[1D9h 0473 1] Entry Length : 08
[1DAh 0474 2] Reserved : 0000
[1DCh 0476 1] Enumeration ID : 00
[1DDh 0477 1] PCI Bus Number : 00
[1DEh 0478 2] PCI Path : [02, 00]
[1E0h 0480 1] Device Scope Entry Type : 02
[1E1h 0481 1] Entry Length : 08
[1E2h 0482 2] Reserved : 0000
[1E4h 0484 1] Enumeration ID : 00
[1E5h 0485 1] PCI Bus Number : 00
[1E6h 0486 2] PCI Path : [03, 00]
[1E8h 0488 1] Device Scope Entry Type : 02
[1E9h 0489 1] Entry Length : 08
[1EAh 0490 2] Reserved : 0000
[1ECh 0492 1] Enumeration ID : 00
[1EDh 0493 1] PCI Bus Number : 00
[1EEh 0494 2] PCI Path : [03, 02]
[1F0h 0496 1] Device Scope Entry Type : 02
[1F1h 0497 1] Entry Length : 08
[1F2h 0498 2] Reserved : 0000
[1F4h 0500 1] Enumeration ID : 00
[1F5h 0501 1] PCI Bus Number : 00
[1F6h 0502 2] PCI Path : [03, 03]
[1F8h 0504 2] Subtable Type : 0002 <Root Port ATS Capability>
[1FAh 0506 2] Length : 0020
[1FCh 0508 1] Flags : 00
[1FDh 0509 1] Reserved : 00
[1FEh 0510 2] PCI Segment Number : 0000
[200h 0512 1] Device Scope Entry Type : 02
[201h 0513 1] Entry Length : 08
[202h 0514 2] Reserved : 0000
[204h 0516 1] Enumeration ID : 00
[205h 0517 1] PCI Bus Number : 40
[206h 0518 2] PCI Path : [02, 00]
[208h 0520 1] Device Scope Entry Type : 02
[209h 0521 1] Entry Length : 08
[20Ah 0522 2] Reserved : 0000
[20Ch 0524 1] Enumeration ID : 00
[20Dh 0525 1] PCI Bus Number : 40
[20Eh 0526 2] PCI Path : [02, 02]
[210h 0528 1] Device Scope Entry Type : 02
[211h 0529 1] Entry Length : 08
[212h 0530 2] Reserved : 0000
[214h 0532 1] Enumeration ID : 00
[215h 0533 1] PCI Bus Number : 40
[216h 0534 2] PCI Path : [03, 00]
[218h 0536 2] Subtable Type : 0002 <Root Port ATS Capability>
[21Ah 0538 2] Length : 0020
[21Ch 0540 1] Flags : 00
[21Dh 0541 1] Reserved : 00
[21Eh 0542 2] PCI Segment Number : 0000
[220h 0544 1] Device Scope Entry Type : 02
[221h 0545 1] Entry Length : 08
[222h 0546 2] Reserved : 0000
[224h 0548 1] Enumeration ID : 00
[225h 0549 1] PCI Bus Number : 80
[226h 0550 2] PCI Path : [02, 00]
[228h 0552 1] Device Scope Entry Type : 02
[229h 0553 1] Entry Length : 08
[22Ah 0554 2] Reserved : 0000
[22Ch 0556 1] Enumeration ID : 00
[22Dh 0557 1] PCI Bus Number : 80
[22Eh 0558 2] PCI Path : [02, 02]
[230h 0560 1] Device Scope Entry Type : 02
[231h 0561 1] Entry Length : 08
[232h 0562 2] Reserved : 0000
[234h 0564 1] Enumeration ID : 00
[235h 0565 1] PCI Bus Number : 80
[236h 0566 2] PCI Path : [03, 00]
[238h 0568 2] Subtable Type : 0002 <Root Port ATS Capability>
[23Ah 0570 2] Length : 0020
[23Ch 0572 1] Flags : 00
[23Dh 0573 1] Reserved : 00
[23Eh 0574 2] PCI Segment Number : 0000
[240h 0576 1] Device Scope Entry Type : 02
[241h 0577 1] Entry Length : 08
[242h 0578 2] Reserved : 0000
[244h 0580 1] Enumeration ID : 00
[245h 0581 1] PCI Bus Number : C0
[246h 0582 2] PCI Path : [02, 00]
[248h 0584 1] Device Scope Entry Type : 02
[249h 0585 1] Entry Length : 08
[24Ah 0586 2] Reserved : 0000
[24Ch 0588 1] Enumeration ID : 00
[24Dh 0589 1] PCI Bus Number : C0
[24Eh 0590 2] PCI Path : [02, 02]
[250h 0592 1] Device Scope Entry Type : 02
[251h 0593 1] Entry Length : 08
[252h 0594 2] Reserved : 0000
[254h 0596 1] Enumeration ID : 00
[255h 0597 1] PCI Bus Number : C0
[256h 0598 2] PCI Path : [03, 00]
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:31 +00:00
|
|
|
if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT)
|
2011-08-24 00:05:20 +00:00
|
|
|
break;
|
|
|
|
}
|
iommu/vt-d: Fix error in detect ATS capability
Current Intel IOMMU driver only matches a PCIe root port with the first
DRHD unit with the samge segment number. It will report false result
if there are multiple DRHD units with the same segment number, thus fail
to detect ATS capability for some PCIe devices.
This patch refines function dmar_find_matched_atsr_unit() to search all
DRHD units with the same segment number.
An example DMAR table entries as below:
[1D0h 0464 2] Subtable Type : 0002 <Root Port ATS Capability>
[1D2h 0466 2] Length : 0028
[1D4h 0468 1] Flags : 00
[1D5h 0469 1] Reserved : 00
[1D6h 0470 2] PCI Segment Number : 0000
[1D8h 0472 1] Device Scope Entry Type : 02
[1D9h 0473 1] Entry Length : 08
[1DAh 0474 2] Reserved : 0000
[1DCh 0476 1] Enumeration ID : 00
[1DDh 0477 1] PCI Bus Number : 00
[1DEh 0478 2] PCI Path : [02, 00]
[1E0h 0480 1] Device Scope Entry Type : 02
[1E1h 0481 1] Entry Length : 08
[1E2h 0482 2] Reserved : 0000
[1E4h 0484 1] Enumeration ID : 00
[1E5h 0485 1] PCI Bus Number : 00
[1E6h 0486 2] PCI Path : [03, 00]
[1E8h 0488 1] Device Scope Entry Type : 02
[1E9h 0489 1] Entry Length : 08
[1EAh 0490 2] Reserved : 0000
[1ECh 0492 1] Enumeration ID : 00
[1EDh 0493 1] PCI Bus Number : 00
[1EEh 0494 2] PCI Path : [03, 02]
[1F0h 0496 1] Device Scope Entry Type : 02
[1F1h 0497 1] Entry Length : 08
[1F2h 0498 2] Reserved : 0000
[1F4h 0500 1] Enumeration ID : 00
[1F5h 0501 1] PCI Bus Number : 00
[1F6h 0502 2] PCI Path : [03, 03]
[1F8h 0504 2] Subtable Type : 0002 <Root Port ATS Capability>
[1FAh 0506 2] Length : 0020
[1FCh 0508 1] Flags : 00
[1FDh 0509 1] Reserved : 00
[1FEh 0510 2] PCI Segment Number : 0000
[200h 0512 1] Device Scope Entry Type : 02
[201h 0513 1] Entry Length : 08
[202h 0514 2] Reserved : 0000
[204h 0516 1] Enumeration ID : 00
[205h 0517 1] PCI Bus Number : 40
[206h 0518 2] PCI Path : [02, 00]
[208h 0520 1] Device Scope Entry Type : 02
[209h 0521 1] Entry Length : 08
[20Ah 0522 2] Reserved : 0000
[20Ch 0524 1] Enumeration ID : 00
[20Dh 0525 1] PCI Bus Number : 40
[20Eh 0526 2] PCI Path : [02, 02]
[210h 0528 1] Device Scope Entry Type : 02
[211h 0529 1] Entry Length : 08
[212h 0530 2] Reserved : 0000
[214h 0532 1] Enumeration ID : 00
[215h 0533 1] PCI Bus Number : 40
[216h 0534 2] PCI Path : [03, 00]
[218h 0536 2] Subtable Type : 0002 <Root Port ATS Capability>
[21Ah 0538 2] Length : 0020
[21Ch 0540 1] Flags : 00
[21Dh 0541 1] Reserved : 00
[21Eh 0542 2] PCI Segment Number : 0000
[220h 0544 1] Device Scope Entry Type : 02
[221h 0545 1] Entry Length : 08
[222h 0546 2] Reserved : 0000
[224h 0548 1] Enumeration ID : 00
[225h 0549 1] PCI Bus Number : 80
[226h 0550 2] PCI Path : [02, 00]
[228h 0552 1] Device Scope Entry Type : 02
[229h 0553 1] Entry Length : 08
[22Ah 0554 2] Reserved : 0000
[22Ch 0556 1] Enumeration ID : 00
[22Dh 0557 1] PCI Bus Number : 80
[22Eh 0558 2] PCI Path : [02, 02]
[230h 0560 1] Device Scope Entry Type : 02
[231h 0561 1] Entry Length : 08
[232h 0562 2] Reserved : 0000
[234h 0564 1] Enumeration ID : 00
[235h 0565 1] PCI Bus Number : 80
[236h 0566 2] PCI Path : [03, 00]
[238h 0568 2] Subtable Type : 0002 <Root Port ATS Capability>
[23Ah 0570 2] Length : 0020
[23Ch 0572 1] Flags : 00
[23Dh 0573 1] Reserved : 00
[23Eh 0574 2] PCI Segment Number : 0000
[240h 0576 1] Device Scope Entry Type : 02
[241h 0577 1] Entry Length : 08
[242h 0578 2] Reserved : 0000
[244h 0580 1] Enumeration ID : 00
[245h 0581 1] PCI Bus Number : C0
[246h 0582 2] PCI Path : [02, 00]
[248h 0584 1] Device Scope Entry Type : 02
[249h 0585 1] Entry Length : 08
[24Ah 0586 2] Reserved : 0000
[24Ch 0588 1] Enumeration ID : 00
[24Dh 0589 1] PCI Bus Number : C0
[24Eh 0590 2] PCI Path : [02, 02]
[250h 0592 1] Device Scope Entry Type : 02
[251h 0593 1] Entry Length : 08
[252h 0594 2] Reserved : 0000
[254h 0596 1] Enumeration ID : 00
[255h 0597 1] PCI Bus Number : C0
[256h 0598 2] PCI Path : [03, 00]
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:31 +00:00
|
|
|
if (!bridge)
|
|
|
|
return 0;
|
2011-08-24 00:05:20 +00:00
|
|
|
|
2014-02-19 06:07:34 +00:00
|
|
|
rcu_read_lock();
|
iommu/vt-d: Fix error in detect ATS capability
Current Intel IOMMU driver only matches a PCIe root port with the first
DRHD unit with the samge segment number. It will report false result
if there are multiple DRHD units with the same segment number, thus fail
to detect ATS capability for some PCIe devices.
This patch refines function dmar_find_matched_atsr_unit() to search all
DRHD units with the same segment number.
An example DMAR table entries as below:
[1D0h 0464 2] Subtable Type : 0002 <Root Port ATS Capability>
[1D2h 0466 2] Length : 0028
[1D4h 0468 1] Flags : 00
[1D5h 0469 1] Reserved : 00
[1D6h 0470 2] PCI Segment Number : 0000
[1D8h 0472 1] Device Scope Entry Type : 02
[1D9h 0473 1] Entry Length : 08
[1DAh 0474 2] Reserved : 0000
[1DCh 0476 1] Enumeration ID : 00
[1DDh 0477 1] PCI Bus Number : 00
[1DEh 0478 2] PCI Path : [02, 00]
[1E0h 0480 1] Device Scope Entry Type : 02
[1E1h 0481 1] Entry Length : 08
[1E2h 0482 2] Reserved : 0000
[1E4h 0484 1] Enumeration ID : 00
[1E5h 0485 1] PCI Bus Number : 00
[1E6h 0486 2] PCI Path : [03, 00]
[1E8h 0488 1] Device Scope Entry Type : 02
[1E9h 0489 1] Entry Length : 08
[1EAh 0490 2] Reserved : 0000
[1ECh 0492 1] Enumeration ID : 00
[1EDh 0493 1] PCI Bus Number : 00
[1EEh 0494 2] PCI Path : [03, 02]
[1F0h 0496 1] Device Scope Entry Type : 02
[1F1h 0497 1] Entry Length : 08
[1F2h 0498 2] Reserved : 0000
[1F4h 0500 1] Enumeration ID : 00
[1F5h 0501 1] PCI Bus Number : 00
[1F6h 0502 2] PCI Path : [03, 03]
[1F8h 0504 2] Subtable Type : 0002 <Root Port ATS Capability>
[1FAh 0506 2] Length : 0020
[1FCh 0508 1] Flags : 00
[1FDh 0509 1] Reserved : 00
[1FEh 0510 2] PCI Segment Number : 0000
[200h 0512 1] Device Scope Entry Type : 02
[201h 0513 1] Entry Length : 08
[202h 0514 2] Reserved : 0000
[204h 0516 1] Enumeration ID : 00
[205h 0517 1] PCI Bus Number : 40
[206h 0518 2] PCI Path : [02, 00]
[208h 0520 1] Device Scope Entry Type : 02
[209h 0521 1] Entry Length : 08
[20Ah 0522 2] Reserved : 0000
[20Ch 0524 1] Enumeration ID : 00
[20Dh 0525 1] PCI Bus Number : 40
[20Eh 0526 2] PCI Path : [02, 02]
[210h 0528 1] Device Scope Entry Type : 02
[211h 0529 1] Entry Length : 08
[212h 0530 2] Reserved : 0000
[214h 0532 1] Enumeration ID : 00
[215h 0533 1] PCI Bus Number : 40
[216h 0534 2] PCI Path : [03, 00]
[218h 0536 2] Subtable Type : 0002 <Root Port ATS Capability>
[21Ah 0538 2] Length : 0020
[21Ch 0540 1] Flags : 00
[21Dh 0541 1] Reserved : 00
[21Eh 0542 2] PCI Segment Number : 0000
[220h 0544 1] Device Scope Entry Type : 02
[221h 0545 1] Entry Length : 08
[222h 0546 2] Reserved : 0000
[224h 0548 1] Enumeration ID : 00
[225h 0549 1] PCI Bus Number : 80
[226h 0550 2] PCI Path : [02, 00]
[228h 0552 1] Device Scope Entry Type : 02
[229h 0553 1] Entry Length : 08
[22Ah 0554 2] Reserved : 0000
[22Ch 0556 1] Enumeration ID : 00
[22Dh 0557 1] PCI Bus Number : 80
[22Eh 0558 2] PCI Path : [02, 02]
[230h 0560 1] Device Scope Entry Type : 02
[231h 0561 1] Entry Length : 08
[232h 0562 2] Reserved : 0000
[234h 0564 1] Enumeration ID : 00
[235h 0565 1] PCI Bus Number : 80
[236h 0566 2] PCI Path : [03, 00]
[238h 0568 2] Subtable Type : 0002 <Root Port ATS Capability>
[23Ah 0570 2] Length : 0020
[23Ch 0572 1] Flags : 00
[23Dh 0573 1] Reserved : 00
[23Eh 0574 2] PCI Segment Number : 0000
[240h 0576 1] Device Scope Entry Type : 02
[241h 0577 1] Entry Length : 08
[242h 0578 2] Reserved : 0000
[244h 0580 1] Enumeration ID : 00
[245h 0581 1] PCI Bus Number : C0
[246h 0582 2] PCI Path : [02, 00]
[248h 0584 1] Device Scope Entry Type : 02
[249h 0585 1] Entry Length : 08
[24Ah 0586 2] Reserved : 0000
[24Ch 0588 1] Enumeration ID : 00
[24Dh 0589 1] PCI Bus Number : C0
[24Eh 0590 2] PCI Path : [02, 02]
[250h 0592 1] Device Scope Entry Type : 02
[251h 0593 1] Entry Length : 08
[252h 0594 2] Reserved : 0000
[254h 0596 1] Enumeration ID : 00
[255h 0597 1] PCI Bus Number : C0
[256h 0598 2] PCI Path : [03, 00]
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:31 +00:00
|
|
|
list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
|
|
|
|
atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
|
|
|
|
if (atsr->segment != pci_domain_nr(dev->bus))
|
|
|
|
continue;
|
|
|
|
|
2014-02-19 06:07:32 +00:00
|
|
|
for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp)
|
2014-03-07 15:08:36 +00:00
|
|
|
if (tmp == &bridge->dev)
|
2014-02-19 06:07:32 +00:00
|
|
|
goto out;
|
iommu/vt-d: Fix error in detect ATS capability
Current Intel IOMMU driver only matches a PCIe root port with the first
DRHD unit with the samge segment number. It will report false result
if there are multiple DRHD units with the same segment number, thus fail
to detect ATS capability for some PCIe devices.
This patch refines function dmar_find_matched_atsr_unit() to search all
DRHD units with the same segment number.
An example DMAR table entries as below:
[1D0h 0464 2] Subtable Type : 0002 <Root Port ATS Capability>
[1D2h 0466 2] Length : 0028
[1D4h 0468 1] Flags : 00
[1D5h 0469 1] Reserved : 00
[1D6h 0470 2] PCI Segment Number : 0000
[1D8h 0472 1] Device Scope Entry Type : 02
[1D9h 0473 1] Entry Length : 08
[1DAh 0474 2] Reserved : 0000
[1DCh 0476 1] Enumeration ID : 00
[1DDh 0477 1] PCI Bus Number : 00
[1DEh 0478 2] PCI Path : [02, 00]
[1E0h 0480 1] Device Scope Entry Type : 02
[1E1h 0481 1] Entry Length : 08
[1E2h 0482 2] Reserved : 0000
[1E4h 0484 1] Enumeration ID : 00
[1E5h 0485 1] PCI Bus Number : 00
[1E6h 0486 2] PCI Path : [03, 00]
[1E8h 0488 1] Device Scope Entry Type : 02
[1E9h 0489 1] Entry Length : 08
[1EAh 0490 2] Reserved : 0000
[1ECh 0492 1] Enumeration ID : 00
[1EDh 0493 1] PCI Bus Number : 00
[1EEh 0494 2] PCI Path : [03, 02]
[1F0h 0496 1] Device Scope Entry Type : 02
[1F1h 0497 1] Entry Length : 08
[1F2h 0498 2] Reserved : 0000
[1F4h 0500 1] Enumeration ID : 00
[1F5h 0501 1] PCI Bus Number : 00
[1F6h 0502 2] PCI Path : [03, 03]
[1F8h 0504 2] Subtable Type : 0002 <Root Port ATS Capability>
[1FAh 0506 2] Length : 0020
[1FCh 0508 1] Flags : 00
[1FDh 0509 1] Reserved : 00
[1FEh 0510 2] PCI Segment Number : 0000
[200h 0512 1] Device Scope Entry Type : 02
[201h 0513 1] Entry Length : 08
[202h 0514 2] Reserved : 0000
[204h 0516 1] Enumeration ID : 00
[205h 0517 1] PCI Bus Number : 40
[206h 0518 2] PCI Path : [02, 00]
[208h 0520 1] Device Scope Entry Type : 02
[209h 0521 1] Entry Length : 08
[20Ah 0522 2] Reserved : 0000
[20Ch 0524 1] Enumeration ID : 00
[20Dh 0525 1] PCI Bus Number : 40
[20Eh 0526 2] PCI Path : [02, 02]
[210h 0528 1] Device Scope Entry Type : 02
[211h 0529 1] Entry Length : 08
[212h 0530 2] Reserved : 0000
[214h 0532 1] Enumeration ID : 00
[215h 0533 1] PCI Bus Number : 40
[216h 0534 2] PCI Path : [03, 00]
[218h 0536 2] Subtable Type : 0002 <Root Port ATS Capability>
[21Ah 0538 2] Length : 0020
[21Ch 0540 1] Flags : 00
[21Dh 0541 1] Reserved : 00
[21Eh 0542 2] PCI Segment Number : 0000
[220h 0544 1] Device Scope Entry Type : 02
[221h 0545 1] Entry Length : 08
[222h 0546 2] Reserved : 0000
[224h 0548 1] Enumeration ID : 00
[225h 0549 1] PCI Bus Number : 80
[226h 0550 2] PCI Path : [02, 00]
[228h 0552 1] Device Scope Entry Type : 02
[229h 0553 1] Entry Length : 08
[22Ah 0554 2] Reserved : 0000
[22Ch 0556 1] Enumeration ID : 00
[22Dh 0557 1] PCI Bus Number : 80
[22Eh 0558 2] PCI Path : [02, 02]
[230h 0560 1] Device Scope Entry Type : 02
[231h 0561 1] Entry Length : 08
[232h 0562 2] Reserved : 0000
[234h 0564 1] Enumeration ID : 00
[235h 0565 1] PCI Bus Number : 80
[236h 0566 2] PCI Path : [03, 00]
[238h 0568 2] Subtable Type : 0002 <Root Port ATS Capability>
[23Ah 0570 2] Length : 0020
[23Ch 0572 1] Flags : 00
[23Dh 0573 1] Reserved : 00
[23Eh 0574 2] PCI Segment Number : 0000
[240h 0576 1] Device Scope Entry Type : 02
[241h 0577 1] Entry Length : 08
[242h 0578 2] Reserved : 0000
[244h 0580 1] Enumeration ID : 00
[245h 0581 1] PCI Bus Number : C0
[246h 0582 2] PCI Path : [02, 00]
[248h 0584 1] Device Scope Entry Type : 02
[249h 0585 1] Entry Length : 08
[24Ah 0586 2] Reserved : 0000
[24Ch 0588 1] Enumeration ID : 00
[24Dh 0589 1] PCI Bus Number : C0
[24Eh 0590 2] PCI Path : [02, 02]
[250h 0592 1] Device Scope Entry Type : 02
[251h 0593 1] Entry Length : 08
[252h 0594 2] Reserved : 0000
[254h 0596 1] Enumeration ID : 00
[255h 0597 1] PCI Bus Number : C0
[256h 0598 2] PCI Path : [03, 00]
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:31 +00:00
|
|
|
|
|
|
|
if (atsru->include_all)
|
2014-02-19 06:07:32 +00:00
|
|
|
goto out;
|
iommu/vt-d: Fix error in detect ATS capability
Current Intel IOMMU driver only matches a PCIe root port with the first
DRHD unit with the samge segment number. It will report false result
if there are multiple DRHD units with the same segment number, thus fail
to detect ATS capability for some PCIe devices.
This patch refines function dmar_find_matched_atsr_unit() to search all
DRHD units with the same segment number.
An example DMAR table entries as below:
[1D0h 0464 2] Subtable Type : 0002 <Root Port ATS Capability>
[1D2h 0466 2] Length : 0028
[1D4h 0468 1] Flags : 00
[1D5h 0469 1] Reserved : 00
[1D6h 0470 2] PCI Segment Number : 0000
[1D8h 0472 1] Device Scope Entry Type : 02
[1D9h 0473 1] Entry Length : 08
[1DAh 0474 2] Reserved : 0000
[1DCh 0476 1] Enumeration ID : 00
[1DDh 0477 1] PCI Bus Number : 00
[1DEh 0478 2] PCI Path : [02, 00]
[1E0h 0480 1] Device Scope Entry Type : 02
[1E1h 0481 1] Entry Length : 08
[1E2h 0482 2] Reserved : 0000
[1E4h 0484 1] Enumeration ID : 00
[1E5h 0485 1] PCI Bus Number : 00
[1E6h 0486 2] PCI Path : [03, 00]
[1E8h 0488 1] Device Scope Entry Type : 02
[1E9h 0489 1] Entry Length : 08
[1EAh 0490 2] Reserved : 0000
[1ECh 0492 1] Enumeration ID : 00
[1EDh 0493 1] PCI Bus Number : 00
[1EEh 0494 2] PCI Path : [03, 02]
[1F0h 0496 1] Device Scope Entry Type : 02
[1F1h 0497 1] Entry Length : 08
[1F2h 0498 2] Reserved : 0000
[1F4h 0500 1] Enumeration ID : 00
[1F5h 0501 1] PCI Bus Number : 00
[1F6h 0502 2] PCI Path : [03, 03]
[1F8h 0504 2] Subtable Type : 0002 <Root Port ATS Capability>
[1FAh 0506 2] Length : 0020
[1FCh 0508 1] Flags : 00
[1FDh 0509 1] Reserved : 00
[1FEh 0510 2] PCI Segment Number : 0000
[200h 0512 1] Device Scope Entry Type : 02
[201h 0513 1] Entry Length : 08
[202h 0514 2] Reserved : 0000
[204h 0516 1] Enumeration ID : 00
[205h 0517 1] PCI Bus Number : 40
[206h 0518 2] PCI Path : [02, 00]
[208h 0520 1] Device Scope Entry Type : 02
[209h 0521 1] Entry Length : 08
[20Ah 0522 2] Reserved : 0000
[20Ch 0524 1] Enumeration ID : 00
[20Dh 0525 1] PCI Bus Number : 40
[20Eh 0526 2] PCI Path : [02, 02]
[210h 0528 1] Device Scope Entry Type : 02
[211h 0529 1] Entry Length : 08
[212h 0530 2] Reserved : 0000
[214h 0532 1] Enumeration ID : 00
[215h 0533 1] PCI Bus Number : 40
[216h 0534 2] PCI Path : [03, 00]
[218h 0536 2] Subtable Type : 0002 <Root Port ATS Capability>
[21Ah 0538 2] Length : 0020
[21Ch 0540 1] Flags : 00
[21Dh 0541 1] Reserved : 00
[21Eh 0542 2] PCI Segment Number : 0000
[220h 0544 1] Device Scope Entry Type : 02
[221h 0545 1] Entry Length : 08
[222h 0546 2] Reserved : 0000
[224h 0548 1] Enumeration ID : 00
[225h 0549 1] PCI Bus Number : 80
[226h 0550 2] PCI Path : [02, 00]
[228h 0552 1] Device Scope Entry Type : 02
[229h 0553 1] Entry Length : 08
[22Ah 0554 2] Reserved : 0000
[22Ch 0556 1] Enumeration ID : 00
[22Dh 0557 1] PCI Bus Number : 80
[22Eh 0558 2] PCI Path : [02, 02]
[230h 0560 1] Device Scope Entry Type : 02
[231h 0561 1] Entry Length : 08
[232h 0562 2] Reserved : 0000
[234h 0564 1] Enumeration ID : 00
[235h 0565 1] PCI Bus Number : 80
[236h 0566 2] PCI Path : [03, 00]
[238h 0568 2] Subtable Type : 0002 <Root Port ATS Capability>
[23Ah 0570 2] Length : 0020
[23Ch 0572 1] Flags : 00
[23Dh 0573 1] Reserved : 00
[23Eh 0574 2] PCI Segment Number : 0000
[240h 0576 1] Device Scope Entry Type : 02
[241h 0577 1] Entry Length : 08
[242h 0578 2] Reserved : 0000
[244h 0580 1] Enumeration ID : 00
[245h 0581 1] PCI Bus Number : C0
[246h 0582 2] PCI Path : [02, 00]
[248h 0584 1] Device Scope Entry Type : 02
[249h 0585 1] Entry Length : 08
[24Ah 0586 2] Reserved : 0000
[24Ch 0588 1] Enumeration ID : 00
[24Dh 0589 1] PCI Bus Number : C0
[24Eh 0590 2] PCI Path : [02, 02]
[250h 0592 1] Device Scope Entry Type : 02
[251h 0593 1] Entry Length : 08
[252h 0594 2] Reserved : 0000
[254h 0596 1] Enumeration ID : 00
[255h 0597 1] PCI Bus Number : C0
[256h 0598 2] PCI Path : [03, 00]
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:31 +00:00
|
|
|
}
|
2014-02-19 06:07:32 +00:00
|
|
|
ret = 0;
|
|
|
|
out:
|
2014-02-19 06:07:34 +00:00
|
|
|
rcu_read_unlock();
|
2011-08-24 00:05:20 +00:00
|
|
|
|
2014-02-19 06:07:32 +00:00
|
|
|
return ret;
|
2011-08-24 00:05:20 +00:00
|
|
|
}
|
|
|
|
|
2014-02-19 06:07:35 +00:00
|
|
|
int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
struct dmar_rmrr_unit *rmrru;
|
|
|
|
struct dmar_atsr_unit *atsru;
|
|
|
|
struct acpi_dmar_atsr *atsr;
|
|
|
|
struct acpi_dmar_reserved_memory *rmrr;
|
|
|
|
|
|
|
|
if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
list_for_each_entry(rmrru, &dmar_rmrr_units, list) {
|
|
|
|
rmrr = container_of(rmrru->hdr,
|
|
|
|
struct acpi_dmar_reserved_memory, header);
|
|
|
|
if (info->event == BUS_NOTIFY_ADD_DEVICE) {
|
|
|
|
ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1),
|
|
|
|
((void *)rmrr) + rmrr->header.length,
|
|
|
|
rmrr->segment, rmrru->devices,
|
|
|
|
rmrru->devices_cnt);
|
2014-06-20 07:08:06 +00:00
|
|
|
if(ret < 0)
|
2014-02-19 06:07:35 +00:00
|
|
|
return ret;
|
|
|
|
} else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
|
2014-06-20 07:08:06 +00:00
|
|
|
dmar_remove_dev_scope(info, rmrr->segment,
|
|
|
|
rmrru->devices, rmrru->devices_cnt);
|
2014-02-19 06:07:35 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
list_for_each_entry(atsru, &dmar_atsr_units, list) {
|
|
|
|
if (atsru->include_all)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
|
|
|
|
if (info->event == BUS_NOTIFY_ADD_DEVICE) {
|
|
|
|
ret = dmar_insert_dev_scope(info, (void *)(atsr + 1),
|
|
|
|
(void *)atsr + atsr->header.length,
|
|
|
|
atsr->segment, atsru->devices,
|
|
|
|
atsru->devices_cnt);
|
|
|
|
if (ret > 0)
|
|
|
|
break;
|
|
|
|
else if(ret < 0)
|
|
|
|
return ret;
|
|
|
|
} else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
|
|
|
|
if (dmar_remove_dev_scope(info, atsr->segment,
|
|
|
|
atsru->devices, atsru->devices_cnt))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-11-11 15:23:06 +00:00
|
|
|
/*
|
|
|
|
* Here we only respond to action of unbound device from driver.
|
|
|
|
*
|
|
|
|
* Added device is not attached to its DMAR domain here yet. That will happen
|
|
|
|
* when mapping the device to iova.
|
|
|
|
*/
|
|
|
|
static int device_notifier(struct notifier_block *nb,
|
|
|
|
unsigned long action, void *data)
|
|
|
|
{
|
|
|
|
struct device *dev = data;
|
|
|
|
struct dmar_domain *domain;
|
|
|
|
|
2014-03-06 15:59:26 +00:00
|
|
|
if (iommu_dummy(dev))
|
2009-12-02 10:18:30 +00:00
|
|
|
return 0;
|
|
|
|
|
2014-09-30 11:02:03 +00:00
|
|
|
if (action != BUS_NOTIFY_REMOVED_DEVICE)
|
2014-02-19 06:07:23 +00:00
|
|
|
return 0;
|
|
|
|
|
2014-03-06 16:19:30 +00:00
|
|
|
domain = find_domain(dev);
|
2009-11-11 15:23:06 +00:00
|
|
|
if (!domain)
|
|
|
|
return 0;
|
|
|
|
|
iommu/vt-d: Introduce a rwsem to protect global data structures
Introduce a global rwsem dmar_global_lock, which will be used to
protect DMAR related global data structures from DMAR/PCI/memory
device hotplug operations in process context.
DMA and interrupt remapping related data structures are read most,
and only change when memory/PCI/DMAR hotplug event happens.
So a global rwsem solution is adopted for balance between simplicity
and performance.
For interrupt remapping driver, function intel_irq_remapping_supported(),
dmar_table_init(), intel_enable_irq_remapping(), disable_irq_remapping(),
reenable_irq_remapping() and enable_drhd_fault_handling() etc
are called during booting, suspending and resuming with interrupt
disabled, so no need to take the global lock.
For interrupt remapping entry allocation, the locking model is:
down_read(&dmar_global_lock);
/* Find corresponding iommu */
iommu = map_hpet_to_ir(id);
if (iommu)
/*
* Allocate remapping entry and mark entry busy,
* the IOMMU won't be hot-removed until the
* allocated entry has been released.
*/
index = alloc_irte(iommu, irq, 1);
up_read(&dmar_global_lock);
For DMA remmaping driver, we only uses the dmar_global_lock rwsem to
protect functions which are only called in process context. For any
function which may be called in interrupt context, we will use RCU
to protect them in following patches.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:33 +00:00
|
|
|
down_read(&dmar_global_lock);
|
2014-03-09 23:19:13 +00:00
|
|
|
domain_remove_one_dev_info(domain, dev);
|
2014-07-11 06:19:27 +00:00
|
|
|
if (!domain_type_is_vm_or_si(domain) && list_empty(&domain->devices))
|
2014-02-19 06:07:23 +00:00
|
|
|
domain_exit(domain);
|
iommu/vt-d: Introduce a rwsem to protect global data structures
Introduce a global rwsem dmar_global_lock, which will be used to
protect DMAR related global data structures from DMAR/PCI/memory
device hotplug operations in process context.
DMA and interrupt remapping related data structures are read most,
and only change when memory/PCI/DMAR hotplug event happens.
So a global rwsem solution is adopted for balance between simplicity
and performance.
For interrupt remapping driver, function intel_irq_remapping_supported(),
dmar_table_init(), intel_enable_irq_remapping(), disable_irq_remapping(),
reenable_irq_remapping() and enable_drhd_fault_handling() etc
are called during booting, suspending and resuming with interrupt
disabled, so no need to take the global lock.
For interrupt remapping entry allocation, the locking model is:
down_read(&dmar_global_lock);
/* Find corresponding iommu */
iommu = map_hpet_to_ir(id);
if (iommu)
/*
* Allocate remapping entry and mark entry busy,
* the IOMMU won't be hot-removed until the
* allocated entry has been released.
*/
index = alloc_irte(iommu, irq, 1);
up_read(&dmar_global_lock);
For DMA remmaping driver, we only uses the dmar_global_lock rwsem to
protect functions which are only called in process context. For any
function which may be called in interrupt context, we will use RCU
to protect them in following patches.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:33 +00:00
|
|
|
up_read(&dmar_global_lock);
|
2011-03-04 21:52:16 +00:00
|
|
|
|
2009-11-11 15:23:06 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct notifier_block device_nb = {
|
|
|
|
.notifier_call = device_notifier,
|
|
|
|
};
|
|
|
|
|
2014-02-19 06:07:37 +00:00
|
|
|
static int intel_iommu_memory_notifier(struct notifier_block *nb,
|
|
|
|
unsigned long val, void *v)
|
|
|
|
{
|
|
|
|
struct memory_notify *mhp = v;
|
|
|
|
unsigned long long start, end;
|
|
|
|
unsigned long start_vpfn, last_vpfn;
|
|
|
|
|
|
|
|
switch (val) {
|
|
|
|
case MEM_GOING_ONLINE:
|
|
|
|
start = mhp->start_pfn << PAGE_SHIFT;
|
|
|
|
end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1;
|
|
|
|
if (iommu_domain_identity_map(si_domain, start, end)) {
|
|
|
|
pr_warn("dmar: failed to build identity map for [%llx-%llx]\n",
|
|
|
|
start, end);
|
|
|
|
return NOTIFY_BAD;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MEM_OFFLINE:
|
|
|
|
case MEM_CANCEL_ONLINE:
|
|
|
|
start_vpfn = mm_to_dma_pfn(mhp->start_pfn);
|
|
|
|
last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1);
|
|
|
|
while (start_vpfn <= last_vpfn) {
|
|
|
|
struct iova *iova;
|
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
struct intel_iommu *iommu;
|
2014-03-05 17:09:32 +00:00
|
|
|
struct page *freelist;
|
2014-02-19 06:07:37 +00:00
|
|
|
|
|
|
|
iova = find_iova(&si_domain->iovad, start_vpfn);
|
|
|
|
if (iova == NULL) {
|
|
|
|
pr_debug("dmar: failed get IOVA for PFN %lx\n",
|
|
|
|
start_vpfn);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
iova = split_and_remove_iova(&si_domain->iovad, iova,
|
|
|
|
start_vpfn, last_vpfn);
|
|
|
|
if (iova == NULL) {
|
|
|
|
pr_warn("dmar: failed to split IOVA PFN [%lx-%lx]\n",
|
|
|
|
start_vpfn, last_vpfn);
|
|
|
|
return NOTIFY_BAD;
|
|
|
|
}
|
|
|
|
|
2014-03-05 17:09:32 +00:00
|
|
|
freelist = domain_unmap(si_domain, iova->pfn_lo,
|
|
|
|
iova->pfn_hi);
|
|
|
|
|
2014-02-19 06:07:37 +00:00
|
|
|
rcu_read_lock();
|
|
|
|
for_each_active_iommu(iommu, drhd)
|
|
|
|
iommu_flush_iotlb_psi(iommu, si_domain->id,
|
2014-07-11 06:19:36 +00:00
|
|
|
iova->pfn_lo, iova_size(iova),
|
2014-03-05 17:09:32 +00:00
|
|
|
!freelist, 0);
|
2014-02-19 06:07:37 +00:00
|
|
|
rcu_read_unlock();
|
2014-03-05 17:09:32 +00:00
|
|
|
dma_free_pagelist(freelist);
|
2014-02-19 06:07:37 +00:00
|
|
|
|
|
|
|
start_vpfn = iova->pfn_hi + 1;
|
|
|
|
free_iova_mem(iova);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return NOTIFY_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct notifier_block intel_iommu_memory_nb = {
|
|
|
|
.notifier_call = intel_iommu_memory_notifier,
|
|
|
|
.priority = 0
|
|
|
|
};
|
|
|
|
|
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
|
|
|
|
|
|
|
static ssize_t intel_iommu_show_version(struct device *dev,
|
|
|
|
struct device_attribute *attr,
|
|
|
|
char *buf)
|
|
|
|
{
|
|
|
|
struct intel_iommu *iommu = dev_get_drvdata(dev);
|
|
|
|
u32 ver = readl(iommu->reg + DMAR_VER_REG);
|
|
|
|
return sprintf(buf, "%d:%d\n",
|
|
|
|
DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver));
|
|
|
|
}
|
|
|
|
static DEVICE_ATTR(version, S_IRUGO, intel_iommu_show_version, NULL);
|
|
|
|
|
|
|
|
static ssize_t intel_iommu_show_address(struct device *dev,
|
|
|
|
struct device_attribute *attr,
|
|
|
|
char *buf)
|
|
|
|
{
|
|
|
|
struct intel_iommu *iommu = dev_get_drvdata(dev);
|
|
|
|
return sprintf(buf, "%llx\n", iommu->reg_phys);
|
|
|
|
}
|
|
|
|
static DEVICE_ATTR(address, S_IRUGO, intel_iommu_show_address, NULL);
|
|
|
|
|
|
|
|
static ssize_t intel_iommu_show_cap(struct device *dev,
|
|
|
|
struct device_attribute *attr,
|
|
|
|
char *buf)
|
|
|
|
{
|
|
|
|
struct intel_iommu *iommu = dev_get_drvdata(dev);
|
|
|
|
return sprintf(buf, "%llx\n", iommu->cap);
|
|
|
|
}
|
|
|
|
static DEVICE_ATTR(cap, S_IRUGO, intel_iommu_show_cap, NULL);
|
|
|
|
|
|
|
|
static ssize_t intel_iommu_show_ecap(struct device *dev,
|
|
|
|
struct device_attribute *attr,
|
|
|
|
char *buf)
|
|
|
|
{
|
|
|
|
struct intel_iommu *iommu = dev_get_drvdata(dev);
|
|
|
|
return sprintf(buf, "%llx\n", iommu->ecap);
|
|
|
|
}
|
|
|
|
static DEVICE_ATTR(ecap, S_IRUGO, intel_iommu_show_ecap, NULL);
|
|
|
|
|
|
|
|
static struct attribute *intel_iommu_attrs[] = {
|
|
|
|
&dev_attr_version.attr,
|
|
|
|
&dev_attr_address.attr,
|
|
|
|
&dev_attr_cap.attr,
|
|
|
|
&dev_attr_ecap.attr,
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct attribute_group intel_iommu_group = {
|
|
|
|
.name = "intel-iommu",
|
|
|
|
.attrs = intel_iommu_attrs,
|
|
|
|
};
|
|
|
|
|
|
|
|
const struct attribute_group *intel_iommu_groups[] = {
|
|
|
|
&intel_iommu_group,
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
int __init intel_iommu_init(void)
|
|
|
|
{
|
2014-01-06 06:18:27 +00:00
|
|
|
int ret = -ENODEV;
|
2013-04-23 08:35:03 +00:00
|
|
|
struct dmar_drhd_unit *drhd;
|
2014-01-06 06:18:18 +00:00
|
|
|
struct intel_iommu *iommu;
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2009-07-01 02:31:10 +00:00
|
|
|
/* VT-d is required for a TXT/tboot launch, so enforce that */
|
|
|
|
force_on = tboot_force_iommu();
|
|
|
|
|
iommu/vt-d: Introduce a rwsem to protect global data structures
Introduce a global rwsem dmar_global_lock, which will be used to
protect DMAR related global data structures from DMAR/PCI/memory
device hotplug operations in process context.
DMA and interrupt remapping related data structures are read most,
and only change when memory/PCI/DMAR hotplug event happens.
So a global rwsem solution is adopted for balance between simplicity
and performance.
For interrupt remapping driver, function intel_irq_remapping_supported(),
dmar_table_init(), intel_enable_irq_remapping(), disable_irq_remapping(),
reenable_irq_remapping() and enable_drhd_fault_handling() etc
are called during booting, suspending and resuming with interrupt
disabled, so no need to take the global lock.
For interrupt remapping entry allocation, the locking model is:
down_read(&dmar_global_lock);
/* Find corresponding iommu */
iommu = map_hpet_to_ir(id);
if (iommu)
/*
* Allocate remapping entry and mark entry busy,
* the IOMMU won't be hot-removed until the
* allocated entry has been released.
*/
index = alloc_irte(iommu, irq, 1);
up_read(&dmar_global_lock);
For DMA remmaping driver, we only uses the dmar_global_lock rwsem to
protect functions which are only called in process context. For any
function which may be called in interrupt context, we will use RCU
to protect them in following patches.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:33 +00:00
|
|
|
if (iommu_init_mempool()) {
|
|
|
|
if (force_on)
|
|
|
|
panic("tboot: Failed to initialize iommu memory\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
down_write(&dmar_global_lock);
|
2009-07-01 02:31:10 +00:00
|
|
|
if (dmar_table_init()) {
|
|
|
|
if (force_on)
|
|
|
|
panic("tboot: Failed to initialize DMAR table\n");
|
2014-01-06 06:18:27 +00:00
|
|
|
goto out_free_dmar;
|
2009-07-01 02:31:10 +00:00
|
|
|
}
|
2007-10-21 23:41:49 +00:00
|
|
|
|
2013-04-23 08:35:03 +00:00
|
|
|
/*
|
|
|
|
* Disable translation if already enabled prior to OS handover.
|
|
|
|
*/
|
2014-01-06 06:18:18 +00:00
|
|
|
for_each_active_iommu(iommu, drhd)
|
2013-04-23 08:35:03 +00:00
|
|
|
if (iommu->gcmd & DMA_GCMD_TE)
|
|
|
|
iommu_disable_translation(iommu);
|
|
|
|
|
2011-08-24 00:05:19 +00:00
|
|
|
if (dmar_dev_scope_init() < 0) {
|
2009-07-01 02:31:10 +00:00
|
|
|
if (force_on)
|
|
|
|
panic("tboot: Failed to initialize DMAR device scope\n");
|
2014-01-06 06:18:27 +00:00
|
|
|
goto out_free_dmar;
|
2009-07-01 02:31:10 +00:00
|
|
|
}
|
2008-07-10 18:16:37 +00:00
|
|
|
|
2009-11-10 10:46:20 +00:00
|
|
|
if (no_iommu || dmar_disabled)
|
2014-01-06 06:18:27 +00:00
|
|
|
goto out_free_dmar;
|
2008-07-10 18:16:43 +00:00
|
|
|
|
2011-08-24 00:05:20 +00:00
|
|
|
if (list_empty(&dmar_rmrr_units))
|
|
|
|
printk(KERN_INFO "DMAR: No RMRR found\n");
|
|
|
|
|
|
|
|
if (list_empty(&dmar_atsr_units))
|
|
|
|
printk(KERN_INFO "DMAR: No ATSR found\n");
|
|
|
|
|
2011-03-21 18:04:24 +00:00
|
|
|
if (dmar_init_reserved_ranges()) {
|
|
|
|
if (force_on)
|
|
|
|
panic("tboot: Failed to reserve iommu ranges\n");
|
iommu/vt-d: Introduce a rwsem to protect global data structures
Introduce a global rwsem dmar_global_lock, which will be used to
protect DMAR related global data structures from DMAR/PCI/memory
device hotplug operations in process context.
DMA and interrupt remapping related data structures are read most,
and only change when memory/PCI/DMAR hotplug event happens.
So a global rwsem solution is adopted for balance between simplicity
and performance.
For interrupt remapping driver, function intel_irq_remapping_supported(),
dmar_table_init(), intel_enable_irq_remapping(), disable_irq_remapping(),
reenable_irq_remapping() and enable_drhd_fault_handling() etc
are called during booting, suspending and resuming with interrupt
disabled, so no need to take the global lock.
For interrupt remapping entry allocation, the locking model is:
down_read(&dmar_global_lock);
/* Find corresponding iommu */
iommu = map_hpet_to_ir(id);
if (iommu)
/*
* Allocate remapping entry and mark entry busy,
* the IOMMU won't be hot-removed until the
* allocated entry has been released.
*/
index = alloc_irte(iommu, irq, 1);
up_read(&dmar_global_lock);
For DMA remmaping driver, we only uses the dmar_global_lock rwsem to
protect functions which are only called in process context. For any
function which may be called in interrupt context, we will use RCU
to protect them in following patches.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:33 +00:00
|
|
|
goto out_free_reserved_range;
|
2011-03-21 18:04:24 +00:00
|
|
|
}
|
2007-10-21 23:41:49 +00:00
|
|
|
|
|
|
|
init_no_remapping_devices();
|
|
|
|
|
2011-05-03 07:08:37 +00:00
|
|
|
ret = init_dmars();
|
2007-10-21 23:41:49 +00:00
|
|
|
if (ret) {
|
2009-07-01 02:31:10 +00:00
|
|
|
if (force_on)
|
|
|
|
panic("tboot: Failed to initialize DMARs\n");
|
2007-10-21 23:41:49 +00:00
|
|
|
printk(KERN_ERR "IOMMU: dmar init failed\n");
|
2014-01-06 06:18:27 +00:00
|
|
|
goto out_free_reserved_range;
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
iommu/vt-d: Introduce a rwsem to protect global data structures
Introduce a global rwsem dmar_global_lock, which will be used to
protect DMAR related global data structures from DMAR/PCI/memory
device hotplug operations in process context.
DMA and interrupt remapping related data structures are read most,
and only change when memory/PCI/DMAR hotplug event happens.
So a global rwsem solution is adopted for balance between simplicity
and performance.
For interrupt remapping driver, function intel_irq_remapping_supported(),
dmar_table_init(), intel_enable_irq_remapping(), disable_irq_remapping(),
reenable_irq_remapping() and enable_drhd_fault_handling() etc
are called during booting, suspending and resuming with interrupt
disabled, so no need to take the global lock.
For interrupt remapping entry allocation, the locking model is:
down_read(&dmar_global_lock);
/* Find corresponding iommu */
iommu = map_hpet_to_ir(id);
if (iommu)
/*
* Allocate remapping entry and mark entry busy,
* the IOMMU won't be hot-removed until the
* allocated entry has been released.
*/
index = alloc_irte(iommu, irq, 1);
up_read(&dmar_global_lock);
For DMA remmaping driver, we only uses the dmar_global_lock rwsem to
protect functions which are only called in process context. For any
function which may be called in interrupt context, we will use RCU
to protect them in following patches.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:33 +00:00
|
|
|
up_write(&dmar_global_lock);
|
2007-10-21 23:41:49 +00:00
|
|
|
printk(KERN_INFO
|
|
|
|
"PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
|
|
|
|
|
2008-03-04 23:22:08 +00:00
|
|
|
init_timer(&unmap_timer);
|
2009-11-10 10:46:20 +00:00
|
|
|
#ifdef CONFIG_SWIOTLB
|
|
|
|
swiotlb = 0;
|
|
|
|
#endif
|
2009-08-04 15:19:20 +00:00
|
|
|
dma_ops = &intel_dma_ops;
|
2009-04-25 00:30:20 +00:00
|
|
|
|
2011-03-23 21:16:14 +00:00
|
|
|
init_iommu_pm_ops();
|
2008-12-03 14:14:02 +00:00
|
|
|
|
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
|
|
|
for_each_active_iommu(iommu, drhd)
|
|
|
|
iommu->iommu_dev = iommu_device_create(NULL, iommu,
|
|
|
|
intel_iommu_groups,
|
|
|
|
iommu->name);
|
|
|
|
|
2011-09-06 15:56:07 +00:00
|
|
|
bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
|
2009-11-11 15:23:06 +00:00
|
|
|
bus_register_notifier(&pci_bus_type, &device_nb);
|
2014-02-19 06:07:37 +00:00
|
|
|
if (si_domain && !hw_pass_through)
|
|
|
|
register_memory_notifier(&intel_iommu_memory_nb);
|
2009-11-11 15:23:06 +00:00
|
|
|
|
2011-11-23 18:42:14 +00:00
|
|
|
intel_iommu_enabled = 1;
|
|
|
|
|
2007-10-21 23:41:49 +00:00
|
|
|
return 0;
|
2014-01-06 06:18:27 +00:00
|
|
|
|
|
|
|
out_free_reserved_range:
|
|
|
|
put_iova_domain(&reserved_iova_list);
|
|
|
|
out_free_dmar:
|
|
|
|
intel_iommu_free_dmars();
|
iommu/vt-d: Introduce a rwsem to protect global data structures
Introduce a global rwsem dmar_global_lock, which will be used to
protect DMAR related global data structures from DMAR/PCI/memory
device hotplug operations in process context.
DMA and interrupt remapping related data structures are read most,
and only change when memory/PCI/DMAR hotplug event happens.
So a global rwsem solution is adopted for balance between simplicity
and performance.
For interrupt remapping driver, function intel_irq_remapping_supported(),
dmar_table_init(), intel_enable_irq_remapping(), disable_irq_remapping(),
reenable_irq_remapping() and enable_drhd_fault_handling() etc
are called during booting, suspending and resuming with interrupt
disabled, so no need to take the global lock.
For interrupt remapping entry allocation, the locking model is:
down_read(&dmar_global_lock);
/* Find corresponding iommu */
iommu = map_hpet_to_ir(id);
if (iommu)
/*
* Allocate remapping entry and mark entry busy,
* the IOMMU won't be hot-removed until the
* allocated entry has been released.
*/
index = alloc_irte(iommu, irq, 1);
up_read(&dmar_global_lock);
For DMA remmaping driver, we only uses the dmar_global_lock rwsem to
protect functions which are only called in process context. For any
function which may be called in interrupt context, we will use RCU
to protect them in following patches.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:33 +00:00
|
|
|
up_write(&dmar_global_lock);
|
|
|
|
iommu_exit_mempool();
|
2014-01-06 06:18:27 +00:00
|
|
|
return ret;
|
2007-10-21 23:41:49 +00:00
|
|
|
}
|
2007-10-21 23:41:55 +00:00
|
|
|
|
2014-07-03 15:51:43 +00:00
|
|
|
static int iommu_detach_dev_cb(struct pci_dev *pdev, u16 alias, void *opaque)
|
|
|
|
{
|
|
|
|
struct intel_iommu *iommu = opaque;
|
|
|
|
|
|
|
|
iommu_detach_dev(iommu, PCI_BUS_NUM(alias), alias & 0xff);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* NB - intel-iommu lacks any sort of reference counting for the users of
|
|
|
|
* dependent devices. If multiple endpoints have intersecting dependent
|
|
|
|
* devices, unbinding the driver from any one of them will possibly leave
|
|
|
|
* the others unable to operate.
|
|
|
|
*/
|
2009-02-26 09:31:12 +00:00
|
|
|
static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
|
2014-03-06 17:12:03 +00:00
|
|
|
struct device *dev)
|
2009-02-26 09:31:12 +00:00
|
|
|
{
|
2014-03-06 17:12:03 +00:00
|
|
|
if (!iommu || !dev || !dev_is_pci(dev))
|
2009-02-26 09:31:12 +00:00
|
|
|
return;
|
|
|
|
|
2014-07-03 15:51:43 +00:00
|
|
|
pci_for_each_dma_alias(to_pci_dev(dev), &iommu_detach_dev_cb, iommu);
|
2009-02-26 09:31:12 +00:00
|
|
|
}
|
|
|
|
|
2009-06-19 20:47:29 +00:00
|
|
|
static void domain_remove_one_dev_info(struct dmar_domain *domain,
|
2014-03-09 23:19:13 +00:00
|
|
|
struct device *dev)
|
2008-12-08 14:51:37 +00:00
|
|
|
{
|
2013-10-31 09:26:04 +00:00
|
|
|
struct device_domain_info *info, *tmp;
|
2008-12-08 14:51:37 +00:00
|
|
|
struct intel_iommu *iommu;
|
|
|
|
unsigned long flags;
|
2015-02-06 09:59:53 +00:00
|
|
|
bool found = false;
|
2014-03-09 21:00:57 +00:00
|
|
|
u8 bus, devfn;
|
2008-12-08 14:51:37 +00:00
|
|
|
|
2014-03-09 23:19:13 +00:00
|
|
|
iommu = device_to_iommu(dev, &bus, &devfn);
|
2008-12-08 14:51:37 +00:00
|
|
|
if (!iommu)
|
|
|
|
return;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&device_domain_lock, flags);
|
2013-10-31 09:26:04 +00:00
|
|
|
list_for_each_entry_safe(info, tmp, &domain->devices, link) {
|
2014-03-09 23:19:13 +00:00
|
|
|
if (info->iommu == iommu && info->bus == bus &&
|
|
|
|
info->devfn == devfn) {
|
2012-05-25 16:43:02 +00:00
|
|
|
unlink_domain_info(info);
|
2008-12-08 14:51:37 +00:00
|
|
|
spin_unlock_irqrestore(&device_domain_lock, flags);
|
|
|
|
|
2009-05-18 05:51:37 +00:00
|
|
|
iommu_disable_dev_iotlb(info);
|
2008-12-08 14:51:37 +00:00
|
|
|
iommu_detach_dev(iommu, info->bus, info->devfn);
|
2014-03-09 23:19:13 +00:00
|
|
|
iommu_detach_dependent_devices(iommu, dev);
|
2008-12-08 14:51:37 +00:00
|
|
|
free_devinfo_mem(info);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&device_domain_lock, flags);
|
|
|
|
|
|
|
|
if (found)
|
|
|
|
break;
|
|
|
|
else
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* if there is no other devices under the same iommu
|
|
|
|
* owned by this domain, clear this iommu in iommu_bmp
|
|
|
|
* update iommu count and coherency
|
|
|
|
*/
|
2014-03-09 20:52:37 +00:00
|
|
|
if (info->iommu == iommu)
|
2015-02-06 09:59:53 +00:00
|
|
|
found = true;
|
2008-12-08 14:51:37 +00:00
|
|
|
}
|
|
|
|
|
intel-iommu: Fix AB-BA lockdep report
When unbinding a device so that I could pass it through to a KVM VM, I
got the lockdep report below. It looks like a legitimate lock
ordering problem:
- domain_context_mapping_one() takes iommu->lock and calls
iommu_support_dev_iotlb(), which takes device_domain_lock (inside
iommu->lock).
- domain_remove_one_dev_info() starts by taking device_domain_lock
then takes iommu->lock inside it (near the end of the function).
So this is the classic AB-BA deadlock. It looks like a safe fix is to
simply release device_domain_lock a bit earlier, since as far as I can
tell, it doesn't protect any of the stuff accessed at the end of
domain_remove_one_dev_info() anyway.
BTW, the use of device_domain_lock looks a bit unsafe to me... it's
at least not obvious to me why we aren't vulnerable to the race below:
iommu_support_dev_iotlb()
domain_remove_dev_info()
lock device_domain_lock
find info
unlock device_domain_lock
lock device_domain_lock
find same info
unlock device_domain_lock
free_devinfo_mem(info)
do stuff with info after it's free
However I don't understand the locking here well enough to know if
this is a real problem, let alone what the best fix is.
Anyway here's the full lockdep output that prompted all of this:
=======================================================
[ INFO: possible circular locking dependency detected ]
2.6.39.1+ #1
-------------------------------------------------------
bash/13954 is trying to acquire lock:
(&(&iommu->lock)->rlock){......}, at: [<ffffffff812f6421>] domain_remove_one_dev_info+0x121/0x230
but task is already holding lock:
(device_domain_lock){-.-...}, at: [<ffffffff812f6508>] domain_remove_one_dev_info+0x208/0x230
which lock already depends on the new lock.
the existing dependency chain (in reverse order) is:
-> #1 (device_domain_lock){-.-...}:
[<ffffffff8109ca9d>] lock_acquire+0x9d/0x130
[<ffffffff81571475>] _raw_spin_lock_irqsave+0x55/0xa0
[<ffffffff812f8350>] domain_context_mapping_one+0x600/0x750
[<ffffffff812f84df>] domain_context_mapping+0x3f/0x120
[<ffffffff812f9175>] iommu_prepare_identity_map+0x1c5/0x1e0
[<ffffffff81ccf1ca>] intel_iommu_init+0x88e/0xb5e
[<ffffffff81cab204>] pci_iommu_init+0x16/0x41
[<ffffffff81002165>] do_one_initcall+0x45/0x190
[<ffffffff81ca3d3f>] kernel_init+0xe3/0x168
[<ffffffff8157ac24>] kernel_thread_helper+0x4/0x10
-> #0 (&(&iommu->lock)->rlock){......}:
[<ffffffff8109bf3e>] __lock_acquire+0x195e/0x1e10
[<ffffffff8109ca9d>] lock_acquire+0x9d/0x130
[<ffffffff81571475>] _raw_spin_lock_irqsave+0x55/0xa0
[<ffffffff812f6421>] domain_remove_one_dev_info+0x121/0x230
[<ffffffff812f8b42>] device_notifier+0x72/0x90
[<ffffffff8157555c>] notifier_call_chain+0x8c/0xc0
[<ffffffff81089768>] __blocking_notifier_call_chain+0x78/0xb0
[<ffffffff810897b6>] blocking_notifier_call_chain+0x16/0x20
[<ffffffff81373a5c>] __device_release_driver+0xbc/0xe0
[<ffffffff81373ccf>] device_release_driver+0x2f/0x50
[<ffffffff81372ee3>] driver_unbind+0xa3/0xc0
[<ffffffff813724ac>] drv_attr_store+0x2c/0x30
[<ffffffff811e4506>] sysfs_write_file+0xe6/0x170
[<ffffffff8117569e>] vfs_write+0xce/0x190
[<ffffffff811759e4>] sys_write+0x54/0xa0
[<ffffffff81579a82>] system_call_fastpath+0x16/0x1b
other info that might help us debug this:
6 locks held by bash/13954:
#0: (&buffer->mutex){+.+.+.}, at: [<ffffffff811e4464>] sysfs_write_file+0x44/0x170
#1: (s_active#3){++++.+}, at: [<ffffffff811e44ed>] sysfs_write_file+0xcd/0x170
#2: (&__lockdep_no_validate__){+.+.+.}, at: [<ffffffff81372edb>] driver_unbind+0x9b/0xc0
#3: (&__lockdep_no_validate__){+.+.+.}, at: [<ffffffff81373cc7>] device_release_driver+0x27/0x50
#4: (&(&priv->bus_notifier)->rwsem){.+.+.+}, at: [<ffffffff8108974f>] __blocking_notifier_call_chain+0x5f/0xb0
#5: (device_domain_lock){-.-...}, at: [<ffffffff812f6508>] domain_remove_one_dev_info+0x208/0x230
stack backtrace:
Pid: 13954, comm: bash Not tainted 2.6.39.1+ #1
Call Trace:
[<ffffffff810993a7>] print_circular_bug+0xf7/0x100
[<ffffffff8109bf3e>] __lock_acquire+0x195e/0x1e10
[<ffffffff810972bd>] ? trace_hardirqs_off+0xd/0x10
[<ffffffff8109d57d>] ? trace_hardirqs_on_caller+0x13d/0x180
[<ffffffff8109ca9d>] lock_acquire+0x9d/0x130
[<ffffffff812f6421>] ? domain_remove_one_dev_info+0x121/0x230
[<ffffffff81571475>] _raw_spin_lock_irqsave+0x55/0xa0
[<ffffffff812f6421>] ? domain_remove_one_dev_info+0x121/0x230
[<ffffffff810972bd>] ? trace_hardirqs_off+0xd/0x10
[<ffffffff812f6421>] domain_remove_one_dev_info+0x121/0x230
[<ffffffff812f8b42>] device_notifier+0x72/0x90
[<ffffffff8157555c>] notifier_call_chain+0x8c/0xc0
[<ffffffff81089768>] __blocking_notifier_call_chain+0x78/0xb0
[<ffffffff810897b6>] blocking_notifier_call_chain+0x16/0x20
[<ffffffff81373a5c>] __device_release_driver+0xbc/0xe0
[<ffffffff81373ccf>] device_release_driver+0x2f/0x50
[<ffffffff81372ee3>] driver_unbind+0xa3/0xc0
[<ffffffff813724ac>] drv_attr_store+0x2c/0x30
[<ffffffff811e4506>] sysfs_write_file+0xe6/0x170
[<ffffffff8117569e>] vfs_write+0xce/0x190
[<ffffffff811759e4>] sys_write+0x54/0xa0
[<ffffffff81579a82>] system_call_fastpath+0x16/0x1b
Signed-off-by: Roland Dreier <roland@purestorage.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-07-20 13:22:21 +00:00
|
|
|
spin_unlock_irqrestore(&device_domain_lock, flags);
|
|
|
|
|
2008-12-08 14:51:37 +00:00
|
|
|
if (found == 0) {
|
2014-07-11 06:19:28 +00:00
|
|
|
domain_detach_iommu(domain, iommu);
|
|
|
|
if (!domain_type_is_vm_or_si(domain))
|
|
|
|
iommu_detach_domain(domain, iommu);
|
2008-12-08 14:51:37 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-06-19 20:47:29 +00:00
|
|
|
static int md_domain_init(struct dmar_domain *domain, int guest_width)
|
2008-12-08 15:03:27 +00:00
|
|
|
{
|
|
|
|
int adjust_width;
|
|
|
|
|
2015-01-12 17:51:16 +00:00
|
|
|
init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN,
|
|
|
|
DMA_32BIT_PFN);
|
2008-12-08 15:03:27 +00:00
|
|
|
domain_reserve_special_ranges(domain);
|
|
|
|
|
|
|
|
/* calculate AGAW */
|
|
|
|
domain->gaw = guest_width;
|
|
|
|
adjust_width = guestwidth_to_adjustwidth(guest_width);
|
|
|
|
domain->agaw = width_to_agaw(adjust_width);
|
|
|
|
|
|
|
|
domain->iommu_coherency = 0;
|
2009-08-06 05:31:56 +00:00
|
|
|
domain->iommu_snooping = 0;
|
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
|
|
|
domain->iommu_superpage = 0;
|
2008-12-08 15:10:23 +00:00
|
|
|
domain->max_addr = 0;
|
2008-12-08 15:03:27 +00:00
|
|
|
|
|
|
|
/* always allocate the top pgd */
|
2009-10-02 18:01:24 +00:00
|
|
|
domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
|
2008-12-08 15:03:27 +00:00
|
|
|
if (!domain->pgd)
|
|
|
|
return -ENOMEM;
|
|
|
|
domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-03-26 12:43:08 +00:00
|
|
|
static struct iommu_domain *intel_iommu_domain_alloc(unsigned type)
|
2008-09-09 15:37:29 +00:00
|
|
|
{
|
2008-12-03 13:52:32 +00:00
|
|
|
struct dmar_domain *dmar_domain;
|
2015-03-26 12:43:08 +00:00
|
|
|
struct iommu_domain *domain;
|
|
|
|
|
|
|
|
if (type != IOMMU_DOMAIN_UNMANAGED)
|
|
|
|
return NULL;
|
2008-09-09 15:37:29 +00:00
|
|
|
|
2014-07-11 06:19:27 +00:00
|
|
|
dmar_domain = alloc_domain(DOMAIN_FLAG_VIRTUAL_MACHINE);
|
2008-12-03 13:52:32 +00:00
|
|
|
if (!dmar_domain) {
|
2008-09-09 15:37:29 +00:00
|
|
|
printk(KERN_ERR
|
2008-12-03 13:52:32 +00:00
|
|
|
"intel_iommu_domain_init: dmar_domain == NULL\n");
|
2015-03-26 12:43:08 +00:00
|
|
|
return NULL;
|
2008-09-09 15:37:29 +00:00
|
|
|
}
|
2009-06-19 20:47:29 +00:00
|
|
|
if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
|
2008-09-09 15:37:29 +00:00
|
|
|
printk(KERN_ERR
|
2008-12-03 13:52:32 +00:00
|
|
|
"intel_iommu_domain_init() failed\n");
|
2014-02-19 06:07:28 +00:00
|
|
|
domain_exit(dmar_domain);
|
2015-03-26 12:43:08 +00:00
|
|
|
return NULL;
|
2008-09-09 15:37:29 +00:00
|
|
|
}
|
2011-10-14 19:32:17 +00:00
|
|
|
domain_update_iommu_cap(dmar_domain);
|
2008-12-08 15:09:29 +00:00
|
|
|
|
2015-03-26 12:43:08 +00:00
|
|
|
domain = &dmar_domain->domain;
|
2012-01-26 18:40:54 +00:00
|
|
|
domain->geometry.aperture_start = 0;
|
|
|
|
domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw);
|
|
|
|
domain->geometry.force_aperture = true;
|
|
|
|
|
2015-03-26 12:43:08 +00:00
|
|
|
return domain;
|
2008-09-09 15:37:29 +00:00
|
|
|
}
|
|
|
|
|
2015-03-26 12:43:08 +00:00
|
|
|
static void intel_iommu_domain_free(struct iommu_domain *domain)
|
2008-09-09 15:37:29 +00:00
|
|
|
{
|
2015-03-26 12:43:08 +00:00
|
|
|
domain_exit(to_dmar_domain(domain));
|
2008-09-09 15:37:29 +00:00
|
|
|
}
|
|
|
|
|
2008-12-03 13:58:24 +00:00
|
|
|
static int intel_iommu_attach_device(struct iommu_domain *domain,
|
|
|
|
struct device *dev)
|
2008-09-09 15:37:29 +00:00
|
|
|
{
|
2015-03-26 12:43:08 +00:00
|
|
|
struct dmar_domain *dmar_domain = to_dmar_domain(domain);
|
2008-12-08 15:10:23 +00:00
|
|
|
struct intel_iommu *iommu;
|
|
|
|
int addr_width;
|
2014-03-09 21:00:57 +00:00
|
|
|
u8 bus, devfn;
|
2008-12-08 15:09:29 +00:00
|
|
|
|
2014-07-03 15:57:02 +00:00
|
|
|
if (device_is_rmrr_locked(dev)) {
|
|
|
|
dev_warn(dev, "Device is ineligible for IOMMU domain attach due to platform RMRR requirement. Contact your platform vendor.\n");
|
|
|
|
return -EPERM;
|
|
|
|
}
|
|
|
|
|
2014-03-09 23:31:06 +00:00
|
|
|
/* normally dev is not mapped */
|
|
|
|
if (unlikely(domain_context_mapped(dev))) {
|
2008-12-08 15:09:29 +00:00
|
|
|
struct dmar_domain *old_domain;
|
|
|
|
|
2014-03-06 16:19:30 +00:00
|
|
|
old_domain = find_domain(dev);
|
2008-12-08 15:09:29 +00:00
|
|
|
if (old_domain) {
|
2014-07-11 06:19:27 +00:00
|
|
|
if (domain_type_is_vm_or_si(dmar_domain))
|
2014-03-09 23:19:13 +00:00
|
|
|
domain_remove_one_dev_info(old_domain, dev);
|
2008-12-08 15:09:29 +00:00
|
|
|
else
|
|
|
|
domain_remove_dev_info(old_domain);
|
2014-12-09 11:56:45 +00:00
|
|
|
|
|
|
|
if (!domain_type_is_vm_or_si(old_domain) &&
|
|
|
|
list_empty(&old_domain->devices))
|
|
|
|
domain_exit(old_domain);
|
2008-12-08 15:09:29 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-03-09 21:00:57 +00:00
|
|
|
iommu = device_to_iommu(dev, &bus, &devfn);
|
2008-12-08 15:10:23 +00:00
|
|
|
if (!iommu)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
/* check if this iommu agaw is sufficient for max mapped address */
|
|
|
|
addr_width = agaw_to_width(iommu->agaw);
|
2010-05-17 07:20:45 +00:00
|
|
|
if (addr_width > cap_mgaw(iommu->cap))
|
|
|
|
addr_width = cap_mgaw(iommu->cap);
|
|
|
|
|
|
|
|
if (dmar_domain->max_addr > (1LL << addr_width)) {
|
|
|
|
printk(KERN_ERR "%s: iommu width (%d) is not "
|
2008-12-08 15:10:23 +00:00
|
|
|
"sufficient for the mapped address (%llx)\n",
|
2010-05-17 07:20:45 +00:00
|
|
|
__func__, addr_width, dmar_domain->max_addr);
|
2008-12-08 15:10:23 +00:00
|
|
|
return -EFAULT;
|
|
|
|
}
|
2010-05-17 07:20:45 +00:00
|
|
|
dmar_domain->gaw = addr_width;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Knock out extra levels of page tables if necessary
|
|
|
|
*/
|
|
|
|
while (iommu->agaw < dmar_domain->agaw) {
|
|
|
|
struct dma_pte *pte;
|
|
|
|
|
|
|
|
pte = dmar_domain->pgd;
|
|
|
|
if (dma_pte_present(pte)) {
|
2010-06-12 11:21:42 +00:00
|
|
|
dmar_domain->pgd = (struct dma_pte *)
|
|
|
|
phys_to_virt(dma_pte_addr(pte));
|
2010-11-02 07:05:51 +00:00
|
|
|
free_pgtable_page(pte);
|
2010-05-17 07:20:45 +00:00
|
|
|
}
|
|
|
|
dmar_domain->agaw--;
|
|
|
|
}
|
2008-12-08 15:10:23 +00:00
|
|
|
|
2014-03-09 23:27:31 +00:00
|
|
|
return domain_add_dev_info(dmar_domain, dev, CONTEXT_TT_MULTI_LEVEL);
|
2008-09-09 15:37:29 +00:00
|
|
|
}
|
|
|
|
|
2008-12-03 13:58:24 +00:00
|
|
|
static void intel_iommu_detach_device(struct iommu_domain *domain,
|
|
|
|
struct device *dev)
|
2008-09-09 15:37:29 +00:00
|
|
|
{
|
2015-03-26 12:43:08 +00:00
|
|
|
domain_remove_one_dev_info(to_dmar_domain(domain), dev);
|
2008-12-08 15:09:29 +00:00
|
|
|
}
|
2008-12-08 14:51:37 +00:00
|
|
|
|
2010-01-20 16:17:37 +00:00
|
|
|
static int intel_iommu_map(struct iommu_domain *domain,
|
|
|
|
unsigned long iova, phys_addr_t hpa,
|
2011-11-10 09:32:25 +00:00
|
|
|
size_t size, int iommu_prot)
|
2008-12-08 15:09:29 +00:00
|
|
|
{
|
2015-03-26 12:43:08 +00:00
|
|
|
struct dmar_domain *dmar_domain = to_dmar_domain(domain);
|
2008-12-08 15:10:23 +00:00
|
|
|
u64 max_addr;
|
2008-12-03 14:04:09 +00:00
|
|
|
int prot = 0;
|
2008-12-08 15:09:29 +00:00
|
|
|
int ret;
|
2008-12-08 15:10:23 +00:00
|
|
|
|
2008-12-03 14:04:09 +00:00
|
|
|
if (iommu_prot & IOMMU_READ)
|
|
|
|
prot |= DMA_PTE_READ;
|
|
|
|
if (iommu_prot & IOMMU_WRITE)
|
|
|
|
prot |= DMA_PTE_WRITE;
|
2009-03-18 07:33:07 +00:00
|
|
|
if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
|
|
|
|
prot |= DMA_PTE_SNP;
|
2008-12-03 14:04:09 +00:00
|
|
|
|
2009-06-27 23:51:17 +00:00
|
|
|
max_addr = iova + size;
|
2008-12-03 14:04:09 +00:00
|
|
|
if (dmar_domain->max_addr < max_addr) {
|
2008-12-08 15:10:23 +00:00
|
|
|
u64 end;
|
|
|
|
|
|
|
|
/* check if minimum agaw is sufficient for mapped address */
|
2010-05-17 07:19:52 +00:00
|
|
|
end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
|
2008-12-08 15:10:23 +00:00
|
|
|
if (end < max_addr) {
|
2010-05-17 07:19:52 +00:00
|
|
|
printk(KERN_ERR "%s: iommu width (%d) is not "
|
2008-12-08 15:10:23 +00:00
|
|
|
"sufficient for the mapped address (%llx)\n",
|
2010-05-17 07:19:52 +00:00
|
|
|
__func__, dmar_domain->gaw, max_addr);
|
2008-12-08 15:10:23 +00:00
|
|
|
return -EFAULT;
|
|
|
|
}
|
2008-12-03 14:04:09 +00:00
|
|
|
dmar_domain->max_addr = max_addr;
|
2008-12-08 15:10:23 +00:00
|
|
|
}
|
2009-06-28 13:22:28 +00:00
|
|
|
/* Round up size to next multiple of PAGE_SIZE, if it and
|
|
|
|
the low bits of hpa would take us onto the next page */
|
2009-06-28 14:03:06 +00:00
|
|
|
size = aligned_nrpages(hpa, size);
|
2009-06-28 13:22:28 +00:00
|
|
|
ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
|
|
|
|
hpa >> VTD_PAGE_SHIFT, size, prot);
|
2008-12-08 15:09:29 +00:00
|
|
|
return ret;
|
2008-09-09 15:37:29 +00:00
|
|
|
}
|
|
|
|
|
2011-11-10 09:32:25 +00:00
|
|
|
static size_t intel_iommu_unmap(struct iommu_domain *domain,
|
2014-03-05 17:09:32 +00:00
|
|
|
unsigned long iova, size_t size)
|
2008-09-09 15:37:29 +00:00
|
|
|
{
|
2015-03-26 12:43:08 +00:00
|
|
|
struct dmar_domain *dmar_domain = to_dmar_domain(domain);
|
2014-03-05 17:09:32 +00:00
|
|
|
struct page *freelist = NULL;
|
|
|
|
struct intel_iommu *iommu;
|
|
|
|
unsigned long start_pfn, last_pfn;
|
|
|
|
unsigned int npages;
|
|
|
|
int iommu_id, num, ndomains, level = 0;
|
2014-03-19 16:07:49 +00:00
|
|
|
|
|
|
|
/* Cope with horrid API which requires us to unmap more than the
|
|
|
|
size argument if it happens to be a large-page mapping. */
|
|
|
|
if (!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level))
|
|
|
|
BUG();
|
|
|
|
|
|
|
|
if (size < VTD_PAGE_SIZE << level_to_offset_bits(level))
|
|
|
|
size = VTD_PAGE_SIZE << level_to_offset_bits(level);
|
2009-07-08 10:52:52 +00:00
|
|
|
|
2014-03-05 17:09:32 +00:00
|
|
|
start_pfn = iova >> VTD_PAGE_SHIFT;
|
|
|
|
last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT;
|
|
|
|
|
|
|
|
freelist = domain_unmap(dmar_domain, start_pfn, last_pfn);
|
|
|
|
|
|
|
|
npages = last_pfn - start_pfn + 1;
|
|
|
|
|
|
|
|
for_each_set_bit(iommu_id, dmar_domain->iommu_bmp, g_num_of_iommus) {
|
|
|
|
iommu = g_iommus[iommu_id];
|
|
|
|
|
|
|
|
/*
|
|
|
|
* find bit position of dmar_domain
|
|
|
|
*/
|
|
|
|
ndomains = cap_ndoms(iommu->cap);
|
|
|
|
for_each_set_bit(num, iommu->domain_ids, ndomains) {
|
|
|
|
if (iommu->domains[num] == dmar_domain)
|
|
|
|
iommu_flush_iotlb_psi(iommu, num, start_pfn,
|
|
|
|
npages, !freelist, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
dma_free_pagelist(freelist);
|
2008-12-08 15:10:23 +00:00
|
|
|
|
2009-06-27 23:51:17 +00:00
|
|
|
if (dmar_domain->max_addr == iova + size)
|
|
|
|
dmar_domain->max_addr = iova;
|
2010-01-20 16:17:37 +00:00
|
|
|
|
2014-03-19 16:07:49 +00:00
|
|
|
return size;
|
2008-09-09 15:37:29 +00:00
|
|
|
}
|
|
|
|
|
2008-12-03 14:06:57 +00:00
|
|
|
static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
|
2013-03-28 19:53:58 +00:00
|
|
|
dma_addr_t iova)
|
2008-09-09 15:37:29 +00:00
|
|
|
{
|
2015-03-26 12:43:08 +00:00
|
|
|
struct dmar_domain *dmar_domain = to_dmar_domain(domain);
|
2008-09-09 15:37:29 +00:00
|
|
|
struct dma_pte *pte;
|
2014-03-19 16:07:49 +00:00
|
|
|
int level = 0;
|
2008-12-08 15:09:29 +00:00
|
|
|
u64 phys = 0;
|
2008-09-09 15:37:29 +00:00
|
|
|
|
2014-03-19 16:07:49 +00:00
|
|
|
pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level);
|
2008-09-09 15:37:29 +00:00
|
|
|
if (pte)
|
2008-12-08 15:09:29 +00:00
|
|
|
phys = dma_pte_addr(pte);
|
2008-09-09 15:37:29 +00:00
|
|
|
|
2008-12-08 15:09:29 +00:00
|
|
|
return phys;
|
2008-09-09 15:37:29 +00:00
|
|
|
}
|
2008-12-03 14:14:02 +00:00
|
|
|
|
2014-09-05 08:50:45 +00:00
|
|
|
static bool intel_iommu_capable(enum iommu_cap cap)
|
2009-03-18 07:33:06 +00:00
|
|
|
{
|
|
|
|
if (cap == IOMMU_CAP_CACHE_COHERENCY)
|
2014-09-05 08:50:45 +00:00
|
|
|
return domain_update_iommu_snooping(NULL) == 1;
|
2010-07-02 20:56:14 +00:00
|
|
|
if (cap == IOMMU_CAP_INTR_REMAP)
|
2014-09-05 08:50:45 +00:00
|
|
|
return irq_remapping_enabled == 1;
|
2009-03-18 07:33:06 +00:00
|
|
|
|
2014-09-05 08:50:45 +00:00
|
|
|
return false;
|
2009-03-18 07:33:06 +00:00
|
|
|
}
|
|
|
|
|
2012-05-30 20:19:19 +00:00
|
|
|
static int intel_iommu_add_device(struct device *dev)
|
|
|
|
{
|
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
|
|
|
struct intel_iommu *iommu;
|
2012-05-30 20:19:19 +00:00
|
|
|
struct iommu_group *group;
|
2014-03-09 21:00:57 +00:00
|
|
|
u8 bus, devfn;
|
2011-10-21 19:56:11 +00:00
|
|
|
|
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
|
|
|
iommu = device_to_iommu(dev, &bus, &devfn);
|
|
|
|
if (!iommu)
|
2011-10-21 19:56:11 +00:00
|
|
|
return -ENODEV;
|
|
|
|
|
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
|
|
|
iommu_device_link(iommu->iommu_dev, dev);
|
2012-08-04 18:08:55 +00:00
|
|
|
|
2014-07-03 15:51:37 +00:00
|
|
|
group = iommu_group_get_for_dev(dev);
|
2012-05-30 20:19:43 +00:00
|
|
|
|
2014-07-03 15:51:37 +00:00
|
|
|
if (IS_ERR(group))
|
|
|
|
return PTR_ERR(group);
|
2011-10-21 19:56:24 +00:00
|
|
|
|
2012-05-30 20:19:19 +00:00
|
|
|
iommu_group_put(group);
|
2014-07-03 15:51:37 +00:00
|
|
|
return 0;
|
2012-05-30 20:19:19 +00:00
|
|
|
}
|
2011-10-21 19:56:11 +00:00
|
|
|
|
2012-05-30 20:19:19 +00:00
|
|
|
static void intel_iommu_remove_device(struct device *dev)
|
|
|
|
{
|
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
|
|
|
struct intel_iommu *iommu;
|
|
|
|
u8 bus, devfn;
|
|
|
|
|
|
|
|
iommu = device_to_iommu(dev, &bus, &devfn);
|
|
|
|
if (!iommu)
|
|
|
|
return;
|
|
|
|
|
2012-05-30 20:19:19 +00:00
|
|
|
iommu_group_remove_device(dev);
|
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
|
|
|
|
|
|
|
iommu_device_unlink(iommu->iommu_dev, dev);
|
2011-10-21 19:56:11 +00:00
|
|
|
}
|
|
|
|
|
2014-06-27 07:03:12 +00:00
|
|
|
static const struct iommu_ops intel_iommu_ops = {
|
2014-09-05 08:50:45 +00:00
|
|
|
.capable = intel_iommu_capable,
|
2015-03-26 12:43:08 +00:00
|
|
|
.domain_alloc = intel_iommu_domain_alloc,
|
|
|
|
.domain_free = intel_iommu_domain_free,
|
2008-12-03 14:14:02 +00:00
|
|
|
.attach_dev = intel_iommu_attach_device,
|
|
|
|
.detach_dev = intel_iommu_detach_device,
|
2010-01-20 16:17:37 +00:00
|
|
|
.map = intel_iommu_map,
|
|
|
|
.unmap = intel_iommu_unmap,
|
2014-10-25 16:55:16 +00:00
|
|
|
.map_sg = default_iommu_map_sg,
|
2008-12-03 14:14:02 +00:00
|
|
|
.iova_to_phys = intel_iommu_iova_to_phys,
|
2012-05-30 20:19:19 +00:00
|
|
|
.add_device = intel_iommu_add_device,
|
|
|
|
.remove_device = intel_iommu_remove_device,
|
2011-11-10 09:32:30 +00:00
|
|
|
.pgsize_bitmap = INTEL_IOMMU_PGSIZES,
|
2008-12-03 14:14:02 +00:00
|
|
|
};
|
2009-02-13 23:18:03 +00:00
|
|
|
|
2013-01-20 22:50:13 +00:00
|
|
|
static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
/* G4x/GM45 integrated gfx dmar support is totally busted. */
|
|
|
|
printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
|
|
|
|
dmar_map_gfx = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);
|
|
|
|
|
2012-12-21 23:05:21 +00:00
|
|
|
static void quirk_iommu_rwbf(struct pci_dev *dev)
|
2009-02-13 23:18:03 +00:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Mobile 4 Series Chipset neglects to set RWBF capability,
|
2013-01-21 18:48:59 +00:00
|
|
|
* but needs it. Same seems to hold for the desktop versions.
|
2009-02-13 23:18:03 +00:00
|
|
|
*/
|
|
|
|
printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
|
|
|
|
rwbf_quirk = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
|
2013-01-21 18:48:59 +00:00
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
|
2009-09-30 16:12:17 +00:00
|
|
|
|
2010-08-25 20:17:34 +00:00
|
|
|
#define GGC 0x52
|
|
|
|
#define GGC_MEMORY_SIZE_MASK (0xf << 8)
|
|
|
|
#define GGC_MEMORY_SIZE_NONE (0x0 << 8)
|
|
|
|
#define GGC_MEMORY_SIZE_1M (0x1 << 8)
|
|
|
|
#define GGC_MEMORY_SIZE_2M (0x3 << 8)
|
|
|
|
#define GGC_MEMORY_VT_ENABLED (0x8 << 8)
|
|
|
|
#define GGC_MEMORY_SIZE_2M_VT (0x9 << 8)
|
|
|
|
#define GGC_MEMORY_SIZE_3M_VT (0xa << 8)
|
|
|
|
#define GGC_MEMORY_SIZE_4M_VT (0xb << 8)
|
|
|
|
|
2012-12-21 23:05:21 +00:00
|
|
|
static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
|
2010-09-21 21:28:23 +00:00
|
|
|
{
|
|
|
|
unsigned short ggc;
|
|
|
|
|
2010-08-25 20:17:34 +00:00
|
|
|
if (pci_read_config_word(dev, GGC, &ggc))
|
2010-09-21 21:28:23 +00:00
|
|
|
return;
|
|
|
|
|
2010-08-25 20:17:34 +00:00
|
|
|
if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
|
2010-09-21 21:28:23 +00:00
|
|
|
printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
|
|
|
|
dmar_map_gfx = 0;
|
2011-09-26 02:11:14 +00:00
|
|
|
} else if (dmar_map_gfx) {
|
|
|
|
/* we have to ensure the gfx device is idle before we flush */
|
|
|
|
printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n");
|
|
|
|
intel_iommu_strict = 1;
|
|
|
|
}
|
2010-09-21 21:28:23 +00:00
|
|
|
}
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);
|
|
|
|
|
2009-09-30 16:12:17 +00:00
|
|
|
/* On Tylersburg chipsets, some BIOSes have been known to enable the
|
|
|
|
ISOCH DMAR unit for the Azalia sound device, but not give it any
|
|
|
|
TLB entries, which causes it to deadlock. Check for that. We do
|
|
|
|
this in a function called from init_dmars(), instead of in a PCI
|
|
|
|
quirk, because we don't want to print the obnoxious "BIOS broken"
|
|
|
|
message if VT-d is actually disabled.
|
|
|
|
*/
|
|
|
|
static void __init check_tylersburg_isoch(void)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev;
|
|
|
|
uint32_t vtisochctrl;
|
|
|
|
|
|
|
|
/* If there's no Azalia in the system anyway, forget it. */
|
|
|
|
pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
|
|
|
|
if (!pdev)
|
|
|
|
return;
|
|
|
|
pci_dev_put(pdev);
|
|
|
|
|
|
|
|
/* System Management Registers. Might be hidden, in which case
|
|
|
|
we can't do the sanity check. But that's OK, because the
|
|
|
|
known-broken BIOSes _don't_ actually hide it, so far. */
|
|
|
|
pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
|
|
|
|
if (!pdev)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
|
|
|
|
pci_dev_put(pdev);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
pci_dev_put(pdev);
|
|
|
|
|
|
|
|
/* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
|
|
|
|
if (vtisochctrl & 1)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Drop all bits other than the number of TLB entries */
|
|
|
|
vtisochctrl &= 0x1c;
|
|
|
|
|
|
|
|
/* If we have the recommended number of TLB entries (16), fine. */
|
|
|
|
if (vtisochctrl == 0x10)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Zero TLB entries? You get to ride the short bus to school. */
|
|
|
|
if (!vtisochctrl) {
|
|
|
|
WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
|
|
|
|
"BIOS vendor: %s; Ver: %s; Product Version: %s\n",
|
|
|
|
dmi_get_system_info(DMI_BIOS_VENDOR),
|
|
|
|
dmi_get_system_info(DMI_BIOS_VERSION),
|
|
|
|
dmi_get_system_info(DMI_PRODUCT_VERSION));
|
|
|
|
iommu_identity_mapping |= IDENTMAP_AZALIA;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
|
|
|
|
vtisochctrl);
|
|
|
|
}
|