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linux/drivers/mtd/spi-nor/Makefile

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mtd: spi-nor: shorten Kconfig naming Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Huang Shijie <b32955@freescale.com>
2014-04-09 03:30:25 +00:00
obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
mtd: spi-nor: add memory controllers for the Aspeed AST2500 SoC This driver adds mtd support for the Aspeed AST2500 SoC static memory controllers : * Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . supports SPI type flash memory (CE0-CE1) . CE2 can be of NOR type flash but this is not supported by the driver * SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1) . supports SPI type flash memory Each controller has a memory range on which it maps its flash module slaves. Each slave is assigned a memory window for its mapping that can be changed at bootime with the Segment Address Register. Each SPI flash slave can then be accessed in two modes: Command and User. When in User mode, accesses to the memory segment of the slaves are translated in SPI transfers. When in Command mode, the HW generates the SPI commands automatically and the memory segment is accessed as if doing a MMIO. Currently, only the User mode is supported. Command mode needs a little more work to check that the memory window on the AHB bus fits the module size. Based on previous work from Milton D. Miller II <miltonm@us.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2016-12-21 16:57:17 +00:00
obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
mtd: atmel-quadspi: add driver for Atmel QSPI controller This driver add support to the new Atmel QSPI controller embedded into sama5d2x SoCs. It expects a NOR memory to be connected to the QSPI controller. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-06-13 15:10:26 +00:00
obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o
mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller Add support for the Cadence QSPI controller. This controller is present in the Altera SoCFPGA SoCs and this driver has been tested on the Cyclone V SoC. Signed-off-by: Graham Moore <grmoore@opensource.altera.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alan Tull <atull@opensource.altera.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Graham Moore <grmoore@opensource.altera.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Yves Vandervennet <yvanderv@opensource.altera.com> Cc: devicetree@vger.kernel.org Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-06-04 00:39:34 +00:00
obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o
mtd: spi-nor: Add Freescale QuadSPI driver (0) What is the QuadSPI controller? The QuadSPI(Quad Serial Peripheral Interface) acts as an interface to one single or two external serial flash devices, each with up to 4 bidirectional data lines. (1) The QuadSPI controller is driven by the LUT(Look-up Table) registers. The LUT registers are a look-up-table for sequences of instructions. A valid sequence consists of four LUT registers. (2) The definition of the LUT register shows below: --------------------------------------------------- | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | --------------------------------------------------- There are several types of INSTRx, such as: CMD : the SPI NOR command. ADDR : the address for the SPI NOR command. DUMMY : the dummy cycles needed by the SPI NOR command. .... There are several types of PADx, such as: PAD1 : use a singe I/O line. PAD2 : use two I/O lines. PAD4 : use quad I/O lines. .... (3) Test this driver with the JFFS2 and UBIFS: For jffs2: ------------- #flash_eraseall /dev/mtd0 #mount -t jffs2 /dev/mtdblock0 tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 For ubifs: ------------- #flash_eraseall /dev/mtd0 #ubiattach /dev/ubi_ctrl -m 0 #ubimkvol /dev/ubi0 -N test -m #mount -t ubifs ubi0:test tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-02-24 10:37:42 +00:00
obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o
mtd: spi-nor: add hisilicon spi-nor flash controller driver Add hisilicon spi-nor flash controller driver Signed-off-by: Binquan Peng <pengbinquan@hisilicon.com> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-06-28 07:48:19 +00:00
obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
mtd: mtk-nor: new Mediatek serial flash controller driver Add spi nor flash driver for mediatek controller Signed-off-by: Bayi Cheng <bayi.cheng@mediatek.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-11-18 03:30:02 +00:00
obj-$(CONFIG_MTD_MT81xx_NOR) += mtk-quadspi.o
mtd: spi-nor: add driver for NXP SPI Flash Interface (SPIFI) Add SPI-NOR driver for the SPI Flash Interface (SPIFI) controller that is found on newer NXP MCU devices. The controller supports serial SPI Flash devices with 1-, 2- and 4-bit width in either SPI mode 0 or 3. The controller can operate in either command or memory mode. In memory mode the Flash is exposed as normal memory and can be directly accessed by the CPU. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-08-13 17:19:40 +00:00
obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
spi-nor: Add support for Intel SPI serial flash controller Add support for the SPI serial flash host controller found on many Intel CPUs including Baytrail and Braswell. The SPI serial flash controller is used to access BIOS and other platform specific information. By default the driver exposes a single read-only MTD device but with a module parameter "writeable=1" the MTD device can be made read-write which makes it possible to upgrade BIOS directly from Linux. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-11-28 12:06:24 +00:00
obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
mtd: spi-nor: intel-spi: Add support for Intel Denverton SPI serial flash controller Intel Denverton exposes the SPI serial flash controller as a PCI device instead of being part of the LPC chip as previous generations did. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
2017-06-29 11:45:42 +00:00
obj-$(CONFIG_SPI_INTEL_SPI_PCI) += intel-spi-pci.o
spi-nor: Add support for Intel SPI serial flash controller Add support for the SPI serial flash host controller found on many Intel CPUs including Baytrail and Braswell. The SPI serial flash controller is used to access BIOS and other platform specific information. By default the driver exposes a single read-only MTD device but with a module parameter "writeable=1" the MTD device can be made read-write which makes it possible to upgrade BIOS directly from Linux. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-11-28 12:06:24 +00:00
obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM) += intel-spi-platform.o
mtd: spi-nor: add driver for STM32 quad spi flash controller The quadspi is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the following modes: -indirect mode: all the operations are performed using the quadspi registers -read memory-mapped mode: the external Flash memory is mapped to the microcontroller address space and is seen by the system as if it was an internal memory Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-04-13 17:15:57 +00:00
obj-$(CONFIG_SPI_STM32_QUADSPI) += stm32-quadspi.o
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