forked from Minki/linux
mtd: spi-nor: add driver for STM32 quad spi flash controller
The quadspi is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the following modes: -indirect mode: all the operations are performed using the quadspi registers -read memory-mapped mode: the external Flash memory is mapped to the microcontroller address space and is seen by the system as if it was an internal memory Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
This commit is contained in:
Ludovic Barre
Cyrille Pitchen
parent
b0fcb4b413
commit
0d43d7ab27
@ -106,4 +106,11 @@ config SPI_INTEL_SPI_PLATFORM
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To compile this driver as a module, choose M here: the module
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will be called intel-spi-platform.
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config SPI_STM32_QUADSPI
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tristate "STM32 Quad SPI controller"
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depends on ARCH_STM32
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help
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This enables support for the STM32 Quad SPI controller.
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We only connect the NOR to this controller.
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endif # MTD_SPI_NOR
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@ -8,3 +8,4 @@ obj-$(CONFIG_MTD_MT81xx_NOR) += mtk-quadspi.o
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obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
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obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
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obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM) += intel-spi-platform.o
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obj-$(CONFIG_SPI_STM32_QUADSPI) += stm32-quadspi.o
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693
drivers/mtd/spi-nor/stm32-quadspi.c
Normal file
693
drivers/mtd/spi-nor/stm32-quadspi.c
Normal file
@ -0,0 +1,693 @@
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/*
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* stm32_quadspi.c
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*
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* Copyright (C) 2017, Ludovic Barre
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*
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* License terms: GNU General Public License (GPL), version 2
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*/
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#include <linux/clk.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/spi-nor.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#define QUADSPI_CR 0x00
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#define CR_EN BIT(0)
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#define CR_ABORT BIT(1)
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#define CR_DMAEN BIT(2)
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#define CR_TCEN BIT(3)
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#define CR_SSHIFT BIT(4)
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#define CR_DFM BIT(6)
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#define CR_FSEL BIT(7)
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#define CR_FTHRES_SHIFT 8
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#define CR_FTHRES_MASK GENMASK(12, 8)
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#define CR_FTHRES(n) (((n) << CR_FTHRES_SHIFT) & CR_FTHRES_MASK)
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#define CR_TEIE BIT(16)
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#define CR_TCIE BIT(17)
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#define CR_FTIE BIT(18)
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#define CR_SMIE BIT(19)
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#define CR_TOIE BIT(20)
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#define CR_PRESC_SHIFT 24
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#define CR_PRESC_MASK GENMASK(31, 24)
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#define CR_PRESC(n) (((n) << CR_PRESC_SHIFT) & CR_PRESC_MASK)
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#define QUADSPI_DCR 0x04
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#define DCR_CSHT_SHIFT 8
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#define DCR_CSHT_MASK GENMASK(10, 8)
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#define DCR_CSHT(n) (((n) << DCR_CSHT_SHIFT) & DCR_CSHT_MASK)
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#define DCR_FSIZE_SHIFT 16
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#define DCR_FSIZE_MASK GENMASK(20, 16)
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#define DCR_FSIZE(n) (((n) << DCR_FSIZE_SHIFT) & DCR_FSIZE_MASK)
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#define QUADSPI_SR 0x08
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#define SR_TEF BIT(0)
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#define SR_TCF BIT(1)
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#define SR_FTF BIT(2)
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#define SR_SMF BIT(3)
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#define SR_TOF BIT(4)
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#define SR_BUSY BIT(5)
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#define SR_FLEVEL_SHIFT 8
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#define SR_FLEVEL_MASK GENMASK(13, 8)
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#define QUADSPI_FCR 0x0c
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#define FCR_CTCF BIT(1)
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#define QUADSPI_DLR 0x10
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#define QUADSPI_CCR 0x14
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#define CCR_INST_SHIFT 0
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#define CCR_INST_MASK GENMASK(7, 0)
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#define CCR_INST(n) (((n) << CCR_INST_SHIFT) & CCR_INST_MASK)
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#define CCR_IMODE_NONE (0U << 8)
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#define CCR_IMODE_1 (1U << 8)
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#define CCR_IMODE_2 (2U << 8)
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#define CCR_IMODE_4 (3U << 8)
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#define CCR_ADMODE_NONE (0U << 10)
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#define CCR_ADMODE_1 (1U << 10)
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#define CCR_ADMODE_2 (2U << 10)
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#define CCR_ADMODE_4 (3U << 10)
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#define CCR_ADSIZE_SHIFT 12
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#define CCR_ADSIZE_MASK GENMASK(13, 12)
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#define CCR_ADSIZE(n) (((n) << CCR_ADSIZE_SHIFT) & CCR_ADSIZE_MASK)
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#define CCR_ABMODE_NONE (0U << 14)
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#define CCR_ABMODE_1 (1U << 14)
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#define CCR_ABMODE_2 (2U << 14)
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#define CCR_ABMODE_4 (3U << 14)
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#define CCR_ABSIZE_8 (0U << 16)
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#define CCR_ABSIZE_16 (1U << 16)
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#define CCR_ABSIZE_24 (2U << 16)
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#define CCR_ABSIZE_32 (3U << 16)
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#define CCR_DCYC_SHIFT 18
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#define CCR_DCYC_MASK GENMASK(22, 18)
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#define CCR_DCYC(n) (((n) << CCR_DCYC_SHIFT) & CCR_DCYC_MASK)
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#define CCR_DMODE_NONE (0U << 24)
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#define CCR_DMODE_1 (1U << 24)
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#define CCR_DMODE_2 (2U << 24)
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#define CCR_DMODE_4 (3U << 24)
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#define CCR_FMODE_INDW (0U << 26)
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#define CCR_FMODE_INDR (1U << 26)
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#define CCR_FMODE_APM (2U << 26)
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#define CCR_FMODE_MM (3U << 26)
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#define QUADSPI_AR 0x18
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#define QUADSPI_ABR 0x1c
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#define QUADSPI_DR 0x20
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#define QUADSPI_PSMKR 0x24
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#define QUADSPI_PSMAR 0x28
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#define QUADSPI_PIR 0x2c
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#define QUADSPI_LPTR 0x30
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#define LPTR_DFT_TIMEOUT 0x10
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#define FSIZE_VAL(size) (__fls(size) - 1)
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#define STM32_MAX_MMAP_SZ SZ_256M
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#define STM32_MAX_NORCHIP 2
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#define STM32_QSPI_FIFO_TIMEOUT_US 30000
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#define STM32_QSPI_BUSY_TIMEOUT_US 100000
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struct stm32_qspi_flash {
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struct spi_nor nor;
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struct stm32_qspi *qspi;
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u32 cs;
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u32 fsize;
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u32 presc;
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u32 read_mode;
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bool registered;
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};
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struct stm32_qspi {
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struct device *dev;
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void __iomem *io_base;
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void __iomem *mm_base;
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resource_size_t mm_size;
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u32 nor_num;
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struct clk *clk;
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u32 clk_rate;
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struct stm32_qspi_flash flash[STM32_MAX_NORCHIP];
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struct completion cmd_completion;
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/*
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* to protect device configuration, could be different between
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* 2 flash access (bk1, bk2)
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*/
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struct mutex lock;
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};
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struct stm32_qspi_cmd {
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u8 addr_width;
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u8 dummy;
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bool tx_data;
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u8 opcode;
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u32 framemode;
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u32 qspimode;
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u32 addr;
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size_t len;
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void *buf;
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};
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static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi)
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{
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u32 cr;
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int err = 0;
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if (readl_relaxed(qspi->io_base + QUADSPI_SR) & SR_TCF)
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return 0;
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reinit_completion(&qspi->cmd_completion);
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cr = readl_relaxed(qspi->io_base + QUADSPI_CR);
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writel_relaxed(cr | CR_TCIE, qspi->io_base + QUADSPI_CR);
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if (!wait_for_completion_interruptible_timeout(&qspi->cmd_completion,
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msecs_to_jiffies(1000)))
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err = -ETIMEDOUT;
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writel_relaxed(cr, qspi->io_base + QUADSPI_CR);
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return err;
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}
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static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
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{
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u32 sr;
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return readl_relaxed_poll_timeout(qspi->io_base + QUADSPI_SR, sr,
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!(sr & SR_BUSY), 10,
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STM32_QSPI_BUSY_TIMEOUT_US);
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}
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static void stm32_qspi_set_framemode(struct spi_nor *nor,
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struct stm32_qspi_cmd *cmd, bool read)
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{
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u32 dmode = CCR_DMODE_1;
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cmd->framemode = CCR_IMODE_1;
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if (read) {
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switch (nor->flash_read) {
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case SPI_NOR_NORMAL:
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case SPI_NOR_FAST:
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dmode = CCR_DMODE_1;
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break;
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case SPI_NOR_DUAL:
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dmode = CCR_DMODE_2;
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break;
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case SPI_NOR_QUAD:
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dmode = CCR_DMODE_4;
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break;
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}
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}
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cmd->framemode |= cmd->tx_data ? dmode : 0;
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cmd->framemode |= cmd->addr_width ? CCR_ADMODE_1 : 0;
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}
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static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
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{
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*val = readb_relaxed(addr);
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}
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static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
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{
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writeb_relaxed(*val, addr);
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}
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static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
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const struct stm32_qspi_cmd *cmd)
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{
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void (*tx_fifo)(u8 *, void __iomem *);
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u32 len = cmd->len, sr;
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u8 *buf = cmd->buf;
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int ret;
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if (cmd->qspimode == CCR_FMODE_INDW)
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tx_fifo = stm32_qspi_write_fifo;
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else
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tx_fifo = stm32_qspi_read_fifo;
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while (len--) {
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ret = readl_relaxed_poll_timeout(qspi->io_base + QUADSPI_SR,
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sr, (sr & SR_FTF), 10,
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STM32_QSPI_FIFO_TIMEOUT_US);
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if (ret) {
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dev_err(qspi->dev, "fifo timeout (stat:%#x)\n", sr);
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break;
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}
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tx_fifo(buf++, qspi->io_base + QUADSPI_DR);
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}
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return ret;
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}
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static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
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const struct stm32_qspi_cmd *cmd)
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{
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memcpy_fromio(cmd->buf, qspi->mm_base + cmd->addr, cmd->len);
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return 0;
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}
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static int stm32_qspi_tx(struct stm32_qspi *qspi,
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const struct stm32_qspi_cmd *cmd)
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{
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if (!cmd->tx_data)
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return 0;
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if (cmd->qspimode == CCR_FMODE_MM)
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return stm32_qspi_tx_mm(qspi, cmd);
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return stm32_qspi_tx_poll(qspi, cmd);
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}
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static int stm32_qspi_send(struct stm32_qspi_flash *flash,
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const struct stm32_qspi_cmd *cmd)
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{
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struct stm32_qspi *qspi = flash->qspi;
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u32 ccr, dcr, cr;
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int err;
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err = stm32_qspi_wait_nobusy(qspi);
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if (err)
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goto abort;
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dcr = readl_relaxed(qspi->io_base + QUADSPI_DCR) & ~DCR_FSIZE_MASK;
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dcr |= DCR_FSIZE(flash->fsize);
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writel_relaxed(dcr, qspi->io_base + QUADSPI_DCR);
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cr = readl_relaxed(qspi->io_base + QUADSPI_CR);
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cr &= ~CR_PRESC_MASK & ~CR_FSEL;
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cr |= CR_PRESC(flash->presc);
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cr |= flash->cs ? CR_FSEL : 0;
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writel_relaxed(cr, qspi->io_base + QUADSPI_CR);
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if (cmd->tx_data)
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writel_relaxed(cmd->len - 1, qspi->io_base + QUADSPI_DLR);
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ccr = cmd->framemode | cmd->qspimode;
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if (cmd->dummy)
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ccr |= CCR_DCYC(cmd->dummy);
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if (cmd->addr_width)
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ccr |= CCR_ADSIZE(cmd->addr_width - 1);
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ccr |= CCR_INST(cmd->opcode);
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writel_relaxed(ccr, qspi->io_base + QUADSPI_CCR);
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if (cmd->addr_width && cmd->qspimode != CCR_FMODE_MM)
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writel_relaxed(cmd->addr, qspi->io_base + QUADSPI_AR);
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err = stm32_qspi_tx(qspi, cmd);
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if (err)
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goto abort;
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if (cmd->qspimode != CCR_FMODE_MM) {
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err = stm32_qspi_wait_cmd(qspi);
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if (err)
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goto abort;
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writel_relaxed(FCR_CTCF, qspi->io_base + QUADSPI_FCR);
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}
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return err;
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abort:
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cr = readl_relaxed(qspi->io_base + QUADSPI_CR) | CR_ABORT;
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writel_relaxed(cr, qspi->io_base + QUADSPI_CR);
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dev_err(qspi->dev, "%s abort err:%d\n", __func__, err);
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return err;
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}
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static int stm32_qspi_read_reg(struct spi_nor *nor,
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u8 opcode, u8 *buf, int len)
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{
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struct stm32_qspi_flash *flash = nor->priv;
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struct device *dev = flash->qspi->dev;
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struct stm32_qspi_cmd cmd;
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dev_dbg(dev, "read_reg: cmd:%#.2x buf:%p len:%#x\n", opcode, buf, len);
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memset(&cmd, 0, sizeof(cmd));
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cmd.opcode = opcode;
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cmd.tx_data = true;
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cmd.len = len;
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cmd.buf = buf;
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cmd.qspimode = CCR_FMODE_INDR;
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stm32_qspi_set_framemode(nor, &cmd, false);
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return stm32_qspi_send(flash, &cmd);
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}
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static int stm32_qspi_write_reg(struct spi_nor *nor, u8 opcode,
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u8 *buf, int len)
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{
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struct stm32_qspi_flash *flash = nor->priv;
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struct device *dev = flash->qspi->dev;
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struct stm32_qspi_cmd cmd;
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dev_dbg(dev, "write_reg: cmd:%#.2x buf:%p len:%#x\n", opcode, buf, len);
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memset(&cmd, 0, sizeof(cmd));
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cmd.opcode = opcode;
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cmd.tx_data = !!(buf && len > 0);
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cmd.len = len;
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cmd.buf = buf;
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cmd.qspimode = CCR_FMODE_INDW;
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stm32_qspi_set_framemode(nor, &cmd, false);
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return stm32_qspi_send(flash, &cmd);
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}
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static ssize_t stm32_qspi_read(struct spi_nor *nor, loff_t from, size_t len,
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u_char *buf)
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{
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struct stm32_qspi_flash *flash = nor->priv;
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struct stm32_qspi *qspi = flash->qspi;
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struct stm32_qspi_cmd cmd;
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int err;
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dev_dbg(qspi->dev, "read(%#.2x): buf:%p from:%#.8x len:%#x\n",
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nor->read_opcode, buf, (u32)from, len);
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memset(&cmd, 0, sizeof(cmd));
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cmd.opcode = nor->read_opcode;
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cmd.addr_width = nor->addr_width;
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cmd.addr = (u32)from;
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cmd.tx_data = true;
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cmd.dummy = nor->read_dummy;
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cmd.len = len;
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cmd.buf = buf;
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cmd.qspimode = flash->read_mode;
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stm32_qspi_set_framemode(nor, &cmd, true);
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err = stm32_qspi_send(flash, &cmd);
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return err ? err : len;
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}
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static ssize_t stm32_qspi_write(struct spi_nor *nor, loff_t to, size_t len,
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const u_char *buf)
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{
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struct stm32_qspi_flash *flash = nor->priv;
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struct device *dev = flash->qspi->dev;
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struct stm32_qspi_cmd cmd;
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int err;
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dev_dbg(dev, "write(%#.2x): buf:%p to:%#.8x len:%#x\n",
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nor->program_opcode, buf, (u32)to, len);
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memset(&cmd, 0, sizeof(cmd));
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cmd.opcode = nor->program_opcode;
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cmd.addr_width = nor->addr_width;
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cmd.addr = (u32)to;
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cmd.tx_data = true;
|
||||
cmd.len = len;
|
||||
cmd.buf = (void *)buf;
|
||||
cmd.qspimode = CCR_FMODE_INDW;
|
||||
|
||||
stm32_qspi_set_framemode(nor, &cmd, false);
|
||||
err = stm32_qspi_send(flash, &cmd);
|
||||
|
||||
return err ? err : len;
|
||||
}
|
||||
|
||||
static int stm32_qspi_erase(struct spi_nor *nor, loff_t offs)
|
||||
{
|
||||
struct stm32_qspi_flash *flash = nor->priv;
|
||||
struct device *dev = flash->qspi->dev;
|
||||
struct stm32_qspi_cmd cmd;
|
||||
|
||||
dev_dbg(dev, "erase(%#.2x):offs:%#x\n", nor->erase_opcode, (u32)offs);
|
||||
|
||||
memset(&cmd, 0, sizeof(cmd));
|
||||
cmd.opcode = nor->erase_opcode;
|
||||
cmd.addr_width = nor->addr_width;
|
||||
cmd.addr = (u32)offs;
|
||||
cmd.qspimode = CCR_FMODE_INDW;
|
||||
|
||||
stm32_qspi_set_framemode(nor, &cmd, false);
|
||||
|
||||
return stm32_qspi_send(flash, &cmd);
|
||||
}
|
||||
|
||||
static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
|
||||
{
|
||||
struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
|
||||
u32 cr, sr, fcr = 0;
|
||||
|
||||
cr = readl_relaxed(qspi->io_base + QUADSPI_CR);
|
||||
sr = readl_relaxed(qspi->io_base + QUADSPI_SR);
|
||||
|
||||
if ((cr & CR_TCIE) && (sr & SR_TCF)) {
|
||||
/* tx complete */
|
||||
fcr |= FCR_CTCF;
|
||||
complete(&qspi->cmd_completion);
|
||||
} else {
|
||||
dev_info_ratelimited(qspi->dev, "spurious interrupt\n");
|
||||
}
|
||||
|
||||
writel_relaxed(fcr, qspi->io_base + QUADSPI_FCR);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int stm32_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
|
||||
{
|
||||
struct stm32_qspi_flash *flash = nor->priv;
|
||||
struct stm32_qspi *qspi = flash->qspi;
|
||||
|
||||
mutex_lock(&qspi->lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void stm32_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
|
||||
{
|
||||
struct stm32_qspi_flash *flash = nor->priv;
|
||||
struct stm32_qspi *qspi = flash->qspi;
|
||||
|
||||
mutex_unlock(&qspi->lock);
|
||||
}
|
||||
|
||||
static int stm32_qspi_flash_setup(struct stm32_qspi *qspi,
|
||||
struct device_node *np)
|
||||
{
|
||||
u32 width, flash_read, presc, cs_num, max_rate = 0;
|
||||
struct stm32_qspi_flash *flash;
|
||||
struct mtd_info *mtd;
|
||||
int ret;
|
||||
|
||||
of_property_read_u32(np, "reg", &cs_num);
|
||||
if (cs_num >= STM32_MAX_NORCHIP)
|
||||
return -EINVAL;
|
||||
|
||||
of_property_read_u32(np, "spi-max-frequency", &max_rate);
|
||||
if (!max_rate)
|
||||
return -EINVAL;
|
||||
|
||||
presc = DIV_ROUND_UP(qspi->clk_rate, max_rate) - 1;
|
||||
|
||||
if (of_property_read_u32(np, "spi-rx-bus-width", &width))
|
||||
width = 1;
|
||||
|
||||
if (width == 4)
|
||||
flash_read = SPI_NOR_QUAD;
|
||||
else if (width == 2)
|
||||
flash_read = SPI_NOR_DUAL;
|
||||
else if (width == 1)
|
||||
flash_read = SPI_NOR_NORMAL;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
flash = &qspi->flash[cs_num];
|
||||
flash->qspi = qspi;
|
||||
flash->cs = cs_num;
|
||||
flash->presc = presc;
|
||||
|
||||
flash->nor.dev = qspi->dev;
|
||||
spi_nor_set_flash_node(&flash->nor, np);
|
||||
flash->nor.priv = flash;
|
||||
mtd = &flash->nor.mtd;
|
||||
|
||||
flash->nor.read = stm32_qspi_read;
|
||||
flash->nor.write = stm32_qspi_write;
|
||||
flash->nor.erase = stm32_qspi_erase;
|
||||
flash->nor.read_reg = stm32_qspi_read_reg;
|
||||
flash->nor.write_reg = stm32_qspi_write_reg;
|
||||
flash->nor.prepare = stm32_qspi_prep;
|
||||
flash->nor.unprepare = stm32_qspi_unprep;
|
||||
|
||||
writel_relaxed(LPTR_DFT_TIMEOUT, qspi->io_base + QUADSPI_LPTR);
|
||||
|
||||
writel_relaxed(CR_PRESC(presc) | CR_FTHRES(3) | CR_TCEN | CR_SSHIFT
|
||||
| CR_EN, qspi->io_base + QUADSPI_CR);
|
||||
|
||||
/*
|
||||
* in stm32 qspi controller, QUADSPI_DCR register has a fsize field
|
||||
* which define the size of nor flash.
|
||||
* if fsize is NULL, the controller can't sent spi-nor command.
|
||||
* set a temporary value just to discover the nor flash with
|
||||
* "spi_nor_scan". After, the right value (mtd->size) can be set.
|
||||
*/
|
||||
flash->fsize = FSIZE_VAL(SZ_1K);
|
||||
|
||||
ret = spi_nor_scan(&flash->nor, NULL, flash_read);
|
||||
if (ret) {
|
||||
dev_err(qspi->dev, "device scan failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
flash->fsize = FSIZE_VAL(mtd->size);
|
||||
|
||||
flash->read_mode = CCR_FMODE_MM;
|
||||
if (mtd->size > qspi->mm_size)
|
||||
flash->read_mode = CCR_FMODE_INDR;
|
||||
|
||||
writel_relaxed(DCR_CSHT(1), qspi->io_base + QUADSPI_DCR);
|
||||
|
||||
ret = mtd_device_register(mtd, NULL, 0);
|
||||
if (ret) {
|
||||
dev_err(qspi->dev, "mtd device parse failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
flash->registered = true;
|
||||
|
||||
dev_dbg(qspi->dev, "read mm:%s cs:%d bus:%d\n",
|
||||
flash->read_mode == CCR_FMODE_MM ? "yes" : "no", cs_num, width);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void stm32_qspi_mtd_free(struct stm32_qspi *qspi)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < STM32_MAX_NORCHIP; i++)
|
||||
if (qspi->flash[i].registered)
|
||||
mtd_device_unregister(&qspi->flash[i].nor.mtd);
|
||||
}
|
||||
|
||||
static int stm32_qspi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *flash_np;
|
||||
struct reset_control *rstc;
|
||||
struct stm32_qspi *qspi;
|
||||
struct resource *res;
|
||||
int ret, irq;
|
||||
|
||||
qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL);
|
||||
if (!qspi)
|
||||
return -ENOMEM;
|
||||
|
||||
qspi->nor_num = of_get_child_count(dev->of_node);
|
||||
if (!qspi->nor_num || qspi->nor_num > STM32_MAX_NORCHIP)
|
||||
return -ENODEV;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
|
||||
qspi->io_base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(qspi->io_base))
|
||||
return PTR_ERR(qspi->io_base);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
|
||||
qspi->mm_base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(qspi->mm_base))
|
||||
return PTR_ERR(qspi->mm_base);
|
||||
|
||||
qspi->mm_size = resource_size(res);
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
|
||||
dev_name(dev), qspi);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to request irq\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
init_completion(&qspi->cmd_completion);
|
||||
|
||||
qspi->clk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(qspi->clk))
|
||||
return PTR_ERR(qspi->clk);
|
||||
|
||||
qspi->clk_rate = clk_get_rate(qspi->clk);
|
||||
if (!qspi->clk_rate)
|
||||
return -EINVAL;
|
||||
|
||||
ret = clk_prepare_enable(qspi->clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "can not enable the clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
rstc = devm_reset_control_get(dev, NULL);
|
||||
if (!IS_ERR(rstc)) {
|
||||
reset_control_assert(rstc);
|
||||
udelay(2);
|
||||
reset_control_deassert(rstc);
|
||||
}
|
||||
|
||||
qspi->dev = dev;
|
||||
platform_set_drvdata(pdev, qspi);
|
||||
mutex_init(&qspi->lock);
|
||||
|
||||
for_each_available_child_of_node(dev->of_node, flash_np) {
|
||||
ret = stm32_qspi_flash_setup(qspi, flash_np);
|
||||
if (ret) {
|
||||
dev_err(dev, "unable to setup flash chip\n");
|
||||
goto err_flash;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_flash:
|
||||
mutex_destroy(&qspi->lock);
|
||||
stm32_qspi_mtd_free(qspi);
|
||||
|
||||
clk_disable_unprepare(qspi->clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32_qspi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct stm32_qspi *qspi = platform_get_drvdata(pdev);
|
||||
|
||||
/* disable qspi */
|
||||
writel_relaxed(0, qspi->io_base + QUADSPI_CR);
|
||||
|
||||
stm32_qspi_mtd_free(qspi);
|
||||
mutex_destroy(&qspi->lock);
|
||||
|
||||
clk_disable_unprepare(qspi->clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id stm32_qspi_match[] = {
|
||||
{.compatible = "st,stm32f469-qspi"},
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, stm32_qspi_match);
|
||||
|
||||
static struct platform_driver stm32_qspi_driver = {
|
||||
.probe = stm32_qspi_probe,
|
||||
.remove = stm32_qspi_remove,
|
||||
.driver = {
|
||||
.name = "stm32-quadspi",
|
||||
.of_match_table = stm32_qspi_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(stm32_qspi_driver);
|
||||
|
||||
MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
|
||||
MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue
Block a user