2014-07-07 22:54:13 +00:00
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/*
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2011-02-14 07:33:10 +00:00
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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2010-07-26 12:08:52 +00:00
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*
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* Cloned from linux/arch/arm/mach-vexpress/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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2014-05-12 22:13:44 +00:00
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#include <linux/of_address.h>
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2010-07-26 12:08:52 +00:00
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#include <asm/cacheflush.h>
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2014-09-13 17:49:31 +00:00
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#include <asm/cp15.h>
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2012-01-20 11:01:12 +00:00
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#include <asm/smp_plat.h>
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2010-07-26 12:08:52 +00:00
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#include <asm/smp_scu.h>
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2012-12-11 04:58:43 +00:00
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#include <asm/firmware.h>
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2010-07-26 12:08:52 +00:00
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2014-07-18 18:43:22 +00:00
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#include <mach/map.h>
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2011-09-08 12:15:22 +00:00
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#include "common.h"
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2013-12-18 19:06:56 +00:00
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#include "regs-pmu.h"
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2011-09-08 12:15:22 +00:00
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2011-02-14 07:33:10 +00:00
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extern void exynos4_secondary_startup(void);
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2010-07-26 12:08:52 +00:00
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2014-09-13 17:49:31 +00:00
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#ifdef CONFIG_HOTPLUG_CPU
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2014-09-13 17:49:32 +00:00
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static inline void cpu_leave_lowpower(u32 core_id)
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2014-09-13 17:49:31 +00:00
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{
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unsigned int v;
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asm volatile(
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"mrc p15, 0, %0, c1, c0, 0\n"
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" orr %0, %0, %1\n"
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" mcr p15, 0, %0, c1, c0, 0\n"
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" mrc p15, 0, %0, c1, c0, 1\n"
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" orr %0, %0, %2\n"
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" mcr p15, 0, %0, c1, c0, 1\n"
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: "=&r" (v)
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: "Ir" (CR_C), "Ir" (0x40)
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: "cc");
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}
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static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
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{
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u32 mpidr = cpu_logical_map(cpu);
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u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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for (;;) {
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/* Turn the CPU off on next WFI instruction. */
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exynos_cpu_power_down(core_id);
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wfi();
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if (pen_release == core_id) {
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/*
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* OK, proper wakeup, we're done
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*/
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break;
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}
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/*
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* Getting here, means that we have come out of WFI without
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* having been woken up - this shouldn't happen
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*
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* Just note it happening - when we're woken, we can report
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* its occurrence.
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*/
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(*spurious)++;
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}
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}
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#endif /* CONFIG_HOTPLUG_CPU */
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2014-07-18 19:45:02 +00:00
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/**
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* exynos_core_power_down : power down the specified cpu
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* @cpu : the cpu to power down
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*
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* Power down the specified cpu. The sequence must be finished by a
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* call to cpu_do_idle()
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*
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*/
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void exynos_cpu_power_down(int cpu)
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{
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2015-03-26 17:32:56 +00:00
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u32 core_conf;
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2015-02-26 20:50:41 +00:00
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if (cpu == 0 && (soc_is_exynos5420() || soc_is_exynos5800())) {
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2014-11-07 00:20:16 +00:00
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/*
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* Bypass power down for CPU0 during suspend. Check for
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* the SYS_PWR_REG value to decide if we are suspending
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* the system.
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*/
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int val = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
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if (!(val & S5P_CORE_LOCAL_PWR_EN))
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return;
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}
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2015-03-26 17:32:56 +00:00
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core_conf = pmu_raw_readl(EXYNOS_ARM_CORE_CONFIGURATION(cpu));
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core_conf &= ~S5P_CORE_LOCAL_PWR_EN;
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pmu_raw_writel(core_conf, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
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2014-07-18 19:45:02 +00:00
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}
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/**
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* exynos_cpu_power_up : power up the specified cpu
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* @cpu : the cpu to power up
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*
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* Power up the specified cpu
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*/
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void exynos_cpu_power_up(int cpu)
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{
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2015-03-26 17:32:56 +00:00
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u32 core_conf = S5P_CORE_LOCAL_PWR_EN;
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if (soc_is_exynos3250())
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core_conf |= S5P_CORE_AUTOWAKEUP_EN;
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pmu_raw_writel(core_conf,
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2014-07-26 15:54:21 +00:00
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EXYNOS_ARM_CORE_CONFIGURATION(cpu));
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2014-07-18 19:45:02 +00:00
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}
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/**
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* exynos_cpu_power_state : returns the power state of the cpu
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* @cpu : the cpu to retrieve the power state from
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*
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*/
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int exynos_cpu_power_state(int cpu)
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{
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2014-07-26 15:54:21 +00:00
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return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
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2014-07-18 19:45:02 +00:00
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S5P_CORE_LOCAL_PWR_EN);
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}
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/**
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* exynos_cluster_power_down : power down the specified cluster
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* @cluster : the cluster to power down
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*/
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void exynos_cluster_power_down(int cluster)
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{
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2014-07-26 15:54:21 +00:00
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pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
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2014-07-18 19:45:02 +00:00
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}
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/**
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* exynos_cluster_power_up : power up the specified cluster
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* @cluster : the cluster to power up
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*/
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void exynos_cluster_power_up(int cluster)
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{
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2014-07-26 15:54:21 +00:00
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pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
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EXYNOS_COMMON_CONFIGURATION(cluster));
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2014-07-18 19:45:02 +00:00
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}
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/**
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* exynos_cluster_power_state : returns the power state of the cluster
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* @cluster : the cluster to retrieve the power state from
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*
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*/
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int exynos_cluster_power_state(int cluster)
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{
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2014-07-26 15:54:21 +00:00
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return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
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S5P_CORE_LOCAL_PWR_EN);
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2014-07-18 19:45:02 +00:00
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}
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2015-03-18 13:09:57 +00:00
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static void __iomem *cpu_boot_reg_base(void)
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2012-11-24 02:13:48 +00:00
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{
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if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
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2014-07-18 18:43:22 +00:00
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return pmu_base_addr + S5P_INFORM5;
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2014-05-12 22:13:44 +00:00
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return sysram_base_addr;
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2012-11-24 02:13:48 +00:00
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}
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static inline void __iomem *cpu_boot_reg(int cpu)
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{
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void __iomem *boot_reg;
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boot_reg = cpu_boot_reg_base();
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2014-05-12 22:13:44 +00:00
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if (!boot_reg)
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return ERR_PTR(-ENODEV);
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2012-11-24 02:13:48 +00:00
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if (soc_is_exynos4412())
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boot_reg += 4*cpu;
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2014-05-25 19:16:11 +00:00
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else if (soc_is_exynos5420() || soc_is_exynos5800())
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2013-06-18 15:29:35 +00:00
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boot_reg += 4;
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2012-11-24 02:13:48 +00:00
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return boot_reg;
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}
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2011-07-16 04:39:09 +00:00
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2014-09-25 09:15:13 +00:00
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/*
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* Set wake up by local power mode and execute software reset for given core.
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*
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* Currently this is needed only when booting secondary CPU on Exynos3250.
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*/
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2015-03-18 13:09:57 +00:00
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void exynos_core_restart(u32 core_id)
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2014-09-25 09:15:13 +00:00
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{
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u32 val;
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if (!of_machine_is_compatible("samsung,exynos3250"))
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return;
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2015-03-26 17:32:56 +00:00
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while (!pmu_raw_readl(S5P_PMU_SPARE2))
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udelay(10);
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udelay(10);
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2014-09-25 09:15:13 +00:00
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val = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(core_id));
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val |= S5P_CORE_WAKEUP_FROM_LOCAL_CFG;
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pmu_raw_writel(val, EXYNOS_ARM_CORE_STATUS(core_id));
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pmu_raw_writel(EXYNOS_CORE_PO_RESET(core_id), EXYNOS_SWRESET);
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}
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ARM: Fix subtle race in CPU pen_release hotplug code
There is a subtle race in the CPU hotplug code, where a CPU which has
been offlined can online itself before being requested, which results
in things going astray on the next online/offline cycle.
What happens in the normal online/offline/online cycle is:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads -1
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
However, as the write of -1 of pen_release is not fully flushed back to
memory, and the checking of pen_release is done with caches disabled,
this allows CPU3 the opportunity to read the old value of pen_release:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads 3
starts boot
pen_release = -1
requests boot of CPU3
pen_release = 3
flush cache line
Fix this by grouping the write of pen_release along with its cache line
flushing code to ensure that any update to pen_release is always pushed
out to physical memory.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-18 10:53:12 +00:00
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/*
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* Write pen_release in a way that is guaranteed to be visible to all
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* observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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static void write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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2013-12-05 19:26:16 +00:00
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sync_cache_w(&pen_release);
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ARM: Fix subtle race in CPU pen_release hotplug code
There is a subtle race in the CPU hotplug code, where a CPU which has
been offlined can online itself before being requested, which results
in things going astray on the next online/offline cycle.
What happens in the normal online/offline/online cycle is:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads -1
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
However, as the write of -1 of pen_release is not fully flushed back to
memory, and the checking of pen_release is done with caches disabled,
this allows CPU3 the opportunity to read the old value of pen_release:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads 3
starts boot
pen_release = -1
requests boot of CPU3
pen_release = 3
flush cache line
Fix this by grouping the write of pen_release along with its cache line
flushing code to ensure that any update to pen_release is always pushed
out to physical memory.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-18 10:53:12 +00:00
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}
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2010-07-26 12:08:52 +00:00
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static void __iomem *scu_base_addr(void)
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{
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return (void __iomem *)(S5P_VA_SCU);
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}
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static DEFINE_SPINLOCK(boot_lock);
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2013-06-17 19:43:14 +00:00
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static void exynos_secondary_init(unsigned int cpu)
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2010-07-26 12:08:52 +00:00
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{
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
|
ARM: Fix subtle race in CPU pen_release hotplug code
There is a subtle race in the CPU hotplug code, where a CPU which has
been offlined can online itself before being requested, which results
in things going astray on the next online/offline cycle.
What happens in the normal online/offline/online cycle is:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads -1
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
However, as the write of -1 of pen_release is not fully flushed back to
memory, and the checking of pen_release is done with caches disabled,
this allows CPU3 the opportunity to read the old value of pen_release:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads 3
starts boot
pen_release = -1
requests boot of CPU3
pen_release = 3
flush cache line
Fix this by grouping the write of pen_release along with its cache line
flushing code to ensure that any update to pen_release is always pushed
out to physical memory.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-18 10:53:12 +00:00
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write_pen_release(-1);
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2010-07-26 12:08:52 +00:00
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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|
2015-03-18 13:09:57 +00:00
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int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
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2015-03-18 13:09:55 +00:00
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{
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int ret;
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/*
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* Try to set boot address using firmware first
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* and fall back to boot register if it fails.
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*/
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ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
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if (ret && ret != -ENOSYS)
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goto fail;
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if (ret == -ENOSYS) {
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void __iomem *boot_reg = cpu_boot_reg(core_id);
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if (IS_ERR(boot_reg)) {
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ret = PTR_ERR(boot_reg);
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goto fail;
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}
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__raw_writel(boot_addr, boot_reg);
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ret = 0;
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}
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fail:
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return ret;
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}
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2015-03-18 13:09:57 +00:00
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int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr)
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2015-03-18 13:09:56 +00:00
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|
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{
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int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Try to get boot address using firmware first
|
|
|
|
* and fall back to boot register if it fails.
|
|
|
|
*/
|
|
|
|
ret = call_firmware_op(get_cpu_boot_addr, core_id, boot_addr);
|
|
|
|
if (ret && ret != -ENOSYS)
|
|
|
|
goto fail;
|
|
|
|
if (ret == -ENOSYS) {
|
|
|
|
void __iomem *boot_reg = cpu_boot_reg(core_id);
|
|
|
|
|
|
|
|
if (IS_ERR(boot_reg)) {
|
|
|
|
ret = PTR_ERR(boot_reg);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
*boot_addr = __raw_readl(boot_reg);
|
|
|
|
ret = 0;
|
|
|
|
}
|
|
|
|
fail:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-06-17 19:43:14 +00:00
|
|
|
static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
2010-07-26 12:08:52 +00:00
|
|
|
{
|
|
|
|
unsigned long timeout;
|
2014-07-15 17:59:18 +00:00
|
|
|
u32 mpidr = cpu_logical_map(cpu);
|
|
|
|
u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
|
2014-05-12 22:13:44 +00:00
|
|
|
int ret = -ENOSYS;
|
2010-07-26 12:08:52 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Set synchronisation state between this boot processor
|
|
|
|
* and the secondary one
|
|
|
|
*/
|
|
|
|
spin_lock(&boot_lock);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The secondary processor is waiting to be released from
|
|
|
|
* the holding pen - release it, then wait for it to flag
|
|
|
|
* that it has been released by resetting pen_release.
|
|
|
|
*
|
2014-07-15 17:59:18 +00:00
|
|
|
* Note that "pen_release" is the hardware CPU core ID, whereas
|
2010-07-26 12:08:52 +00:00
|
|
|
* "cpu" is Linux's internal ID.
|
|
|
|
*/
|
2014-07-15 17:59:18 +00:00
|
|
|
write_pen_release(core_id);
|
2010-07-26 12:08:52 +00:00
|
|
|
|
2014-07-15 17:59:18 +00:00
|
|
|
if (!exynos_cpu_power_state(core_id)) {
|
|
|
|
exynos_cpu_power_up(core_id);
|
2011-07-16 04:39:09 +00:00
|
|
|
timeout = 10;
|
|
|
|
|
|
|
|
/* wait max 10 ms until cpu1 is on */
|
2014-07-15 17:59:18 +00:00
|
|
|
while (exynos_cpu_power_state(core_id)
|
|
|
|
!= S5P_CORE_LOCAL_PWR_EN) {
|
2011-07-16 04:39:09 +00:00
|
|
|
if (timeout-- == 0)
|
|
|
|
break;
|
|
|
|
|
|
|
|
mdelay(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (timeout == 0) {
|
|
|
|
printk(KERN_ERR "cpu1 power enable failed");
|
|
|
|
spin_unlock(&boot_lock);
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
}
|
2014-09-25 09:15:13 +00:00
|
|
|
|
|
|
|
exynos_core_restart(core_id);
|
|
|
|
|
2010-07-26 12:08:52 +00:00
|
|
|
/*
|
|
|
|
* Send the secondary CPU a soft interrupt, thereby causing
|
|
|
|
* the boot monitor to read the system wide flags register,
|
|
|
|
* and branch to the address found there.
|
|
|
|
*/
|
|
|
|
|
|
|
|
timeout = jiffies + (1 * HZ);
|
|
|
|
while (time_before(jiffies, timeout)) {
|
2012-12-11 04:58:43 +00:00
|
|
|
unsigned long boot_addr;
|
|
|
|
|
2010-07-26 12:08:52 +00:00
|
|
|
smp_rmb();
|
2011-07-16 04:39:09 +00:00
|
|
|
|
2012-12-11 04:58:43 +00:00
|
|
|
boot_addr = virt_to_phys(exynos4_secondary_startup);
|
|
|
|
|
2015-03-18 13:09:55 +00:00
|
|
|
ret = exynos_set_boot_addr(core_id, boot_addr);
|
|
|
|
if (ret)
|
2014-05-12 22:13:44 +00:00
|
|
|
goto fail;
|
2012-12-11 04:58:43 +00:00
|
|
|
|
2014-07-15 17:59:18 +00:00
|
|
|
call_firmware_op(cpu_boot, core_id);
|
2012-12-11 04:58:43 +00:00
|
|
|
|
2015-03-26 17:32:56 +00:00
|
|
|
if (soc_is_exynos3250())
|
|
|
|
dsb_sev();
|
|
|
|
else
|
|
|
|
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
|
2011-07-16 04:39:09 +00:00
|
|
|
|
2010-07-26 12:08:52 +00:00
|
|
|
if (pen_release == -1)
|
|
|
|
break;
|
|
|
|
|
|
|
|
udelay(10);
|
|
|
|
}
|
|
|
|
|
2015-03-18 13:09:53 +00:00
|
|
|
if (pen_release != -1)
|
|
|
|
ret = -ETIMEDOUT;
|
|
|
|
|
2010-07-26 12:08:52 +00:00
|
|
|
/*
|
|
|
|
* now the secondary core is starting up let it run its
|
|
|
|
* calibrations, then wait for it to finish
|
|
|
|
*/
|
2014-05-12 22:13:44 +00:00
|
|
|
fail:
|
2010-07-26 12:08:52 +00:00
|
|
|
spin_unlock(&boot_lock);
|
|
|
|
|
2014-05-12 22:13:44 +00:00
|
|
|
return pen_release != -1 ? ret : 0;
|
2010-07-26 12:08:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialise the CPU possible map early - this describes the CPUs
|
|
|
|
* which may be present or become present in the system.
|
|
|
|
*/
|
|
|
|
|
2011-09-08 12:15:22 +00:00
|
|
|
static void __init exynos_smp_init_cpus(void)
|
2010-07-26 12:08:52 +00:00
|
|
|
{
|
|
|
|
void __iomem *scu_base = scu_base_addr();
|
|
|
|
unsigned int i, ncores;
|
|
|
|
|
2014-06-24 18:43:15 +00:00
|
|
|
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
|
2012-01-25 06:35:57 +00:00
|
|
|
ncores = scu_base ? scu_get_core_count(scu_base) : 1;
|
2013-06-18 15:29:34 +00:00
|
|
|
else
|
|
|
|
/*
|
|
|
|
* CPU Nodes are passed thru DT and set_cpu_possible
|
|
|
|
* is set by "arm_dt_init_cpu_maps".
|
|
|
|
*/
|
|
|
|
return;
|
2010-07-26 12:08:52 +00:00
|
|
|
|
|
|
|
/* sanity check */
|
2011-10-20 21:04:18 +00:00
|
|
|
if (ncores > nr_cpu_ids) {
|
|
|
|
pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
|
|
|
|
ncores, nr_cpu_ids);
|
|
|
|
ncores = nr_cpu_ids;
|
2010-07-26 12:08:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < ncores; i++)
|
|
|
|
set_cpu_possible(i, true);
|
|
|
|
}
|
|
|
|
|
2011-09-08 12:15:22 +00:00
|
|
|
static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
|
2010-07-26 12:08:52 +00:00
|
|
|
{
|
2012-11-24 02:13:48 +00:00
|
|
|
int i;
|
|
|
|
|
2014-06-03 04:47:46 +00:00
|
|
|
exynos_sysram_init();
|
|
|
|
|
2015-03-11 10:13:57 +00:00
|
|
|
exynos_set_delayed_reset_assertion(true);
|
|
|
|
|
2014-06-24 18:43:15 +00:00
|
|
|
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
|
2012-01-25 06:35:57 +00:00
|
|
|
scu_enable(scu_base_addr());
|
2010-12-03 11:09:48 +00:00
|
|
|
|
2010-07-26 12:08:52 +00:00
|
|
|
/*
|
2010-12-03 11:09:48 +00:00
|
|
|
* Write the address of secondary startup into the
|
|
|
|
* system-wide flags register. The boot monitor waits
|
|
|
|
* until it receives a soft interrupt, and then the
|
|
|
|
* secondary CPU branches to this address.
|
2012-12-11 04:58:43 +00:00
|
|
|
*
|
|
|
|
* Try using firmware operation first and fall back to
|
|
|
|
* boot register if it fails.
|
2010-07-26 12:08:52 +00:00
|
|
|
*/
|
2012-12-11 04:58:43 +00:00
|
|
|
for (i = 1; i < max_cpus; ++i) {
|
|
|
|
unsigned long boot_addr;
|
2014-07-15 17:59:18 +00:00
|
|
|
u32 mpidr;
|
|
|
|
u32 core_id;
|
2014-05-12 22:13:44 +00:00
|
|
|
int ret;
|
2012-12-11 04:58:43 +00:00
|
|
|
|
2014-07-15 17:59:18 +00:00
|
|
|
mpidr = cpu_logical_map(i);
|
|
|
|
core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
|
2012-12-11 04:58:43 +00:00
|
|
|
boot_addr = virt_to_phys(exynos4_secondary_startup);
|
|
|
|
|
2015-03-18 13:09:55 +00:00
|
|
|
ret = exynos_set_boot_addr(core_id, boot_addr);
|
|
|
|
if (ret)
|
2014-05-12 22:13:44 +00:00
|
|
|
break;
|
2012-12-11 04:58:43 +00:00
|
|
|
}
|
2010-07-26 12:08:52 +00:00
|
|
|
}
|
2011-09-08 12:15:22 +00:00
|
|
|
|
2014-09-13 17:49:31 +00:00
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
|
|
/*
|
|
|
|
* platform-specific code to shutdown a CPU
|
|
|
|
*
|
|
|
|
* Called with IRQs disabled
|
|
|
|
*/
|
2014-09-13 17:49:32 +00:00
|
|
|
static void exynos_cpu_die(unsigned int cpu)
|
2014-09-13 17:49:31 +00:00
|
|
|
{
|
|
|
|
int spurious = 0;
|
2014-09-13 17:49:32 +00:00
|
|
|
u32 mpidr = cpu_logical_map(cpu);
|
|
|
|
u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
|
2014-09-13 17:49:31 +00:00
|
|
|
|
|
|
|
v7_exit_coherency_flush(louis);
|
|
|
|
|
|
|
|
platform_do_lowpower(cpu, &spurious);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* bring this CPU back into the world of cache
|
|
|
|
* coherency, and then restore interrupts
|
|
|
|
*/
|
2014-09-13 17:49:32 +00:00
|
|
|
cpu_leave_lowpower(core_id);
|
2014-09-13 17:49:31 +00:00
|
|
|
|
|
|
|
if (spurious)
|
|
|
|
pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_HOTPLUG_CPU */
|
|
|
|
|
2011-09-08 12:15:22 +00:00
|
|
|
struct smp_operations exynos_smp_ops __initdata = {
|
|
|
|
.smp_init_cpus = exynos_smp_init_cpus,
|
|
|
|
.smp_prepare_cpus = exynos_smp_prepare_cpus,
|
|
|
|
.smp_secondary_init = exynos_secondary_init,
|
|
|
|
.smp_boot_secondary = exynos_boot_secondary,
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
|
|
.cpu_die = exynos_cpu_die,
|
|
|
|
#endif
|
|
|
|
};
|