2011-02-14 07:33:10 +00:00
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/* linux/arch/arm/mach-exynos4/platsmp.c
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2010-07-26 12:08:52 +00:00
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*
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2011-02-14 07:33:10 +00:00
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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2010-07-26 12:08:52 +00:00
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*
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* Cloned from linux/arch/arm/mach-vexpress/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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2014-05-12 22:13:44 +00:00
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#include <linux/of_address.h>
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2010-07-26 12:08:52 +00:00
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#include <asm/cacheflush.h>
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2012-01-20 11:01:12 +00:00
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#include <asm/smp_plat.h>
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2010-07-26 12:08:52 +00:00
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#include <asm/smp_scu.h>
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2012-12-11 04:58:43 +00:00
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#include <asm/firmware.h>
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2010-07-26 12:08:52 +00:00
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2011-09-08 12:15:22 +00:00
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#include "common.h"
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2013-12-18 19:06:56 +00:00
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#include "regs-pmu.h"
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2011-09-08 12:15:22 +00:00
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2011-02-14 07:33:10 +00:00
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extern void exynos4_secondary_startup(void);
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2010-07-26 12:08:52 +00:00
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2012-11-24 02:13:48 +00:00
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static inline void __iomem *cpu_boot_reg_base(void)
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{
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if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
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return S5P_INFORM5;
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2014-05-12 22:13:44 +00:00
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return sysram_base_addr;
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2012-11-24 02:13:48 +00:00
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}
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static inline void __iomem *cpu_boot_reg(int cpu)
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{
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void __iomem *boot_reg;
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boot_reg = cpu_boot_reg_base();
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2014-05-12 22:13:44 +00:00
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if (!boot_reg)
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return ERR_PTR(-ENODEV);
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2012-11-24 02:13:48 +00:00
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if (soc_is_exynos4412())
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boot_reg += 4*cpu;
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2014-05-25 19:16:11 +00:00
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else if (soc_is_exynos5420() || soc_is_exynos5800())
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2013-06-18 15:29:35 +00:00
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boot_reg += 4;
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2012-11-24 02:13:48 +00:00
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return boot_reg;
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}
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2011-07-16 04:39:09 +00:00
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ARM: Fix subtle race in CPU pen_release hotplug code
There is a subtle race in the CPU hotplug code, where a CPU which has
been offlined can online itself before being requested, which results
in things going astray on the next online/offline cycle.
What happens in the normal online/offline/online cycle is:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads -1
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
However, as the write of -1 of pen_release is not fully flushed back to
memory, and the checking of pen_release is done with caches disabled,
this allows CPU3 the opportunity to read the old value of pen_release:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads 3
starts boot
pen_release = -1
requests boot of CPU3
pen_release = 3
flush cache line
Fix this by grouping the write of pen_release along with its cache line
flushing code to ensure that any update to pen_release is always pushed
out to physical memory.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-18 10:53:12 +00:00
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/*
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* Write pen_release in a way that is guaranteed to be visible to all
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* observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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static void write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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2013-12-05 19:26:16 +00:00
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sync_cache_w(&pen_release);
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ARM: Fix subtle race in CPU pen_release hotplug code
There is a subtle race in the CPU hotplug code, where a CPU which has
been offlined can online itself before being requested, which results
in things going astray on the next online/offline cycle.
What happens in the normal online/offline/online cycle is:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads -1
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
However, as the write of -1 of pen_release is not fully flushed back to
memory, and the checking of pen_release is done with caches disabled,
this allows CPU3 the opportunity to read the old value of pen_release:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads 3
starts boot
pen_release = -1
requests boot of CPU3
pen_release = 3
flush cache line
Fix this by grouping the write of pen_release along with its cache line
flushing code to ensure that any update to pen_release is always pushed
out to physical memory.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-18 10:53:12 +00:00
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}
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2010-07-26 12:08:52 +00:00
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static void __iomem *scu_base_addr(void)
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{
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return (void __iomem *)(S5P_VA_SCU);
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}
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static DEFINE_SPINLOCK(boot_lock);
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2013-06-17 19:43:14 +00:00
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static void exynos_secondary_init(unsigned int cpu)
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2010-07-26 12:08:52 +00:00
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{
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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ARM: Fix subtle race in CPU pen_release hotplug code
There is a subtle race in the CPU hotplug code, where a CPU which has
been offlined can online itself before being requested, which results
in things going astray on the next online/offline cycle.
What happens in the normal online/offline/online cycle is:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads -1
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
However, as the write of -1 of pen_release is not fully flushed back to
memory, and the checking of pen_release is done with caches disabled,
this allows CPU3 the opportunity to read the old value of pen_release:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads 3
starts boot
pen_release = -1
requests boot of CPU3
pen_release = 3
flush cache line
Fix this by grouping the write of pen_release along with its cache line
flushing code to ensure that any update to pen_release is always pushed
out to physical memory.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-18 10:53:12 +00:00
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write_pen_release(-1);
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2010-07-26 12:08:52 +00:00
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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2013-06-17 19:43:14 +00:00
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static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
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2010-07-26 12:08:52 +00:00
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{
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unsigned long timeout;
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2012-11-24 02:13:48 +00:00
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unsigned long phys_cpu = cpu_logical_map(cpu);
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2014-05-12 22:13:44 +00:00
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int ret = -ENOSYS;
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2010-07-26 12:08:52 +00:00
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/*
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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* the holding pen - release it, then wait for it to flag
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* that it has been released by resetting pen_release.
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*
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* Note that "pen_release" is the hardware CPU ID, whereas
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* "cpu" is Linux's internal ID.
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*/
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2012-11-24 02:13:48 +00:00
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write_pen_release(phys_cpu);
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2010-07-26 12:08:52 +00:00
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2014-05-15 19:23:25 +00:00
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if (!exynos_cpu_power_state(cpu)) {
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exynos_cpu_power_up(cpu);
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2011-07-16 04:39:09 +00:00
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timeout = 10;
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/* wait max 10 ms until cpu1 is on */
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2014-05-15 19:23:25 +00:00
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while (exynos_cpu_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) {
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2011-07-16 04:39:09 +00:00
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if (timeout-- == 0)
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break;
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mdelay(1);
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}
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if (timeout == 0) {
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printk(KERN_ERR "cpu1 power enable failed");
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spin_unlock(&boot_lock);
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return -ETIMEDOUT;
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}
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}
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2010-07-26 12:08:52 +00:00
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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2012-12-11 04:58:43 +00:00
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unsigned long boot_addr;
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2010-07-26 12:08:52 +00:00
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smp_rmb();
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2011-07-16 04:39:09 +00:00
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2012-12-11 04:58:43 +00:00
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boot_addr = virt_to_phys(exynos4_secondary_startup);
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/*
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* Try to set boot address using firmware first
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* and fall back to boot register if it fails.
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*/
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2014-05-12 22:13:44 +00:00
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ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
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if (ret && ret != -ENOSYS)
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goto fail;
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if (ret == -ENOSYS) {
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void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
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if (IS_ERR(boot_reg)) {
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ret = PTR_ERR(boot_reg);
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goto fail;
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}
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2012-12-11 04:58:43 +00:00
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__raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
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2014-05-12 22:13:44 +00:00
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}
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2012-12-11 04:58:43 +00:00
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call_firmware_op(cpu_boot, phys_cpu);
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2012-11-26 21:05:48 +00:00
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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2011-07-16 04:39:09 +00:00
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2010-07-26 12:08:52 +00:00
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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2014-05-12 22:13:44 +00:00
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fail:
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2010-07-26 12:08:52 +00:00
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spin_unlock(&boot_lock);
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2014-05-12 22:13:44 +00:00
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return pen_release != -1 ? ret : 0;
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2010-07-26 12:08:52 +00:00
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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2011-09-08 12:15:22 +00:00
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static void __init exynos_smp_init_cpus(void)
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2010-07-26 12:08:52 +00:00
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{
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void __iomem *scu_base = scu_base_addr();
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unsigned int i, ncores;
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2013-06-18 15:29:34 +00:00
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if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
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2012-01-25 06:35:57 +00:00
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ncores = scu_base ? scu_get_core_count(scu_base) : 1;
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2013-06-18 15:29:34 +00:00
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else
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/*
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* CPU Nodes are passed thru DT and set_cpu_possible
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* is set by "arm_dt_init_cpu_maps".
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*/
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return;
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2010-07-26 12:08:52 +00:00
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/* sanity check */
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2011-10-20 21:04:18 +00:00
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if (ncores > nr_cpu_ids) {
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pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
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ncores, nr_cpu_ids);
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ncores = nr_cpu_ids;
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2010-07-26 12:08:52 +00:00
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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}
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2011-09-08 12:15:22 +00:00
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static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
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2010-07-26 12:08:52 +00:00
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{
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2012-11-24 02:13:48 +00:00
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int i;
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2014-06-03 04:47:46 +00:00
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exynos_sysram_init();
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2013-06-10 09:28:04 +00:00
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if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
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2012-01-25 06:35:57 +00:00
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scu_enable(scu_base_addr());
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2010-12-03 11:09:48 +00:00
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2010-07-26 12:08:52 +00:00
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/*
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2010-12-03 11:09:48 +00:00
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* Write the address of secondary startup into the
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* system-wide flags register. The boot monitor waits
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* until it receives a soft interrupt, and then the
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* secondary CPU branches to this address.
|
2012-12-11 04:58:43 +00:00
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*
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* Try using firmware operation first and fall back to
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* boot register if it fails.
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2010-07-26 12:08:52 +00:00
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*/
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2012-12-11 04:58:43 +00:00
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for (i = 1; i < max_cpus; ++i) {
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unsigned long phys_cpu;
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unsigned long boot_addr;
|
2014-05-12 22:13:44 +00:00
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int ret;
|
2012-12-11 04:58:43 +00:00
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phys_cpu = cpu_logical_map(i);
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boot_addr = virt_to_phys(exynos4_secondary_startup);
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2014-05-12 22:13:44 +00:00
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ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
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if (ret && ret != -ENOSYS)
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break;
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if (ret == -ENOSYS) {
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void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
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if (IS_ERR(boot_reg))
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break;
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2012-12-11 04:58:43 +00:00
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__raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
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2014-05-12 22:13:44 +00:00
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}
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2012-12-11 04:58:43 +00:00
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}
|
2010-07-26 12:08:52 +00:00
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}
|
2011-09-08 12:15:22 +00:00
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struct smp_operations exynos_smp_ops __initdata = {
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.smp_init_cpus = exynos_smp_init_cpus,
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.smp_prepare_cpus = exynos_smp_prepare_cpus,
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.smp_secondary_init = exynos_secondary_init,
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.smp_boot_secondary = exynos_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = exynos_cpu_die,
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#endif
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};
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