net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
/*
|
|
|
|
* net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
|
|
|
|
* Copyright (c) 2008 Marvell Semiconductor
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
|
|
* (at your option) any later version.
|
|
|
|
*/
|
|
|
|
|
2013-01-08 16:05:54 +00:00
|
|
|
#include <linux/delay.h>
|
2015-03-27 01:36:38 +00:00
|
|
|
#include <linux/etherdevice.h>
|
2015-03-27 01:36:35 +00:00
|
|
|
#include <linux/if_bridge.h>
|
2013-01-08 16:05:54 +00:00
|
|
|
#include <linux/jiffies.h>
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
#include <linux/list.h>
|
2012-01-24 10:41:40 +00:00
|
|
|
#include <linux/module.h>
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
#include <linux/netdevice.h>
|
|
|
|
#include <linux/phy.h>
|
2011-11-27 17:06:08 +00:00
|
|
|
#include <net/dsa.h>
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
#include "mv88e6xxx.h"
|
|
|
|
|
2013-01-08 16:05:53 +00:00
|
|
|
/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
* use all 32 SMI bus addresses on its SMI bus, and all switch registers
|
|
|
|
* will be directly accessible on some {device address,register address}
|
|
|
|
* pair. If the ADDR[4:0] pins are not strapped to zero, the switch
|
|
|
|
* will only respond to SMI transactions to that specific address, and
|
|
|
|
* an indirect addressing mechanism needs to be used to access its
|
|
|
|
* registers.
|
|
|
|
*/
|
|
|
|
static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 16; i++) {
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = mdiobus_read(bus, sw_addr, SMI_CMD);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
if ((ret & SMI_CMD_BUSY) == 0)
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (sw_addr == 0)
|
|
|
|
return mdiobus_read(bus, addr, reg);
|
|
|
|
|
2013-01-08 16:05:53 +00:00
|
|
|
/* Wait for the bus to become free. */
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2013-01-08 16:05:53 +00:00
|
|
|
/* Transmit the read command. */
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = mdiobus_write(bus, sw_addr, SMI_CMD,
|
|
|
|
SMI_CMD_OP_22_READ | (addr << 5) | reg);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2013-01-08 16:05:53 +00:00
|
|
|
/* Wait for the read command to complete. */
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2013-01-08 16:05:53 +00:00
|
|
|
/* Read the data. */
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = mdiobus_read(bus, sw_addr, SMI_DATA);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return ret & 0xffff;
|
|
|
|
}
|
|
|
|
|
2015-03-27 01:36:31 +00:00
|
|
|
/* Must be called with SMI mutex held */
|
|
|
|
static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
{
|
2014-10-17 19:30:58 +00:00
|
|
|
struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
int ret;
|
|
|
|
|
2014-10-17 19:30:58 +00:00
|
|
|
if (bus == NULL)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
|
2015-01-23 21:10:36 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
|
|
|
|
addr, reg, ret);
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-03-27 01:36:31 +00:00
|
|
|
int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
mutex_lock(&ps->smi_mutex);
|
|
|
|
ret = _mv88e6xxx_reg_read(ds, addr, reg);
|
|
|
|
mutex_unlock(&ps->smi_mutex);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
|
|
|
|
int reg, u16 val)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (sw_addr == 0)
|
|
|
|
return mdiobus_write(bus, addr, reg, val);
|
|
|
|
|
2013-01-08 16:05:53 +00:00
|
|
|
/* Wait for the bus to become free. */
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2013-01-08 16:05:53 +00:00
|
|
|
/* Transmit the data to write. */
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = mdiobus_write(bus, sw_addr, SMI_DATA, val);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2013-01-08 16:05:53 +00:00
|
|
|
/* Transmit the write command. */
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = mdiobus_write(bus, sw_addr, SMI_CMD,
|
|
|
|
SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2013-01-08 16:05:53 +00:00
|
|
|
/* Wait for the write command to complete. */
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-03-27 01:36:31 +00:00
|
|
|
/* Must be called with SMI mutex held */
|
|
|
|
static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
|
|
|
|
u16 val)
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
{
|
2014-10-17 19:30:58 +00:00
|
|
|
struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
|
2014-10-17 19:30:58 +00:00
|
|
|
if (bus == NULL)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2015-01-23 21:10:36 +00:00
|
|
|
dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
|
|
|
|
addr, reg, val);
|
|
|
|
|
2015-03-27 01:36:31 +00:00
|
|
|
return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
int ret;
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
mutex_lock(&ps->smi_mutex);
|
2015-03-27 01:36:31 +00:00
|
|
|
ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
mutex_unlock(&ps->smi_mutex);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int mv88e6xxx_config_prio(struct dsa_switch *ds)
|
|
|
|
{
|
2013-01-08 16:05:53 +00:00
|
|
|
/* Configure the IP ToS mapping registers. */
|
2015-04-02 02:06:39 +00:00
|
|
|
REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
|
|
|
|
REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
|
|
|
|
REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
|
|
|
|
REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
|
|
|
|
REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
|
|
|
|
REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
|
|
|
|
REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
|
|
|
|
REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
|
2013-01-08 16:05:53 +00:00
|
|
|
/* Configure the IEEE 802.1p priority mapping register. */
|
2015-04-02 02:06:39 +00:00
|
|
|
REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-10-07 13:45:18 +00:00
|
|
|
int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
|
|
|
|
{
|
2015-04-02 02:06:39 +00:00
|
|
|
REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
|
|
|
|
REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
|
|
|
|
REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
|
2008-10-07 13:45:18 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
for (i = 0; i < 6; i++) {
|
|
|
|
int j;
|
|
|
|
|
2013-01-08 16:05:53 +00:00
|
|
|
/* Write the MAC address byte. */
|
2015-04-02 02:06:39 +00:00
|
|
|
REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
|
|
|
|
GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
|
2013-01-08 16:05:53 +00:00
|
|
|
/* Wait for the write to complete. */
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
for (j = 0; j < 16; j++) {
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
|
|
|
|
if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (j == 16)
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-04-02 02:06:36 +00:00
|
|
|
/* Must be called with phy mutex held */
|
|
|
|
static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
{
|
|
|
|
if (addr >= 0)
|
|
|
|
return mv88e6xxx_reg_read(ds, addr, regnum);
|
|
|
|
return 0xffff;
|
|
|
|
}
|
|
|
|
|
2015-04-02 02:06:36 +00:00
|
|
|
/* Must be called with phy mutex held */
|
|
|
|
static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
|
|
|
|
u16 val)
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
{
|
|
|
|
if (addr >= 0)
|
|
|
|
return mv88e6xxx_reg_write(ds, addr, regnum, val);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-10-07 13:45:18 +00:00
|
|
|
#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
|
|
|
|
static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
|
|
|
|
{
|
|
|
|
int ret;
|
2013-01-08 16:05:54 +00:00
|
|
|
unsigned long timeout;
|
2008-10-07 13:45:18 +00:00
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
|
|
|
|
REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
|
|
|
|
ret & ~GLOBAL_CONTROL_PPU_ENABLE);
|
2008-10-07 13:45:18 +00:00
|
|
|
|
2013-01-08 16:05:54 +00:00
|
|
|
timeout = jiffies + 1 * HZ;
|
|
|
|
while (time_before(jiffies, timeout)) {
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
|
2013-01-08 16:05:54 +00:00
|
|
|
usleep_range(1000, 2000);
|
2015-04-02 02:06:39 +00:00
|
|
|
if ((ret & GLOBAL_STATUS_PPU_MASK) !=
|
|
|
|
GLOBAL_STATUS_PPU_POLLING)
|
2013-01-08 16:05:56 +00:00
|
|
|
return 0;
|
2008-10-07 13:45:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
|
|
|
|
{
|
|
|
|
int ret;
|
2013-01-08 16:05:54 +00:00
|
|
|
unsigned long timeout;
|
2008-10-07 13:45:18 +00:00
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
|
|
|
|
REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
|
2008-10-07 13:45:18 +00:00
|
|
|
|
2013-01-08 16:05:54 +00:00
|
|
|
timeout = jiffies + 1 * HZ;
|
|
|
|
while (time_before(jiffies, timeout)) {
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
|
2013-01-08 16:05:54 +00:00
|
|
|
usleep_range(1000, 2000);
|
2015-04-02 02:06:39 +00:00
|
|
|
if ((ret & GLOBAL_STATUS_PPU_MASK) ==
|
|
|
|
GLOBAL_STATUS_PPU_POLLING)
|
2013-01-08 16:05:56 +00:00
|
|
|
return 0;
|
2008-10-07 13:45:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps;
|
|
|
|
|
|
|
|
ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
|
|
|
|
if (mutex_trylock(&ps->ppu_mutex)) {
|
2013-01-08 16:05:56 +00:00
|
|
|
struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
|
2008-10-07 13:45:18 +00:00
|
|
|
|
2013-01-08 16:05:56 +00:00
|
|
|
if (mv88e6xxx_ppu_enable(ds) == 0)
|
|
|
|
ps->ppu_disabled = 0;
|
|
|
|
mutex_unlock(&ps->ppu_mutex);
|
2008-10-07 13:45:18 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = (void *)_ps;
|
|
|
|
|
|
|
|
schedule_work(&ps->ppu_work);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
|
|
|
|
{
|
2014-04-28 18:14:28 +00:00
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
2008-10-07 13:45:18 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
mutex_lock(&ps->ppu_mutex);
|
|
|
|
|
2013-01-08 16:05:53 +00:00
|
|
|
/* If the PHY polling unit is enabled, disable it so that
|
2008-10-07 13:45:18 +00:00
|
|
|
* we can access the PHY registers. If it was already
|
|
|
|
* disabled, cancel the timer that is going to re-enable
|
|
|
|
* it.
|
|
|
|
*/
|
|
|
|
if (!ps->ppu_disabled) {
|
2013-01-08 16:05:56 +00:00
|
|
|
ret = mv88e6xxx_ppu_disable(ds);
|
|
|
|
if (ret < 0) {
|
|
|
|
mutex_unlock(&ps->ppu_mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
ps->ppu_disabled = 1;
|
2008-10-07 13:45:18 +00:00
|
|
|
} else {
|
2013-01-08 16:05:56 +00:00
|
|
|
del_timer(&ps->ppu_timer);
|
|
|
|
ret = 0;
|
2008-10-07 13:45:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
|
|
|
|
{
|
2014-04-28 18:14:28 +00:00
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
2008-10-07 13:45:18 +00:00
|
|
|
|
2013-01-08 16:05:53 +00:00
|
|
|
/* Schedule a timer to re-enable the PHY polling unit. */
|
2008-10-07 13:45:18 +00:00
|
|
|
mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
|
|
|
|
mutex_unlock(&ps->ppu_mutex);
|
|
|
|
}
|
|
|
|
|
|
|
|
void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
|
|
|
|
{
|
2014-04-28 18:14:28 +00:00
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
2008-10-07 13:45:18 +00:00
|
|
|
|
|
|
|
mutex_init(&ps->ppu_mutex);
|
|
|
|
INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
|
|
|
|
init_timer(&ps->ppu_timer);
|
|
|
|
ps->ppu_timer.data = (unsigned long)ps;
|
|
|
|
ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
|
|
|
|
}
|
|
|
|
|
|
|
|
int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mv88e6xxx_ppu_access_get(ds);
|
|
|
|
if (ret >= 0) {
|
2013-01-08 16:05:56 +00:00
|
|
|
ret = mv88e6xxx_reg_read(ds, addr, regnum);
|
|
|
|
mv88e6xxx_ppu_access_put(ds);
|
2008-10-07 13:45:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
|
|
|
|
int regnum, u16 val)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mv88e6xxx_ppu_access_get(ds);
|
|
|
|
if (ret >= 0) {
|
2013-01-08 16:05:56 +00:00
|
|
|
ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
|
|
|
|
mv88e6xxx_ppu_access_put(ds);
|
2008-10-07 13:45:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
void mv88e6xxx_poll_link(struct dsa_switch *ds)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < DSA_MAX_PORTS; i++) {
|
|
|
|
struct net_device *dev;
|
2008-11-26 00:50:49 +00:00
|
|
|
int uninitialized_var(port_status);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
int link;
|
|
|
|
int speed;
|
|
|
|
int duplex;
|
|
|
|
int fc;
|
|
|
|
|
|
|
|
dev = ds->ports[i];
|
|
|
|
if (dev == NULL)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
link = 0;
|
|
|
|
if (dev->flags & IFF_UP) {
|
2015-04-02 02:06:39 +00:00
|
|
|
port_status = mv88e6xxx_reg_read(ds, REG_PORT(i),
|
|
|
|
PORT_STATUS);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
if (port_status < 0)
|
|
|
|
continue;
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
link = !!(port_status & PORT_STATUS_LINK);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!link) {
|
|
|
|
if (netif_carrier_ok(dev)) {
|
2013-01-08 16:05:55 +00:00
|
|
|
netdev_info(dev, "link down\n");
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
netif_carrier_off(dev);
|
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
switch (port_status & PORT_STATUS_SPEED_MASK) {
|
|
|
|
case PORT_STATUS_SPEED_10:
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
speed = 10;
|
|
|
|
break;
|
2015-04-02 02:06:39 +00:00
|
|
|
case PORT_STATUS_SPEED_100:
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
speed = 100;
|
|
|
|
break;
|
2015-04-02 02:06:39 +00:00
|
|
|
case PORT_STATUS_SPEED_1000:
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
speed = 1000;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
speed = -1;
|
|
|
|
break;
|
|
|
|
}
|
2015-04-02 02:06:39 +00:00
|
|
|
duplex = (port_status & PORT_STATUS_DUPLEX) ? 1 : 0;
|
|
|
|
fc = (port_status & PORT_STATUS_PAUSE_EN) ? 1 : 0;
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
|
|
|
|
if (!netif_carrier_ok(dev)) {
|
2013-01-08 16:05:55 +00:00
|
|
|
netdev_info(dev,
|
|
|
|
"link up, %d Mb/s, %s duplex, flow control %sabled\n",
|
|
|
|
speed,
|
|
|
|
duplex ? "full" : "half",
|
|
|
|
fc ? "en" : "dis");
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
netif_carrier_on(dev);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-04-02 02:06:40 +00:00
|
|
|
static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
|
|
|
|
switch (ps->id) {
|
|
|
|
case PORT_SWITCH_ID_6352:
|
|
|
|
case PORT_SWITCH_ID_6172:
|
|
|
|
case PORT_SWITCH_ID_6176:
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
static int mv88e6xxx_stats_wait(struct dsa_switch *ds)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 10; i++) {
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = REG_READ(REG_GLOBAL, GLOBAL_STATS_OP);
|
|
|
|
if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2015-04-02 02:06:40 +00:00
|
|
|
if (mv88e6xxx_6352_family(ds))
|
|
|
|
port = (port + 1) << 5;
|
|
|
|
|
2013-01-08 16:05:53 +00:00
|
|
|
/* Snapshot the hardware statistics counters for this port. */
|
2015-04-02 02:06:39 +00:00
|
|
|
REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP,
|
|
|
|
GLOBAL_STATS_OP_CAPTURE_PORT |
|
|
|
|
GLOBAL_STATS_OP_HIST_RX_TX | port);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
|
2013-01-08 16:05:53 +00:00
|
|
|
/* Wait for the snapshotting to complete. */
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
ret = mv88e6xxx_stats_wait(ds);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
|
|
|
|
{
|
|
|
|
u32 _val;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
*val = 0;
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
|
|
|
|
GLOBAL_STATS_OP_READ_CAPTURED |
|
|
|
|
GLOBAL_STATS_OP_HIST_RX_TX | stat);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
ret = mv88e6xxx_stats_wait(ds);
|
|
|
|
if (ret < 0)
|
|
|
|
return;
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
_val = ret << 16;
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
*val = _val | ret;
|
|
|
|
}
|
|
|
|
|
2015-04-02 02:06:38 +00:00
|
|
|
static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
|
|
|
|
{ "in_good_octets", 8, 0x00, },
|
|
|
|
{ "in_bad_octets", 4, 0x02, },
|
|
|
|
{ "in_unicast", 4, 0x04, },
|
|
|
|
{ "in_broadcasts", 4, 0x06, },
|
|
|
|
{ "in_multicasts", 4, 0x07, },
|
|
|
|
{ "in_pause", 4, 0x16, },
|
|
|
|
{ "in_undersize", 4, 0x18, },
|
|
|
|
{ "in_fragments", 4, 0x19, },
|
|
|
|
{ "in_oversize", 4, 0x1a, },
|
|
|
|
{ "in_jabber", 4, 0x1b, },
|
|
|
|
{ "in_rx_error", 4, 0x1c, },
|
|
|
|
{ "in_fcs_error", 4, 0x1d, },
|
|
|
|
{ "out_octets", 8, 0x0e, },
|
|
|
|
{ "out_unicast", 4, 0x10, },
|
|
|
|
{ "out_broadcasts", 4, 0x13, },
|
|
|
|
{ "out_multicasts", 4, 0x12, },
|
|
|
|
{ "out_pause", 4, 0x15, },
|
|
|
|
{ "excessive", 4, 0x11, },
|
|
|
|
{ "collisions", 4, 0x1e, },
|
|
|
|
{ "deferred", 4, 0x05, },
|
|
|
|
{ "single", 4, 0x14, },
|
|
|
|
{ "multiple", 4, 0x17, },
|
|
|
|
{ "out_fcs_error", 4, 0x03, },
|
|
|
|
{ "late", 4, 0x1f, },
|
|
|
|
{ "hist_64bytes", 4, 0x08, },
|
|
|
|
{ "hist_65_127bytes", 4, 0x09, },
|
|
|
|
{ "hist_128_255bytes", 4, 0x0a, },
|
|
|
|
{ "hist_256_511bytes", 4, 0x0b, },
|
|
|
|
{ "hist_512_1023bytes", 4, 0x0c, },
|
|
|
|
{ "hist_1024_max_bytes", 4, 0x0d, },
|
|
|
|
/* Not all devices have the following counters */
|
|
|
|
{ "sw_in_discards", 4, 0x110, },
|
|
|
|
{ "sw_in_filtered", 2, 0x112, },
|
|
|
|
{ "sw_out_filtered", 2, 0x113, },
|
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
static bool have_sw_in_discards(struct dsa_switch *ds)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
|
|
|
|
switch (ps->id) {
|
2015-04-02 02:06:39 +00:00
|
|
|
case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161:
|
|
|
|
case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171:
|
|
|
|
case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176:
|
|
|
|
case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185:
|
|
|
|
case PORT_SWITCH_ID_6352:
|
2015-04-02 02:06:38 +00:00
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void _mv88e6xxx_get_strings(struct dsa_switch *ds,
|
|
|
|
int nr_stats,
|
|
|
|
struct mv88e6xxx_hw_stat *stats,
|
|
|
|
int port, uint8_t *data)
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < nr_stats; i++) {
|
|
|
|
memcpy(data + i * ETH_GSTRING_LEN,
|
|
|
|
stats[i].string, ETH_GSTRING_LEN);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-04-02 02:06:38 +00:00
|
|
|
static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
|
|
|
|
int nr_stats,
|
|
|
|
struct mv88e6xxx_hw_stat *stats,
|
|
|
|
int port, uint64_t *data)
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
{
|
2014-04-28 18:14:28 +00:00
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
int ret;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
mutex_lock(&ps->stats_mutex);
|
|
|
|
|
|
|
|
ret = mv88e6xxx_stats_snapshot(ds, port);
|
|
|
|
if (ret < 0) {
|
|
|
|
mutex_unlock(&ps->stats_mutex);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-01-08 16:05:53 +00:00
|
|
|
/* Read each of the counters. */
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
for (i = 0; i < nr_stats; i++) {
|
|
|
|
struct mv88e6xxx_hw_stat *s = stats + i;
|
|
|
|
u32 low;
|
2014-10-29 17:45:07 +00:00
|
|
|
u32 high = 0;
|
|
|
|
|
|
|
|
if (s->reg >= 0x100) {
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
|
|
|
|
s->reg - 0x100);
|
|
|
|
if (ret < 0)
|
|
|
|
goto error;
|
|
|
|
low = ret;
|
|
|
|
if (s->sizeof_stat == 4) {
|
|
|
|
ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
|
|
|
|
s->reg - 0x100 + 1);
|
|
|
|
if (ret < 0)
|
|
|
|
goto error;
|
|
|
|
high = ret;
|
|
|
|
}
|
|
|
|
data[i] = (((u64)high) << 16) | low;
|
|
|
|
continue;
|
|
|
|
}
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
mv88e6xxx_stats_read(ds, s->reg, &low);
|
|
|
|
if (s->sizeof_stat == 8)
|
|
|
|
mv88e6xxx_stats_read(ds, s->reg + 1, &high);
|
|
|
|
|
|
|
|
data[i] = (((u64)high) << 32) | low;
|
|
|
|
}
|
2014-10-29 17:45:07 +00:00
|
|
|
error:
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 13:44:02 +00:00
|
|
|
mutex_unlock(&ps->stats_mutex);
|
|
|
|
}
|
2011-11-25 14:36:19 +00:00
|
|
|
|
2015-04-02 02:06:38 +00:00
|
|
|
/* All the statistics in the table */
|
|
|
|
void
|
|
|
|
mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
|
|
|
|
{
|
|
|
|
if (have_sw_in_discards(ds))
|
|
|
|
_mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
|
|
|
|
mv88e6xxx_hw_stats, port, data);
|
|
|
|
else
|
|
|
|
_mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
|
|
|
|
mv88e6xxx_hw_stats, port, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
|
|
|
|
{
|
|
|
|
if (have_sw_in_discards(ds))
|
|
|
|
return ARRAY_SIZE(mv88e6xxx_hw_stats);
|
|
|
|
return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
|
|
|
|
int port, uint64_t *data)
|
|
|
|
{
|
|
|
|
if (have_sw_in_discards(ds))
|
|
|
|
_mv88e6xxx_get_ethtool_stats(
|
|
|
|
ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
|
|
|
|
mv88e6xxx_hw_stats, port, data);
|
|
|
|
else
|
|
|
|
_mv88e6xxx_get_ethtool_stats(
|
|
|
|
ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
|
|
|
|
mv88e6xxx_hw_stats, port, data);
|
|
|
|
}
|
|
|
|
|
2014-10-29 17:45:05 +00:00
|
|
|
int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
|
|
|
|
{
|
|
|
|
return 32 * sizeof(u16);
|
|
|
|
}
|
|
|
|
|
|
|
|
void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
|
|
|
|
struct ethtool_regs *regs, void *_p)
|
|
|
|
{
|
|
|
|
u16 *p = _p;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
regs->version = 0;
|
|
|
|
|
|
|
|
memset(p, 0xff, 32 * sizeof(u16));
|
|
|
|
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
|
|
|
|
if (ret >= 0)
|
|
|
|
p[i] = ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-11-15 21:24:51 +00:00
|
|
|
#ifdef CONFIG_NET_DSA_HWMON
|
|
|
|
|
|
|
|
int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
int ret;
|
|
|
|
int val;
|
|
|
|
|
|
|
|
*temp = 0;
|
|
|
|
|
|
|
|
mutex_lock(&ps->phy_mutex);
|
|
|
|
|
2015-04-02 02:06:36 +00:00
|
|
|
ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
|
2014-11-15 21:24:51 +00:00
|
|
|
if (ret < 0)
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
/* Enable temperature sensor */
|
2015-04-02 02:06:36 +00:00
|
|
|
ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
|
2014-11-15 21:24:51 +00:00
|
|
|
if (ret < 0)
|
|
|
|
goto error;
|
|
|
|
|
2015-04-02 02:06:36 +00:00
|
|
|
ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
|
2014-11-15 21:24:51 +00:00
|
|
|
if (ret < 0)
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
/* Wait for temperature to stabilize */
|
|
|
|
usleep_range(10000, 12000);
|
|
|
|
|
2015-04-02 02:06:36 +00:00
|
|
|
val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
|
2014-11-15 21:24:51 +00:00
|
|
|
if (val < 0) {
|
|
|
|
ret = val;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Disable temperature sensor */
|
2015-04-02 02:06:36 +00:00
|
|
|
ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
|
2014-11-15 21:24:51 +00:00
|
|
|
if (ret < 0)
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
*temp = ((val & 0x1f) - 5) * 5;
|
|
|
|
|
|
|
|
error:
|
2015-04-02 02:06:36 +00:00
|
|
|
_mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
|
2014-11-15 21:24:51 +00:00
|
|
|
mutex_unlock(&ps->phy_mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_NET_DSA_HWMON */
|
|
|
|
|
2015-02-14 18:17:50 +00:00
|
|
|
static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
|
|
|
|
{
|
|
|
|
unsigned long timeout = jiffies + HZ / 10;
|
|
|
|
|
|
|
|
while (time_before(jiffies, timeout)) {
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = REG_READ(reg, offset);
|
|
|
|
if (!(ret & mask))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
usleep_range(1000, 2000);
|
|
|
|
}
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
int mv88e6xxx_phy_wait(struct dsa_switch *ds)
|
|
|
|
{
|
2015-04-02 02:06:39 +00:00
|
|
|
return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
|
|
|
|
GLOBAL2_SMI_OP_BUSY);
|
2015-02-14 18:17:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
|
|
|
|
{
|
2015-04-02 02:06:39 +00:00
|
|
|
return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
|
|
|
|
GLOBAL2_EEPROM_OP_LOAD);
|
2015-02-14 18:17:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
|
|
|
|
{
|
2015-04-02 02:06:39 +00:00
|
|
|
return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
|
|
|
|
GLOBAL2_EEPROM_OP_BUSY);
|
2015-02-14 18:17:50 +00:00
|
|
|
}
|
|
|
|
|
2015-03-27 01:36:35 +00:00
|
|
|
/* Must be called with SMI lock held */
|
|
|
|
static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
|
|
|
|
{
|
|
|
|
unsigned long timeout = jiffies + HZ / 10;
|
|
|
|
|
|
|
|
while (time_before(jiffies, timeout)) {
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = _mv88e6xxx_reg_read(ds, reg, offset);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
if (!(ret & mask))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
usleep_range(1000, 2000);
|
|
|
|
}
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Must be called with SMI lock held */
|
|
|
|
static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
|
|
|
|
{
|
2015-04-02 02:06:39 +00:00
|
|
|
return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
|
|
|
|
GLOBAL_ATU_OP_BUSY);
|
2015-03-27 01:36:35 +00:00
|
|
|
}
|
|
|
|
|
2015-04-02 02:06:36 +00:00
|
|
|
/* Must be called with phy mutex held */
|
|
|
|
static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
|
|
|
|
int regnum)
|
2015-02-14 18:17:50 +00:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
REG_WRITE(REG_GLOBAL2, GLOBAL2_SMI_OP,
|
|
|
|
GLOBAL2_SMI_OP_22_READ | (addr << 5) | regnum);
|
2015-02-14 18:17:50 +00:00
|
|
|
|
|
|
|
ret = mv88e6xxx_phy_wait(ds);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
return REG_READ(REG_GLOBAL2, GLOBAL2_SMI_DATA);
|
2015-02-14 18:17:50 +00:00
|
|
|
}
|
|
|
|
|
2015-04-02 02:06:36 +00:00
|
|
|
/* Must be called with phy mutex held */
|
|
|
|
static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
|
|
|
|
int regnum, u16 val)
|
2015-02-14 18:17:50 +00:00
|
|
|
{
|
2015-04-02 02:06:39 +00:00
|
|
|
REG_WRITE(REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
|
|
|
|
REG_WRITE(REG_GLOBAL2, GLOBAL2_SMI_OP,
|
|
|
|
GLOBAL2_SMI_OP_22_WRITE | (addr << 5) | regnum);
|
2015-02-14 18:17:50 +00:00
|
|
|
|
|
|
|
return mv88e6xxx_phy_wait(ds);
|
|
|
|
}
|
|
|
|
|
2015-03-07 06:23:51 +00:00
|
|
|
int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
|
|
|
|
{
|
2015-04-02 02:06:37 +00:00
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
2015-03-07 06:23:51 +00:00
|
|
|
int reg;
|
|
|
|
|
2015-04-02 02:06:37 +00:00
|
|
|
mutex_lock(&ps->phy_mutex);
|
|
|
|
|
|
|
|
reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
|
2015-03-07 06:23:51 +00:00
|
|
|
if (reg < 0)
|
2015-04-02 02:06:37 +00:00
|
|
|
goto out;
|
2015-03-07 06:23:51 +00:00
|
|
|
|
|
|
|
e->eee_enabled = !!(reg & 0x0200);
|
|
|
|
e->tx_lpi_enabled = !!(reg & 0x0100);
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
reg = mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
|
2015-03-07 06:23:51 +00:00
|
|
|
if (reg < 0)
|
2015-04-02 02:06:37 +00:00
|
|
|
goto out;
|
2015-03-07 06:23:51 +00:00
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
e->eee_active = !!(reg & PORT_STATUS_EEE);
|
2015-04-02 02:06:37 +00:00
|
|
|
reg = 0;
|
2015-03-07 06:23:51 +00:00
|
|
|
|
2015-04-02 02:06:37 +00:00
|
|
|
out:
|
|
|
|
mutex_unlock(&ps->phy_mutex);
|
|
|
|
return reg;
|
2015-03-07 06:23:51 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
|
|
|
|
struct phy_device *phydev, struct ethtool_eee *e)
|
|
|
|
{
|
2015-04-02 02:06:37 +00:00
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
int reg;
|
2015-03-07 06:23:51 +00:00
|
|
|
int ret;
|
|
|
|
|
2015-04-02 02:06:37 +00:00
|
|
|
mutex_lock(&ps->phy_mutex);
|
2015-03-07 06:23:51 +00:00
|
|
|
|
2015-04-02 02:06:37 +00:00
|
|
|
ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
reg = ret & ~0x0300;
|
|
|
|
if (e->eee_enabled)
|
|
|
|
reg |= 0x0200;
|
|
|
|
if (e->tx_lpi_enabled)
|
|
|
|
reg |= 0x0100;
|
|
|
|
|
|
|
|
ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
|
|
|
|
out:
|
|
|
|
mutex_unlock(&ps->phy_mutex);
|
|
|
|
|
|
|
|
return ret;
|
2015-03-07 06:23:51 +00:00
|
|
|
}
|
|
|
|
|
2015-03-27 01:36:35 +00:00
|
|
|
static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x01, fid);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
|
2015-03-27 01:36:35 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return _mv88e6xxx_atu_wait(ds);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = _mv88e6xxx_atu_wait(ds);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
return _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB);
|
2015-03-27 01:36:35 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
int reg, ret;
|
|
|
|
u8 oldstate;
|
|
|
|
|
|
|
|
mutex_lock(&ps->smi_mutex);
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
|
2015-03-27 01:36:35 +00:00
|
|
|
if (reg < 0)
|
|
|
|
goto abort;
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
oldstate = reg & PORT_CONTROL_STATE_MASK;
|
2015-03-27 01:36:35 +00:00
|
|
|
if (oldstate != state) {
|
|
|
|
/* Flush forwarding database if we're moving a port
|
|
|
|
* from Learning or Forwarding state to Disabled or
|
|
|
|
* Blocking or Listening state.
|
|
|
|
*/
|
2015-04-02 02:06:39 +00:00
|
|
|
if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
|
|
|
|
state <= PORT_CONTROL_STATE_BLOCKING) {
|
2015-03-27 01:36:35 +00:00
|
|
|
ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]);
|
|
|
|
if (ret)
|
|
|
|
goto abort;
|
|
|
|
}
|
2015-04-02 02:06:39 +00:00
|
|
|
reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
|
|
|
|
ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
|
|
|
|
reg);
|
2015-03-27 01:36:35 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
abort:
|
|
|
|
mutex_unlock(&ps->smi_mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Must be called with smi lock held */
|
|
|
|
static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
u8 fid = ps->fid[port];
|
|
|
|
u16 reg = fid << 12;
|
|
|
|
|
|
|
|
if (dsa_is_cpu_port(ds, port))
|
|
|
|
reg |= ds->phys_port_mask;
|
|
|
|
else
|
|
|
|
reg |= (ps->bridge_mask[fid] |
|
|
|
|
(1 << dsa_upstream_port(ds))) & ~(1 << port);
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
|
2015-03-27 01:36:35 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Must be called with smi lock held */
|
|
|
|
static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
int port;
|
|
|
|
u32 mask;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
mask = ds->phys_port_mask;
|
|
|
|
while (mask) {
|
|
|
|
port = __ffs(mask);
|
|
|
|
mask &= ~(1 << port);
|
|
|
|
if (ps->fid[port] != fid)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
ret = _mv88e6xxx_update_port_config(ds, port);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return _mv88e6xxx_flush_fid(ds, fid);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Bridge handling functions */
|
|
|
|
|
|
|
|
int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
int ret = 0;
|
|
|
|
u32 nmask;
|
|
|
|
int fid;
|
|
|
|
|
|
|
|
/* If the bridge group is not empty, join that group.
|
|
|
|
* Otherwise create a new group.
|
|
|
|
*/
|
|
|
|
fid = ps->fid[port];
|
|
|
|
nmask = br_port_mask & ~(1 << port);
|
|
|
|
if (nmask)
|
|
|
|
fid = ps->fid[__ffs(nmask)];
|
|
|
|
|
|
|
|
nmask = ps->bridge_mask[fid] | (1 << port);
|
|
|
|
if (nmask != br_port_mask) {
|
|
|
|
netdev_err(ds->ports[port],
|
|
|
|
"join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
|
|
|
|
fid, br_port_mask, nmask);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_lock(&ps->smi_mutex);
|
|
|
|
|
|
|
|
ps->bridge_mask[fid] = br_port_mask;
|
|
|
|
|
|
|
|
if (fid != ps->fid[port]) {
|
|
|
|
ps->fid_mask |= 1 << ps->fid[port];
|
|
|
|
ps->fid[port] = fid;
|
|
|
|
ret = _mv88e6xxx_update_bridge_config(ds, fid);
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_unlock(&ps->smi_mutex);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
u8 fid, newfid;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
fid = ps->fid[port];
|
|
|
|
|
|
|
|
if (ps->bridge_mask[fid] != br_port_mask) {
|
|
|
|
netdev_err(ds->ports[port],
|
|
|
|
"leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
|
|
|
|
fid, br_port_mask, ps->bridge_mask[fid]);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If the port was the last port of a bridge, we are done.
|
|
|
|
* Otherwise assign a new fid to the port, and fix up
|
|
|
|
* the bridge configuration.
|
|
|
|
*/
|
|
|
|
if (br_port_mask == (1 << port))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
mutex_lock(&ps->smi_mutex);
|
|
|
|
|
|
|
|
newfid = __ffs(ps->fid_mask);
|
|
|
|
ps->fid[port] = newfid;
|
|
|
|
ps->fid_mask &= (1 << newfid);
|
|
|
|
ps->bridge_mask[fid] &= ~(1 << port);
|
|
|
|
ps->bridge_mask[newfid] = 1 << port;
|
|
|
|
|
|
|
|
ret = _mv88e6xxx_update_bridge_config(ds, fid);
|
|
|
|
if (!ret)
|
|
|
|
ret = _mv88e6xxx_update_bridge_config(ds, newfid);
|
|
|
|
|
|
|
|
mutex_unlock(&ps->smi_mutex);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
int stp_state;
|
|
|
|
|
|
|
|
switch (state) {
|
|
|
|
case BR_STATE_DISABLED:
|
2015-04-02 02:06:39 +00:00
|
|
|
stp_state = PORT_CONTROL_STATE_DISABLED;
|
2015-03-27 01:36:35 +00:00
|
|
|
break;
|
|
|
|
case BR_STATE_BLOCKING:
|
|
|
|
case BR_STATE_LISTENING:
|
2015-04-02 02:06:39 +00:00
|
|
|
stp_state = PORT_CONTROL_STATE_BLOCKING;
|
2015-03-27 01:36:35 +00:00
|
|
|
break;
|
|
|
|
case BR_STATE_LEARNING:
|
2015-04-02 02:06:39 +00:00
|
|
|
stp_state = PORT_CONTROL_STATE_LEARNING;
|
2015-03-27 01:36:35 +00:00
|
|
|
break;
|
|
|
|
case BR_STATE_FORWARDING:
|
|
|
|
default:
|
2015-04-02 02:06:39 +00:00
|
|
|
stp_state = PORT_CONTROL_STATE_FORWARDING;
|
2015-03-27 01:36:35 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
|
|
|
|
|
|
|
|
/* mv88e6xxx_port_stp_update may be called with softirqs disabled,
|
|
|
|
* so we can not update the port state directly but need to schedule it.
|
|
|
|
*/
|
|
|
|
ps->port_state[port] = stp_state;
|
|
|
|
set_bit(port, &ps->port_state_update_mask);
|
|
|
|
schedule_work(&ps->bridge_work);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-03-27 01:36:38 +00:00
|
|
|
static int __mv88e6xxx_write_addr(struct dsa_switch *ds,
|
|
|
|
const unsigned char *addr)
|
|
|
|
{
|
|
|
|
int i, ret;
|
|
|
|
|
|
|
|
for (i = 0; i < 3; i++) {
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = _mv88e6xxx_reg_write(
|
|
|
|
ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
|
|
|
|
(addr[i * 2] << 8) | addr[i * 2 + 1]);
|
2015-03-27 01:36:38 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __mv88e6xxx_read_addr(struct dsa_switch *ds, unsigned char *addr)
|
|
|
|
{
|
|
|
|
int i, ret;
|
|
|
|
|
|
|
|
for (i = 0; i < 3; i++) {
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
|
|
|
|
GLOBAL_ATU_MAC_01 + i);
|
2015-03-27 01:36:38 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
addr[i * 2] = ret >> 8;
|
|
|
|
addr[i * 2 + 1] = ret & 0xff;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __mv88e6xxx_port_fdb_cmd(struct dsa_switch *ds, int port,
|
|
|
|
const unsigned char *addr, int state)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
u8 fid = ps->fid[port];
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = _mv88e6xxx_atu_wait(ds);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = __mv88e6xxx_write_addr(ds, addr);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA,
|
2015-03-27 01:36:38 +00:00
|
|
|
(0x10 << port) | state);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_LOAD_DB);
|
2015-03-27 01:36:38 +00:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
|
|
|
|
const unsigned char *addr, u16 vid)
|
|
|
|
{
|
|
|
|
int state = is_multicast_ether_addr(addr) ?
|
2015-04-02 02:06:39 +00:00
|
|
|
GLOBAL_ATU_DATA_STATE_MC_STATIC :
|
|
|
|
GLOBAL_ATU_DATA_STATE_UC_STATIC;
|
2015-03-27 01:36:38 +00:00
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
mutex_lock(&ps->smi_mutex);
|
|
|
|
ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, state);
|
|
|
|
mutex_unlock(&ps->smi_mutex);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
|
|
|
|
const unsigned char *addr, u16 vid)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
mutex_lock(&ps->smi_mutex);
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr,
|
|
|
|
GLOBAL_ATU_DATA_STATE_UNUSED);
|
2015-03-27 01:36:38 +00:00
|
|
|
mutex_unlock(&ps->smi_mutex);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __mv88e6xxx_port_getnext(struct dsa_switch *ds, int port,
|
|
|
|
unsigned char *addr, bool *is_static)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
u8 fid = ps->fid[port];
|
|
|
|
int ret, state;
|
|
|
|
|
|
|
|
ret = _mv88e6xxx_atu_wait(ds);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = __mv88e6xxx_write_addr(ds, addr);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
do {
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
|
2015-03-27 01:36:38 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
|
2015-03-27 01:36:38 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2015-04-02 02:06:39 +00:00
|
|
|
state = ret & GLOBAL_ATU_DATA_STATE_MASK;
|
|
|
|
if (state == GLOBAL_ATU_DATA_STATE_UNUSED)
|
2015-03-27 01:36:38 +00:00
|
|
|
return -ENOENT;
|
|
|
|
} while (!(((ret >> 4) & 0xff) & (1 << port)));
|
|
|
|
|
|
|
|
ret = __mv88e6xxx_read_addr(ds, addr);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
*is_static = state == (is_multicast_ether_addr(addr) ?
|
2015-04-02 02:06:39 +00:00
|
|
|
GLOBAL_ATU_DATA_STATE_MC_STATIC :
|
|
|
|
GLOBAL_ATU_DATA_STATE_UC_STATIC);
|
2015-03-27 01:36:38 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* get next entry for port */
|
|
|
|
int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
|
|
|
|
unsigned char *addr, bool *is_static)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
mutex_lock(&ps->smi_mutex);
|
|
|
|
ret = __mv88e6xxx_port_getnext(ds, port, addr, is_static);
|
|
|
|
mutex_unlock(&ps->smi_mutex);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-03-27 01:36:35 +00:00
|
|
|
static void mv88e6xxx_bridge_work(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps;
|
|
|
|
struct dsa_switch *ds;
|
|
|
|
int port;
|
|
|
|
|
|
|
|
ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
|
|
|
|
ds = ((struct dsa_switch *)ps) - 1;
|
|
|
|
|
|
|
|
while (ps->port_state_update_mask) {
|
|
|
|
port = __ffs(ps->port_state_update_mask);
|
|
|
|
clear_bit(port, &ps->port_state_update_mask);
|
|
|
|
mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-03-27 01:36:29 +00:00
|
|
|
int mv88e6xxx_setup_port_common(struct dsa_switch *ds, int port)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
2015-03-27 01:36:35 +00:00
|
|
|
int ret, fid;
|
2015-03-27 01:36:29 +00:00
|
|
|
|
|
|
|
mutex_lock(&ps->smi_mutex);
|
|
|
|
|
2015-03-27 01:36:30 +00:00
|
|
|
/* Port Control 1: disable trunking, disable sending
|
|
|
|
* learning messages to this port.
|
2015-03-27 01:36:29 +00:00
|
|
|
*/
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
|
|
|
|
0x0000);
|
2015-03-27 01:36:29 +00:00
|
|
|
if (ret)
|
|
|
|
goto abort;
|
|
|
|
|
|
|
|
/* Port based VLAN map: give each port its own address
|
|
|
|
* database, allow the CPU port to talk to each of the 'real'
|
|
|
|
* ports, and allow each of the 'real' ports to only talk to
|
|
|
|
* the upstream port.
|
|
|
|
*/
|
2015-03-27 01:36:35 +00:00
|
|
|
fid = __ffs(ps->fid_mask);
|
|
|
|
ps->fid[port] = fid;
|
|
|
|
ps->fid_mask &= ~(1 << fid);
|
|
|
|
|
|
|
|
if (!dsa_is_cpu_port(ds, port))
|
|
|
|
ps->bridge_mask[fid] = 1 << port;
|
2015-03-27 01:36:29 +00:00
|
|
|
|
2015-03-27 01:36:35 +00:00
|
|
|
ret = _mv88e6xxx_update_port_config(ds, port);
|
2015-03-27 01:36:29 +00:00
|
|
|
if (ret)
|
|
|
|
goto abort;
|
|
|
|
|
|
|
|
/* Default VLAN ID and priority: don't set a default VLAN
|
|
|
|
* ID, and set the default packet priority to zero.
|
|
|
|
*/
|
|
|
|
ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x07, 0x0000);
|
|
|
|
abort:
|
|
|
|
mutex_unlock(&ps->smi_mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-03-27 01:36:28 +00:00
|
|
|
int mv88e6xxx_setup_common(struct dsa_switch *ds)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
|
|
|
|
mutex_init(&ps->smi_mutex);
|
|
|
|
mutex_init(&ps->stats_mutex);
|
|
|
|
mutex_init(&ps->phy_mutex);
|
|
|
|
|
2015-04-02 02:06:39 +00:00
|
|
|
ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
|
2015-03-27 01:36:40 +00:00
|
|
|
|
2015-03-27 01:36:35 +00:00
|
|
|
ps->fid_mask = (1 << DSA_MAX_PORTS) - 1;
|
|
|
|
|
|
|
|
INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
|
|
|
|
|
2015-03-27 01:36:28 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-04-02 02:06:34 +00:00
|
|
|
int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
|
|
|
|
unsigned long timeout;
|
|
|
|
int ret;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Set all ports to the disabled state. */
|
|
|
|
for (i = 0; i < ps->num_ports; i++) {
|
2015-04-02 02:06:39 +00:00
|
|
|
ret = REG_READ(REG_PORT(i), PORT_CONTROL);
|
|
|
|
REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
|
2015-04-02 02:06:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Wait for transmit queues to drain. */
|
|
|
|
usleep_range(2000, 4000);
|
|
|
|
|
|
|
|
/* Reset the switch. Keep the PPU active if requested. The PPU
|
|
|
|
* needs to be active to support indirect phy register access
|
|
|
|
* through global registers 0x18 and 0x19.
|
|
|
|
*/
|
|
|
|
if (ppu_active)
|
|
|
|
REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
|
|
|
|
else
|
|
|
|
REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
|
|
|
|
|
|
|
|
/* Wait up to one second for reset to complete. */
|
|
|
|
timeout = jiffies + 1 * HZ;
|
|
|
|
while (time_before(jiffies, timeout)) {
|
|
|
|
ret = REG_READ(REG_GLOBAL, 0x00);
|
|
|
|
if ((ret & is_reset) == is_reset)
|
|
|
|
break;
|
|
|
|
usleep_range(1000, 2000);
|
|
|
|
}
|
|
|
|
if (time_after(jiffies, timeout))
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-04-02 02:06:35 +00:00
|
|
|
int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
mutex_lock(&ps->phy_mutex);
|
2015-04-02 02:06:36 +00:00
|
|
|
ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
|
2015-04-02 02:06:35 +00:00
|
|
|
if (ret < 0)
|
|
|
|
goto error;
|
2015-04-02 02:06:36 +00:00
|
|
|
ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
|
2015-04-02 02:06:35 +00:00
|
|
|
error:
|
2015-04-02 02:06:36 +00:00
|
|
|
_mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
|
2015-04-02 02:06:35 +00:00
|
|
|
mutex_unlock(&ps->phy_mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
|
|
|
|
int reg, int val)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
mutex_lock(&ps->phy_mutex);
|
2015-04-02 02:06:36 +00:00
|
|
|
ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
|
2015-04-02 02:06:35 +00:00
|
|
|
if (ret < 0)
|
|
|
|
goto error;
|
|
|
|
|
2015-04-02 02:06:36 +00:00
|
|
|
ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
|
2015-04-02 02:06:35 +00:00
|
|
|
error:
|
2015-04-02 02:06:36 +00:00
|
|
|
_mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
|
|
|
|
mutex_unlock(&ps->phy_mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
|
|
|
|
if (port >= 0 && port < ps->num_ports)
|
|
|
|
return port;
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
int addr = mv88e6xxx_port_to_phy_addr(ds, port);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (addr < 0)
|
|
|
|
return addr;
|
|
|
|
|
|
|
|
mutex_lock(&ps->phy_mutex);
|
|
|
|
ret = _mv88e6xxx_phy_read(ds, addr, regnum);
|
|
|
|
mutex_unlock(&ps->phy_mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
int addr = mv88e6xxx_port_to_phy_addr(ds, port);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (addr < 0)
|
|
|
|
return addr;
|
|
|
|
|
|
|
|
mutex_lock(&ps->phy_mutex);
|
|
|
|
ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
|
|
|
|
mutex_unlock(&ps->phy_mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
int addr = mv88e6xxx_port_to_phy_addr(ds, port);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (addr < 0)
|
|
|
|
return addr;
|
|
|
|
|
|
|
|
mutex_lock(&ps->phy_mutex);
|
|
|
|
ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
|
|
|
|
mutex_unlock(&ps->phy_mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
|
|
|
|
u16 val)
|
|
|
|
{
|
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
int addr = mv88e6xxx_port_to_phy_addr(ds, port);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (addr < 0)
|
|
|
|
return addr;
|
|
|
|
|
|
|
|
mutex_lock(&ps->phy_mutex);
|
|
|
|
ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
|
2015-04-02 02:06:35 +00:00
|
|
|
mutex_unlock(&ps->phy_mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-11-25 14:36:19 +00:00
|
|
|
static int __init mv88e6xxx_init(void)
|
|
|
|
{
|
|
|
|
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
|
|
|
|
register_switch_driver(&mv88e6131_switch_driver);
|
|
|
|
#endif
|
|
|
|
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
|
|
|
|
register_switch_driver(&mv88e6123_61_65_switch_driver);
|
2014-09-12 21:58:44 +00:00
|
|
|
#endif
|
2014-10-29 17:44:56 +00:00
|
|
|
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
|
|
|
|
register_switch_driver(&mv88e6352_switch_driver);
|
|
|
|
#endif
|
2014-09-12 21:58:44 +00:00
|
|
|
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
|
|
|
|
register_switch_driver(&mv88e6171_switch_driver);
|
2011-11-25 14:36:19 +00:00
|
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
module_init(mv88e6xxx_init);
|
|
|
|
|
|
|
|
static void __exit mv88e6xxx_cleanup(void)
|
|
|
|
{
|
2014-09-12 21:58:44 +00:00
|
|
|
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
|
|
|
|
unregister_switch_driver(&mv88e6171_switch_driver);
|
|
|
|
#endif
|
2011-11-25 14:36:19 +00:00
|
|
|
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
|
|
|
|
unregister_switch_driver(&mv88e6123_61_65_switch_driver);
|
|
|
|
#endif
|
|
|
|
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
|
|
|
|
unregister_switch_driver(&mv88e6131_switch_driver);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
module_exit(mv88e6xxx_cleanup);
|
2011-11-25 14:37:16 +00:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
|
|
|
|
MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
|
|
|
|
MODULE_LICENSE("GPL");
|