2015-08-12 14:43:39 +00:00
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <linux/circ_buf.h>
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#include "i915_drv.h"
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2016-11-25 17:59:33 +00:00
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#include "intel_uc.h"
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2015-08-12 14:43:39 +00:00
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2015-08-12 14:43:41 +00:00
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/**
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2015-10-19 23:10:54 +00:00
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* DOC: GuC-based command submission
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2015-08-12 14:43:41 +00:00
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*
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* i915_guc_client:
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* We use the term client to avoid confusion with contexts. A i915_guc_client is
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* equivalent to GuC object guc_context_desc. This context descriptor is
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* allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
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* and workqueue for it. Also the process descriptor (guc_process_desc), which
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* is mapped to client space. So the client can write Work Item then ring the
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* doorbell.
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*
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* To simplify the implementation, we allocate one gem object that contains all
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* pages for doorbell, process descriptor and workqueue.
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*
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* The Scratch registers:
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* There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
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* a value to the action register (SOFT_SCRATCH_0) along with any data. It then
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* triggers an interrupt on the GuC via another register write (0xC4C8).
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* Firmware writes a success/fail code back to the action register after
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* processes the request. The kernel driver polls waiting for this update and
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* then proceeds.
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2016-11-25 17:59:35 +00:00
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* See intel_guc_send()
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2015-08-12 14:43:41 +00:00
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*
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* Doorbells:
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* Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
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* mapped into process space.
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*
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* Work Items:
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* There are several types of work items that the host may place into a
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* workqueue, each with its own requirements and limitations. Currently only
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* WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
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* represents in-order queue. The kernel driver packs ring tail pointer and an
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* ELSP context descriptor dword into Work Item.
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2016-09-12 20:19:37 +00:00
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* See guc_wq_item_append()
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2015-08-12 14:43:41 +00:00
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*
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*/
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/*
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* Tell the GuC to allocate or deallocate a specific doorbell
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*/
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2016-11-25 17:59:34 +00:00
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static int guc_allocate_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client)
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2015-08-12 14:43:41 +00:00
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{
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2016-11-25 17:59:35 +00:00
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u32 action[] = {
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INTEL_GUC_ACTION_ALLOCATE_DOORBELL,
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client->ctx_index
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};
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2015-08-12 14:43:41 +00:00
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2016-11-25 17:59:35 +00:00
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return intel_guc_send(guc, action, ARRAY_SIZE(action));
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2015-08-12 14:43:41 +00:00
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}
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2016-11-25 17:59:34 +00:00
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static int guc_release_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client)
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2015-08-12 14:43:41 +00:00
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{
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2016-11-25 17:59:35 +00:00
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u32 action[] = {
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INTEL_GUC_ACTION_DEALLOCATE_DOORBELL,
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client->ctx_index
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};
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2016-10-12 16:24:41 +00:00
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2016-11-25 17:59:35 +00:00
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return intel_guc_send(guc, action, ARRAY_SIZE(action));
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2016-10-12 16:24:41 +00:00
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}
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2015-08-12 14:43:41 +00:00
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/*
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* Initialise, update, or clear doorbell data shared with the GuC
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*
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* These functions modify shared data and so need access to the mapped
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* client object which contains the page being used for the doorbell
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*/
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2016-06-13 16:57:32 +00:00
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static int guc_update_doorbell_id(struct intel_guc *guc,
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struct i915_guc_client *client,
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u16 new_id)
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2015-08-12 14:43:41 +00:00
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{
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2016-08-15 09:48:51 +00:00
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struct sg_table *sg = guc->ctx_pool_vma->pages;
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2016-06-13 16:57:32 +00:00
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void *doorbell_bitmap = guc->doorbell_bitmap;
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2015-08-12 14:43:41 +00:00
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struct guc_doorbell_info *doorbell;
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2016-06-13 16:57:32 +00:00
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struct guc_context_desc desc;
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size_t len;
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2015-08-12 14:43:41 +00:00
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2016-11-02 17:50:47 +00:00
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doorbell = client->vaddr + client->doorbell_offset;
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2015-08-12 14:43:41 +00:00
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2016-06-13 16:57:32 +00:00
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if (client->doorbell_id != GUC_INVALID_DOORBELL_ID &&
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test_bit(client->doorbell_id, doorbell_bitmap)) {
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/* Deactivate the old doorbell */
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doorbell->db_status = GUC_DOORBELL_DISABLED;
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2016-11-25 17:59:34 +00:00
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(void)guc_release_doorbell(guc, client);
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2016-06-13 16:57:32 +00:00
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__clear_bit(client->doorbell_id, doorbell_bitmap);
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}
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/* Update the GuC's idea of the doorbell ID */
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len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
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sizeof(desc) * client->ctx_index);
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if (len != sizeof(desc))
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return -EFAULT;
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desc.db_id = new_id;
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len = sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
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sizeof(desc) * client->ctx_index);
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if (len != sizeof(desc))
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return -EFAULT;
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client->doorbell_id = new_id;
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if (new_id == GUC_INVALID_DOORBELL_ID)
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return 0;
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/* Activate the new doorbell */
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__set_bit(new_id, doorbell_bitmap);
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doorbell->db_status = GUC_DOORBELL_ENABLED;
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2016-11-29 12:10:22 +00:00
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doorbell->cookie = client->doorbell_cookie;
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2016-11-25 17:59:34 +00:00
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return guc_allocate_doorbell(guc, client);
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2016-06-13 16:57:32 +00:00
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}
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2015-08-12 14:43:41 +00:00
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static void guc_disable_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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2016-06-13 16:57:32 +00:00
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(void)guc_update_doorbell_id(guc, client, GUC_INVALID_DOORBELL_ID);
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2015-08-12 14:43:41 +00:00
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/* XXX: wait for any interrupts */
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/* XXX: wait for workqueue to drain */
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}
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2016-06-13 16:57:33 +00:00
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static uint16_t
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select_doorbell_register(struct intel_guc *guc, uint32_t priority)
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{
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/*
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* The bitmap tracks which doorbell registers are currently in use.
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* It is split into two halves; the first half is used for normal
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* priority contexts, the second half for high-priority ones.
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* Note that logically higher priorities are numerically less than
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* normal ones, so the test below means "is it high-priority?"
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*/
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const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH);
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const uint16_t half = GUC_MAX_DOORBELLS / 2;
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const uint16_t start = hi_pri ? half : 0;
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const uint16_t end = start + half;
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uint16_t id;
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id = find_next_zero_bit(guc->doorbell_bitmap, end, start);
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if (id == end)
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id = GUC_INVALID_DOORBELL_ID;
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DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
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hi_pri ? "high" : "normal", id);
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return id;
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}
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2015-08-12 14:43:41 +00:00
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/*
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* Select, assign and relase doorbell cachelines
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*
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* These functions track which doorbell cachelines are in use.
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2016-11-25 17:59:35 +00:00
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* The data they manipulate is protected by the intel_guc_send lock.
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2015-08-12 14:43:41 +00:00
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*/
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static uint32_t select_doorbell_cacheline(struct intel_guc *guc)
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{
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const uint32_t cacheline_size = cache_line_size();
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uint32_t offset;
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/* Doorbell uses a single cache line within a page */
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offset = offset_in_page(guc->db_cacheline);
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/* Moving to next cache line to reduce contention */
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guc->db_cacheline += cacheline_size;
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DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
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offset, guc->db_cacheline, cacheline_size);
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return offset;
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}
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/*
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* Initialise the process descriptor shared with the GuC firmware.
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*/
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2016-09-12 20:19:37 +00:00
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static void guc_proc_desc_init(struct intel_guc *guc,
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2015-08-12 14:43:41 +00:00
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struct i915_guc_client *client)
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{
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struct guc_process_desc *desc;
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2016-11-02 17:50:47 +00:00
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desc = client->vaddr + client->proc_desc_offset;
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2015-08-12 14:43:41 +00:00
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memset(desc, 0, sizeof(*desc));
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/*
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* XXX: pDoorbell and WQVBaseAddress are pointers in process address
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* space for ring3 clients (set them as in mmap_ioctl) or kernel
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* space for kernel clients (map on demand instead? May make debug
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* easier to have it mapped).
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*/
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desc->wq_base_addr = 0;
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desc->db_base_addr = 0;
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desc->context_id = client->ctx_index;
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desc->wq_size_bytes = client->wq_size;
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desc->wq_status = WQ_STATUS_ACTIVE;
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desc->priority = client->priority;
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}
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/*
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* Initialise/clear the context descriptor shared with the GuC firmware.
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*
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* This descriptor tells the GuC where (in GGTT space) to find the important
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* data structures relating to this client (doorbell, process descriptor,
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* write queue, etc).
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*/
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2016-09-12 20:19:37 +00:00
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static void guc_ctx_desc_init(struct intel_guc *guc,
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2015-08-12 14:43:41 +00:00
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struct i915_guc_client *client)
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{
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2016-01-23 19:58:14 +00:00
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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2016-03-16 11:00:36 +00:00
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struct intel_engine_cs *engine;
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2016-05-24 13:53:34 +00:00
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struct i915_gem_context *ctx = client->owner;
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2015-08-12 14:43:41 +00:00
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struct guc_context_desc desc;
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struct sg_table *sg;
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2016-08-27 07:54:01 +00:00
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unsigned int tmp;
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2016-04-19 15:08:36 +00:00
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u32 gfx_addr;
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2015-08-12 14:43:41 +00:00
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memset(&desc, 0, sizeof(desc));
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desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
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desc.context_id = client->ctx_index;
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desc.priority = client->priority;
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desc.db_id = client->doorbell_id;
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2016-08-27 07:54:01 +00:00
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for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
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2016-05-24 13:53:37 +00:00
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struct intel_context *ce = &ctx->engine[engine->id];
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2016-08-09 14:19:22 +00:00
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uint32_t guc_engine_id = engine->guc_id;
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struct guc_execlist_context *lrc = &desc.lrc[guc_engine_id];
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drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 14:43:43 +00:00
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/* TODO: We have a design issue to be solved here. Only when we
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* receive the first batch, we know which engine is used by the
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* user. But here GuC expects the lrc and ring to be pinned. It
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* is not an issue for default context, which is the only one
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* for now who owns a GuC client. But for future owner of GuC
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* client, need to make sure lrc is pinned prior to enter here.
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*/
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2016-05-24 13:53:37 +00:00
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if (!ce->state)
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drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 14:43:43 +00:00
|
|
|
break; /* XXX: continue? */
|
|
|
|
|
2016-05-24 13:53:37 +00:00
|
|
|
lrc->context_desc = lower_32_bits(ce->lrc_desc);
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 14:43:43 +00:00
|
|
|
|
|
|
|
/* The state page is after PPHWSP */
|
2016-08-15 09:48:57 +00:00
|
|
|
lrc->ring_lcra =
|
2016-12-24 19:31:46 +00:00
|
|
|
guc_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 14:43:43 +00:00
|
|
|
lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
|
2016-08-09 14:19:22 +00:00
|
|
|
(guc_engine_id << GUC_ELC_ENGINE_OFFSET);
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 14:43:43 +00:00
|
|
|
|
2016-12-24 19:31:46 +00:00
|
|
|
lrc->ring_begin = guc_ggtt_offset(ce->ring->vma);
|
2016-08-15 09:48:57 +00:00
|
|
|
lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
|
|
|
|
lrc->ring_next_free_location = lrc->ring_begin;
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 14:43:43 +00:00
|
|
|
lrc->ring_current_tail_pointer_value = 0;
|
|
|
|
|
2016-08-09 14:19:22 +00:00
|
|
|
desc.engines_used |= (1 << guc_engine_id);
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 14:43:43 +00:00
|
|
|
}
|
|
|
|
|
2016-08-09 14:19:21 +00:00
|
|
|
DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
|
|
|
|
client->engines, desc.engines_used);
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 14:43:43 +00:00
|
|
|
WARN_ON(desc.engines_used == 0);
|
|
|
|
|
2015-08-12 14:43:41 +00:00
|
|
|
/*
|
2016-04-19 15:08:36 +00:00
|
|
|
* The doorbell, process descriptor, and workqueue are all parts
|
|
|
|
* of the client object, which the GuC will reference via the GGTT
|
2015-08-12 14:43:41 +00:00
|
|
|
*/
|
2016-12-24 19:31:46 +00:00
|
|
|
gfx_addr = guc_ggtt_offset(client->vma);
|
2016-08-15 09:48:51 +00:00
|
|
|
desc.db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
|
2016-04-19 15:08:36 +00:00
|
|
|
client->doorbell_offset;
|
2016-11-02 17:50:47 +00:00
|
|
|
desc.db_trigger_cpu =
|
|
|
|
(uintptr_t)client->vaddr + client->doorbell_offset;
|
2016-04-19 15:08:36 +00:00
|
|
|
desc.db_trigger_uk = gfx_addr + client->doorbell_offset;
|
|
|
|
desc.process_desc = gfx_addr + client->proc_desc_offset;
|
|
|
|
desc.wq_addr = gfx_addr + client->wq_offset;
|
2015-08-12 14:43:41 +00:00
|
|
|
desc.wq_size = client->wq_size;
|
|
|
|
|
|
|
|
/*
|
2016-05-24 13:53:34 +00:00
|
|
|
* XXX: Take LRCs from an existing context if this is not an
|
2015-08-12 14:43:41 +00:00
|
|
|
* IsKMDCreatedContext client
|
|
|
|
*/
|
|
|
|
desc.desc_private = (uintptr_t)client;
|
|
|
|
|
|
|
|
/* Pool context is pinned already */
|
2016-08-15 09:48:51 +00:00
|
|
|
sg = guc->ctx_pool_vma->pages;
|
2015-08-12 14:43:41 +00:00
|
|
|
sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
|
|
|
|
sizeof(desc) * client->ctx_index);
|
|
|
|
}
|
|
|
|
|
2016-09-12 20:19:37 +00:00
|
|
|
static void guc_ctx_desc_fini(struct intel_guc *guc,
|
2015-08-12 14:43:41 +00:00
|
|
|
struct i915_guc_client *client)
|
|
|
|
{
|
|
|
|
struct guc_context_desc desc;
|
|
|
|
struct sg_table *sg;
|
|
|
|
|
|
|
|
memset(&desc, 0, sizeof(desc));
|
|
|
|
|
2016-08-15 09:48:51 +00:00
|
|
|
sg = guc->ctx_pool_vma->pages;
|
2015-08-12 14:43:41 +00:00
|
|
|
sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
|
|
|
|
sizeof(desc) * client->ctx_index);
|
|
|
|
}
|
|
|
|
|
2016-05-13 14:36:32 +00:00
|
|
|
/**
|
2016-09-12 20:19:37 +00:00
|
|
|
* i915_guc_wq_reserve() - reserve space in the GuC's workqueue
|
2016-05-13 14:36:32 +00:00
|
|
|
* @request: request associated with the commands
|
|
|
|
*
|
|
|
|
* Return: 0 if space is available
|
|
|
|
* -EAGAIN if space is not currently available
|
|
|
|
*
|
|
|
|
* This function must be called (and must return 0) before a request
|
|
|
|
* is submitted to the GuC via i915_guc_submit() below. Once a result
|
2016-09-12 20:19:37 +00:00
|
|
|
* of 0 has been returned, it must be balanced by a corresponding
|
|
|
|
* call to submit().
|
2016-05-13 14:36:32 +00:00
|
|
|
*
|
2016-09-12 20:19:37 +00:00
|
|
|
* Reservation allows the caller to determine in advance that space
|
2016-05-13 14:36:32 +00:00
|
|
|
* will be available for the next submission before committing resources
|
|
|
|
* to it, and helps avoid late failures with complicated recovery paths.
|
|
|
|
*/
|
2016-09-12 20:19:37 +00:00
|
|
|
int i915_guc_wq_reserve(struct drm_i915_gem_request *request)
|
2015-08-12 14:43:41 +00:00
|
|
|
{
|
2016-05-13 14:36:33 +00:00
|
|
|
const size_t wqi_size = sizeof(struct guc_wq_item);
|
2016-12-15 19:53:21 +00:00
|
|
|
struct i915_guc_client *client = request->i915->guc.execbuf_client;
|
|
|
|
struct guc_process_desc *desc = client->vaddr +
|
|
|
|
client->proc_desc_offset;
|
2016-05-13 14:36:33 +00:00
|
|
|
u32 freespace;
|
2016-09-09 13:11:57 +00:00
|
|
|
int ret;
|
2015-08-12 14:43:41 +00:00
|
|
|
|
2016-12-15 19:53:21 +00:00
|
|
|
spin_lock(&client->wq_lock);
|
|
|
|
freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
|
|
|
|
freespace -= client->wq_rsvd;
|
2016-09-09 13:11:57 +00:00
|
|
|
if (likely(freespace >= wqi_size)) {
|
2016-12-15 19:53:21 +00:00
|
|
|
client->wq_rsvd += wqi_size;
|
2016-09-09 13:11:57 +00:00
|
|
|
ret = 0;
|
|
|
|
} else {
|
2016-12-15 19:53:21 +00:00
|
|
|
client->no_wq_space++;
|
2016-09-09 13:11:57 +00:00
|
|
|
ret = -EAGAIN;
|
|
|
|
}
|
2016-12-15 19:53:21 +00:00
|
|
|
spin_unlock(&client->wq_lock);
|
2015-08-12 14:43:41 +00:00
|
|
|
|
2016-09-09 13:11:57 +00:00
|
|
|
return ret;
|
2015-08-12 14:43:41 +00:00
|
|
|
}
|
|
|
|
|
2016-10-07 06:53:27 +00:00
|
|
|
void i915_guc_wq_unreserve(struct drm_i915_gem_request *request)
|
|
|
|
{
|
|
|
|
const size_t wqi_size = sizeof(struct guc_wq_item);
|
2016-12-15 19:53:21 +00:00
|
|
|
struct i915_guc_client *client = request->i915->guc.execbuf_client;
|
2016-10-07 06:53:27 +00:00
|
|
|
|
2016-12-15 19:53:21 +00:00
|
|
|
GEM_BUG_ON(READ_ONCE(client->wq_rsvd) < wqi_size);
|
2016-10-07 06:53:27 +00:00
|
|
|
|
2016-12-15 19:53:21 +00:00
|
|
|
spin_lock(&client->wq_lock);
|
|
|
|
client->wq_rsvd -= wqi_size;
|
|
|
|
spin_unlock(&client->wq_lock);
|
2016-10-07 06:53:27 +00:00
|
|
|
}
|
|
|
|
|
2016-09-12 20:19:37 +00:00
|
|
|
/* Construct a Work Item and append it to the GuC's Work Queue */
|
2016-12-15 19:53:21 +00:00
|
|
|
static void guc_wq_item_append(struct i915_guc_client *client,
|
2016-09-12 20:19:37 +00:00
|
|
|
struct drm_i915_gem_request *rq)
|
2015-08-12 14:43:41 +00:00
|
|
|
{
|
2016-05-13 14:36:34 +00:00
|
|
|
/* wqi_len is in DWords, and does not include the one-word header */
|
|
|
|
const size_t wqi_size = sizeof(struct guc_wq_item);
|
|
|
|
const u32 wqi_len = wqi_size/sizeof(u32) - 1;
|
2016-08-09 14:19:22 +00:00
|
|
|
struct intel_engine_cs *engine = rq->engine;
|
2016-04-19 15:08:35 +00:00
|
|
|
struct guc_process_desc *desc;
|
2015-08-12 14:43:41 +00:00
|
|
|
struct guc_wq_item *wqi;
|
2016-11-02 17:50:47 +00:00
|
|
|
u32 freespace, tail, wq_off;
|
2015-12-16 19:45:55 +00:00
|
|
|
|
2016-12-15 19:53:21 +00:00
|
|
|
desc = client->vaddr + client->proc_desc_offset;
|
2015-08-12 14:43:41 +00:00
|
|
|
|
2016-09-12 20:19:37 +00:00
|
|
|
/* Free space is guaranteed, see i915_guc_wq_reserve() above */
|
2016-12-15 19:53:21 +00:00
|
|
|
freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
|
2016-05-13 14:36:34 +00:00
|
|
|
GEM_BUG_ON(freespace < wqi_size);
|
|
|
|
|
|
|
|
/* The GuC firmware wants the tail index in QWords, not bytes */
|
|
|
|
tail = rq->tail;
|
|
|
|
GEM_BUG_ON(tail & 7);
|
|
|
|
tail >>= 3;
|
|
|
|
GEM_BUG_ON(tail > WQ_RING_TAIL_MAX);
|
2015-08-12 14:43:41 +00:00
|
|
|
|
|
|
|
/* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
|
|
|
|
* should not have the case where structure wqi is across page, neither
|
|
|
|
* wrapped to the beginning. This simplifies the implementation below.
|
|
|
|
*
|
|
|
|
* XXX: if not the case, we need save data to a temp wqi and copy it to
|
|
|
|
* workqueue buffer dw by dw.
|
|
|
|
*/
|
2016-05-13 14:36:34 +00:00
|
|
|
BUILD_BUG_ON(wqi_size != 16);
|
2016-12-15 19:53:21 +00:00
|
|
|
GEM_BUG_ON(client->wq_rsvd < wqi_size);
|
2015-08-12 14:43:41 +00:00
|
|
|
|
2016-05-13 14:36:34 +00:00
|
|
|
/* postincrement WQ tail for next time */
|
2016-12-15 19:53:21 +00:00
|
|
|
wq_off = client->wq_tail;
|
2016-09-09 13:11:57 +00:00
|
|
|
GEM_BUG_ON(wq_off & (wqi_size - 1));
|
2016-12-15 19:53:21 +00:00
|
|
|
client->wq_tail += wqi_size;
|
|
|
|
client->wq_tail &= client->wq_size - 1;
|
|
|
|
client->wq_rsvd -= wqi_size;
|
2016-05-13 14:36:34 +00:00
|
|
|
|
|
|
|
/* WQ starts from the page after doorbell / process_desc */
|
2016-12-15 19:53:21 +00:00
|
|
|
wqi = client->vaddr + wq_off + GUC_DB_SIZE;
|
2015-08-12 14:43:41 +00:00
|
|
|
|
2016-05-13 14:36:34 +00:00
|
|
|
/* Now fill in the 4-word work queue item */
|
2015-08-12 14:43:41 +00:00
|
|
|
wqi->header = WQ_TYPE_INORDER |
|
2016-05-13 14:36:34 +00:00
|
|
|
(wqi_len << WQ_LEN_SHIFT) |
|
2016-08-09 14:19:22 +00:00
|
|
|
(engine->guc_id << WQ_TARGET_SHIFT) |
|
2015-08-12 14:43:41 +00:00
|
|
|
WQ_NO_WCFLUSH_WAIT;
|
|
|
|
|
|
|
|
/* The GuC wants only the low-order word of the context descriptor */
|
2016-08-09 14:19:22 +00:00
|
|
|
wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine);
|
2015-08-12 14:43:41 +00:00
|
|
|
|
|
|
|
wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT;
|
2016-10-28 12:58:49 +00:00
|
|
|
wqi->fence_id = rq->global_seqno;
|
2015-08-12 14:43:41 +00:00
|
|
|
}
|
|
|
|
|
2016-12-15 19:53:21 +00:00
|
|
|
static int guc_ring_doorbell(struct i915_guc_client *client)
|
2016-06-13 16:57:31 +00:00
|
|
|
{
|
|
|
|
struct guc_process_desc *desc;
|
|
|
|
union guc_doorbell_qw db_cmp, db_exc, db_ret;
|
|
|
|
union guc_doorbell_qw *db;
|
|
|
|
int attempt = 2, ret = -EAGAIN;
|
|
|
|
|
2016-12-15 19:53:21 +00:00
|
|
|
desc = client->vaddr + client->proc_desc_offset;
|
2016-06-13 16:57:31 +00:00
|
|
|
|
|
|
|
/* Update the tail so it is visible to GuC */
|
2016-12-15 19:53:21 +00:00
|
|
|
desc->tail = client->wq_tail;
|
2016-06-13 16:57:31 +00:00
|
|
|
|
|
|
|
/* current cookie */
|
|
|
|
db_cmp.db_status = GUC_DOORBELL_ENABLED;
|
2016-12-15 19:53:21 +00:00
|
|
|
db_cmp.cookie = client->doorbell_cookie;
|
2016-06-13 16:57:31 +00:00
|
|
|
|
|
|
|
/* cookie to be updated */
|
|
|
|
db_exc.db_status = GUC_DOORBELL_ENABLED;
|
2016-12-15 19:53:21 +00:00
|
|
|
db_exc.cookie = client->doorbell_cookie + 1;
|
2016-06-13 16:57:31 +00:00
|
|
|
if (db_exc.cookie == 0)
|
|
|
|
db_exc.cookie = 1;
|
|
|
|
|
|
|
|
/* pointer of current doorbell cacheline */
|
2016-12-15 19:53:21 +00:00
|
|
|
db = client->vaddr + client->doorbell_offset;
|
2016-06-13 16:57:31 +00:00
|
|
|
|
|
|
|
while (attempt--) {
|
|
|
|
/* lets ring the doorbell */
|
|
|
|
db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db,
|
|
|
|
db_cmp.value_qw, db_exc.value_qw);
|
|
|
|
|
|
|
|
/* if the exchange was successfully executed */
|
|
|
|
if (db_ret.value_qw == db_cmp.value_qw) {
|
|
|
|
/* db was successfully rung */
|
2016-12-15 19:53:21 +00:00
|
|
|
client->doorbell_cookie = db_exc.cookie;
|
2016-06-13 16:57:31 +00:00
|
|
|
ret = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* XXX: doorbell was lost and need to acquire it again */
|
|
|
|
if (db_ret.db_status == GUC_DOORBELL_DISABLED)
|
|
|
|
break;
|
|
|
|
|
2016-08-18 17:17:23 +00:00
|
|
|
DRM_WARN("Cookie mismatch. Expected %d, found %d\n",
|
|
|
|
db_cmp.cookie, db_ret.cookie);
|
2016-06-13 16:57:31 +00:00
|
|
|
|
|
|
|
/* update the cookie to newly read cookie from GuC */
|
|
|
|
db_cmp.cookie = db_ret.cookie;
|
|
|
|
db_exc.cookie = db_ret.cookie + 1;
|
|
|
|
if (db_exc.cookie == 0)
|
|
|
|
db_exc.cookie = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-08-12 14:43:41 +00:00
|
|
|
/**
|
drm/i915/guc: Split hw submission for replay after GPU reset
Something I missed before sending off the partial series was that the
non-scheduler guc reset path was broken (in the full series, this is
pushed to the execlists reset handler). The issue is that after a reset,
we have to refill the GuC workqueues, which we do by resubmitting the
requests. However, if we already have submitted them, the fences within
them have already been used and triggering them again is an error.
Instead, just repopulate the guc workqueue.
[ 115.858560] [IGT] gem_busy: starting subtest hang-render
[ 135.839867] [drm] GPU HANG: ecode 9:0:0xe757fefe, in gem_busy [1716], reason: Hang on render ring, action: reset
[ 135.839902] drm/i915: Resetting chip after gpu hang
[ 135.839957] [drm] RC6 on
[ 135.858351] ------------[ cut here ]------------
[ 135.858357] WARNING: CPU: 2 PID: 45 at drivers/gpu/drm/i915/i915_sw_fence.c:108 i915_sw_fence_complete+0x25/0x30
[ 135.858357] Modules linked in: rfcomm bnep binfmt_misc nls_iso8859_1 input_leds snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hda_core btusb btrtl snd_hwdep snd_pcm 8250_dw snd_seq_midi hid_lenovo snd_seq_midi_event snd_rawmidi iwlwifi x86_pkg_temp_thermal coretemp snd_seq crct10dif_pclmul snd_seq_device hci_uart snd_timer crc32_pclmul ghash_clmulni_intel idma64 aesni_intel virt_dma btbcm snd btqca aes_x86_64 btintel lrw cfg80211 bluetooth gf128mul glue_helper ablk_helper cryptd soundcore intel_lpss_pci intel_pch_thermal intel_lpss_acpi intel_lpss acpi_als mfd_core kfifo_buf acpi_pad industrialio autofs4 hid_plantronics usbhid dm_mirror dm_region_hash dm_log sdhci_pci ahci sdhci libahci i2c_hid hid
[ 135.858389] CPU: 2 PID: 45 Comm: kworker/2:1 Tainted: G W 4.9.0-rc4+ #238
[ 135.858389] Hardware name: /NUC6i3SYB, BIOS SYSKLi35.86A.0024.2015.1027.2142 10/27/2015
[ 135.858392] Workqueue: events_long i915_hangcheck_elapsed
[ 135.858394] ffffc900001bf9b8 ffffffff812bb238 0000000000000000 0000000000000000
[ 135.858396] ffffc900001bf9f8 ffffffff8104f621 0000006c00000000 ffff8808296137f8
[ 135.858398] 0000000000000a00 ffff8808457a0000 ffff880845764e60 ffff880845760000
[ 135.858399] Call Trace:
[ 135.858403] [<ffffffff812bb238>] dump_stack+0x4d/0x65
[ 135.858405] [<ffffffff8104f621>] __warn+0xc1/0xe0
[ 135.858406] [<ffffffff8104f748>] warn_slowpath_null+0x18/0x20
[ 135.858408] [<ffffffff813f8c15>] i915_sw_fence_complete+0x25/0x30
[ 135.858410] [<ffffffff813f8fad>] i915_sw_fence_commit+0xd/0x30
[ 135.858412] [<ffffffff8142e591>] __i915_gem_request_submit+0xe1/0xf0
[ 135.858413] [<ffffffff8142e5c8>] i915_gem_request_submit+0x28/0x40
[ 135.858415] [<ffffffff814433e7>] i915_guc_submit+0x47/0x210
[ 135.858417] [<ffffffff81443e98>] i915_guc_submission_enable+0x468/0x540
[ 135.858419] [<ffffffff81442495>] intel_guc_setup+0x715/0x810
[ 135.858421] [<ffffffff8142b6b4>] i915_gem_init_hw+0x114/0x2a0
[ 135.858423] [<ffffffff813eeaa8>] i915_reset+0xe8/0x120
[ 135.858424] [<ffffffff813f3937>] i915_reset_and_wakeup+0x157/0x180
[ 135.858426] [<ffffffff813f79db>] i915_handle_error+0x1ab/0x230
[ 135.858428] [<ffffffff812c760d>] ? scnprintf+0x4d/0x90
[ 135.858430] [<ffffffff81435985>] i915_hangcheck_elapsed+0x275/0x3d0
[ 135.858432] [<ffffffff810668cf>] process_one_work+0x12f/0x410
[ 135.858433] [<ffffffff81066bf3>] worker_thread+0x43/0x4d0
[ 135.858435] [<ffffffff81066bb0>] ? process_one_work+0x410/0x410
[ 135.858436] [<ffffffff81066bb0>] ? process_one_work+0x410/0x410
[ 135.858438] [<ffffffff8106bbb4>] kthread+0xd4/0xf0
[ 135.858440] [<ffffffff8106bae0>] ? kthread_park+0x60/0x60
v2: Only resubmit submitted requests
v3: Don't forget the pending requests have reserved space.
Fixes: d55ac5bf97c6 ("drm/i915: Defer transfer onto execution timeline to actual hw submission")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161129121024.22650-6-chris@chris-wilson.co.uk
2016-11-29 12:10:24 +00:00
|
|
|
* __i915_guc_submit() - Submit commands through GuC
|
2015-10-19 23:10:54 +00:00
|
|
|
* @rq: request associated with the commands
|
2015-08-12 14:43:41 +00:00
|
|
|
*
|
2016-09-12 20:19:37 +00:00
|
|
|
* The caller must have already called i915_guc_wq_reserve() above with
|
|
|
|
* a result of 0 (success), guaranteeing that there is space in the work
|
|
|
|
* queue for the new request, so enqueuing the item cannot fail.
|
2016-05-13 14:36:32 +00:00
|
|
|
*
|
|
|
|
* Bad Things Will Happen if the caller violates this protocol e.g. calls
|
2016-09-12 20:19:37 +00:00
|
|
|
* submit() when _reserve() says there's no space, or calls _submit()
|
|
|
|
* a different number of times from (successful) calls to _reserve().
|
2016-05-13 14:36:32 +00:00
|
|
|
*
|
|
|
|
* The only error here arises if the doorbell hardware isn't functioning
|
|
|
|
* as expected, which really shouln't happen.
|
2015-08-12 14:43:41 +00:00
|
|
|
*/
|
drm/i915/guc: Split hw submission for replay after GPU reset
Something I missed before sending off the partial series was that the
non-scheduler guc reset path was broken (in the full series, this is
pushed to the execlists reset handler). The issue is that after a reset,
we have to refill the GuC workqueues, which we do by resubmitting the
requests. However, if we already have submitted them, the fences within
them have already been used and triggering them again is an error.
Instead, just repopulate the guc workqueue.
[ 115.858560] [IGT] gem_busy: starting subtest hang-render
[ 135.839867] [drm] GPU HANG: ecode 9:0:0xe757fefe, in gem_busy [1716], reason: Hang on render ring, action: reset
[ 135.839902] drm/i915: Resetting chip after gpu hang
[ 135.839957] [drm] RC6 on
[ 135.858351] ------------[ cut here ]------------
[ 135.858357] WARNING: CPU: 2 PID: 45 at drivers/gpu/drm/i915/i915_sw_fence.c:108 i915_sw_fence_complete+0x25/0x30
[ 135.858357] Modules linked in: rfcomm bnep binfmt_misc nls_iso8859_1 input_leds snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hda_core btusb btrtl snd_hwdep snd_pcm 8250_dw snd_seq_midi hid_lenovo snd_seq_midi_event snd_rawmidi iwlwifi x86_pkg_temp_thermal coretemp snd_seq crct10dif_pclmul snd_seq_device hci_uart snd_timer crc32_pclmul ghash_clmulni_intel idma64 aesni_intel virt_dma btbcm snd btqca aes_x86_64 btintel lrw cfg80211 bluetooth gf128mul glue_helper ablk_helper cryptd soundcore intel_lpss_pci intel_pch_thermal intel_lpss_acpi intel_lpss acpi_als mfd_core kfifo_buf acpi_pad industrialio autofs4 hid_plantronics usbhid dm_mirror dm_region_hash dm_log sdhci_pci ahci sdhci libahci i2c_hid hid
[ 135.858389] CPU: 2 PID: 45 Comm: kworker/2:1 Tainted: G W 4.9.0-rc4+ #238
[ 135.858389] Hardware name: /NUC6i3SYB, BIOS SYSKLi35.86A.0024.2015.1027.2142 10/27/2015
[ 135.858392] Workqueue: events_long i915_hangcheck_elapsed
[ 135.858394] ffffc900001bf9b8 ffffffff812bb238 0000000000000000 0000000000000000
[ 135.858396] ffffc900001bf9f8 ffffffff8104f621 0000006c00000000 ffff8808296137f8
[ 135.858398] 0000000000000a00 ffff8808457a0000 ffff880845764e60 ffff880845760000
[ 135.858399] Call Trace:
[ 135.858403] [<ffffffff812bb238>] dump_stack+0x4d/0x65
[ 135.858405] [<ffffffff8104f621>] __warn+0xc1/0xe0
[ 135.858406] [<ffffffff8104f748>] warn_slowpath_null+0x18/0x20
[ 135.858408] [<ffffffff813f8c15>] i915_sw_fence_complete+0x25/0x30
[ 135.858410] [<ffffffff813f8fad>] i915_sw_fence_commit+0xd/0x30
[ 135.858412] [<ffffffff8142e591>] __i915_gem_request_submit+0xe1/0xf0
[ 135.858413] [<ffffffff8142e5c8>] i915_gem_request_submit+0x28/0x40
[ 135.858415] [<ffffffff814433e7>] i915_guc_submit+0x47/0x210
[ 135.858417] [<ffffffff81443e98>] i915_guc_submission_enable+0x468/0x540
[ 135.858419] [<ffffffff81442495>] intel_guc_setup+0x715/0x810
[ 135.858421] [<ffffffff8142b6b4>] i915_gem_init_hw+0x114/0x2a0
[ 135.858423] [<ffffffff813eeaa8>] i915_reset+0xe8/0x120
[ 135.858424] [<ffffffff813f3937>] i915_reset_and_wakeup+0x157/0x180
[ 135.858426] [<ffffffff813f79db>] i915_handle_error+0x1ab/0x230
[ 135.858428] [<ffffffff812c760d>] ? scnprintf+0x4d/0x90
[ 135.858430] [<ffffffff81435985>] i915_hangcheck_elapsed+0x275/0x3d0
[ 135.858432] [<ffffffff810668cf>] process_one_work+0x12f/0x410
[ 135.858433] [<ffffffff81066bf3>] worker_thread+0x43/0x4d0
[ 135.858435] [<ffffffff81066bb0>] ? process_one_work+0x410/0x410
[ 135.858436] [<ffffffff81066bb0>] ? process_one_work+0x410/0x410
[ 135.858438] [<ffffffff8106bbb4>] kthread+0xd4/0xf0
[ 135.858440] [<ffffffff8106bae0>] ? kthread_park+0x60/0x60
v2: Only resubmit submitted requests
v3: Don't forget the pending requests have reserved space.
Fixes: d55ac5bf97c6 ("drm/i915: Defer transfer onto execution timeline to actual hw submission")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161129121024.22650-6-chris@chris-wilson.co.uk
2016-11-29 12:10:24 +00:00
|
|
|
static void __i915_guc_submit(struct drm_i915_gem_request *rq)
|
2015-08-12 14:43:41 +00:00
|
|
|
{
|
drm/i915/guc: WA to address the Ringbuffer coherency issue
Driver accesses the ringbuffer pages, via GMADR BAR, if the pages are
pinned in mappable aperture portion of GGTT and for ringbuffer pages
allocated from Stolen memory, access can only be done through GMADR BAR.
In case of GuC based submission, updates done in ringbuffer via GMADR
may not get committed to memory by the time the Command streamer starts
reading them, resulting in fetching of stale data.
For Host based submission, such problem is not there as the write to Ring
Tail or ELSP register happens from the Host side prior to submission.
Access to any GFX register from CPU side goes to GTTMMADR BAR and Hw already
enforces the ordering between outstanding GMADR writes & new GTTMADR access.
MMIO writes from GuC side do not go to GTTMMADR BAR as GuC communication to
registers within GT is contained within GT, so ordering is not enforced
resulting in a race, which can manifest in form of a hang.
To ensure the flush of in-flight GMADR writes, a POSTING READ is done to
GuC register prior to doorbell ring.
There is already a similar WA in i915_gem_object_flush_gtt_write_domain(),
which takes care of GMADR writes from User space to GEM buffers, but not the
ringbuffer writes from KMD.
This WA is needed on all recent HW.
v2:
- Use POSTING_READ_FW instead of POSTING_READ as GuC register do not lie
in any forcewake domain range and so the overhead of spinlock & search
in the forcewake table is avoidable. (Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1477413323-1880-1-git-send-email-akash.goel@intel.com
2016-10-25 16:35:23 +00:00
|
|
|
struct drm_i915_private *dev_priv = rq->i915;
|
2016-11-14 20:40:59 +00:00
|
|
|
struct intel_engine_cs *engine = rq->engine;
|
|
|
|
unsigned int engine_id = engine->id;
|
2016-05-13 14:36:32 +00:00
|
|
|
struct intel_guc *guc = &rq->i915->guc;
|
|
|
|
struct i915_guc_client *client = guc->execbuf_client;
|
2016-05-13 14:36:34 +00:00
|
|
|
int b_ret;
|
2015-08-12 14:43:41 +00:00
|
|
|
|
2016-09-09 13:11:57 +00:00
|
|
|
spin_lock(&client->wq_lock);
|
2016-09-12 20:19:37 +00:00
|
|
|
guc_wq_item_append(client, rq);
|
drm/i915/guc: WA to address the Ringbuffer coherency issue
Driver accesses the ringbuffer pages, via GMADR BAR, if the pages are
pinned in mappable aperture portion of GGTT and for ringbuffer pages
allocated from Stolen memory, access can only be done through GMADR BAR.
In case of GuC based submission, updates done in ringbuffer via GMADR
may not get committed to memory by the time the Command streamer starts
reading them, resulting in fetching of stale data.
For Host based submission, such problem is not there as the write to Ring
Tail or ELSP register happens from the Host side prior to submission.
Access to any GFX register from CPU side goes to GTTMMADR BAR and Hw already
enforces the ordering between outstanding GMADR writes & new GTTMADR access.
MMIO writes from GuC side do not go to GTTMMADR BAR as GuC communication to
registers within GT is contained within GT, so ordering is not enforced
resulting in a race, which can manifest in form of a hang.
To ensure the flush of in-flight GMADR writes, a POSTING READ is done to
GuC register prior to doorbell ring.
There is already a similar WA in i915_gem_object_flush_gtt_write_domain(),
which takes care of GMADR writes from User space to GEM buffers, but not the
ringbuffer writes from KMD.
This WA is needed on all recent HW.
v2:
- Use POSTING_READ_FW instead of POSTING_READ as GuC register do not lie
in any forcewake domain range and so the overhead of spinlock & search
in the forcewake table is avoidable. (Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1477413323-1880-1-git-send-email-akash.goel@intel.com
2016-10-25 16:35:23 +00:00
|
|
|
|
|
|
|
/* WA to flush out the pending GMADR writes to ring buffer. */
|
|
|
|
if (i915_vma_is_map_and_fenceable(rq->ring->vma))
|
|
|
|
POSTING_READ_FW(GUC_STATUS);
|
|
|
|
|
2016-05-13 14:36:34 +00:00
|
|
|
b_ret = guc_ring_doorbell(client);
|
2015-08-12 14:43:41 +00:00
|
|
|
|
2016-01-23 19:58:14 +00:00
|
|
|
client->submissions[engine_id] += 1;
|
2016-05-13 14:36:34 +00:00
|
|
|
client->retcode = b_ret;
|
|
|
|
if (b_ret)
|
2015-08-12 14:43:41 +00:00
|
|
|
client->b_fail += 1;
|
2016-05-13 14:36:34 +00:00
|
|
|
|
2016-01-23 19:58:14 +00:00
|
|
|
guc->submissions[engine_id] += 1;
|
2016-10-28 12:58:49 +00:00
|
|
|
guc->last_seqno[engine_id] = rq->global_seqno;
|
2016-09-09 13:11:57 +00:00
|
|
|
spin_unlock(&client->wq_lock);
|
2015-08-12 14:43:41 +00:00
|
|
|
}
|
|
|
|
|
drm/i915/guc: Split hw submission for replay after GPU reset
Something I missed before sending off the partial series was that the
non-scheduler guc reset path was broken (in the full series, this is
pushed to the execlists reset handler). The issue is that after a reset,
we have to refill the GuC workqueues, which we do by resubmitting the
requests. However, if we already have submitted them, the fences within
them have already been used and triggering them again is an error.
Instead, just repopulate the guc workqueue.
[ 115.858560] [IGT] gem_busy: starting subtest hang-render
[ 135.839867] [drm] GPU HANG: ecode 9:0:0xe757fefe, in gem_busy [1716], reason: Hang on render ring, action: reset
[ 135.839902] drm/i915: Resetting chip after gpu hang
[ 135.839957] [drm] RC6 on
[ 135.858351] ------------[ cut here ]------------
[ 135.858357] WARNING: CPU: 2 PID: 45 at drivers/gpu/drm/i915/i915_sw_fence.c:108 i915_sw_fence_complete+0x25/0x30
[ 135.858357] Modules linked in: rfcomm bnep binfmt_misc nls_iso8859_1 input_leds snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hda_core btusb btrtl snd_hwdep snd_pcm 8250_dw snd_seq_midi hid_lenovo snd_seq_midi_event snd_rawmidi iwlwifi x86_pkg_temp_thermal coretemp snd_seq crct10dif_pclmul snd_seq_device hci_uart snd_timer crc32_pclmul ghash_clmulni_intel idma64 aesni_intel virt_dma btbcm snd btqca aes_x86_64 btintel lrw cfg80211 bluetooth gf128mul glue_helper ablk_helper cryptd soundcore intel_lpss_pci intel_pch_thermal intel_lpss_acpi intel_lpss acpi_als mfd_core kfifo_buf acpi_pad industrialio autofs4 hid_plantronics usbhid dm_mirror dm_region_hash dm_log sdhci_pci ahci sdhci libahci i2c_hid hid
[ 135.858389] CPU: 2 PID: 45 Comm: kworker/2:1 Tainted: G W 4.9.0-rc4+ #238
[ 135.858389] Hardware name: /NUC6i3SYB, BIOS SYSKLi35.86A.0024.2015.1027.2142 10/27/2015
[ 135.858392] Workqueue: events_long i915_hangcheck_elapsed
[ 135.858394] ffffc900001bf9b8 ffffffff812bb238 0000000000000000 0000000000000000
[ 135.858396] ffffc900001bf9f8 ffffffff8104f621 0000006c00000000 ffff8808296137f8
[ 135.858398] 0000000000000a00 ffff8808457a0000 ffff880845764e60 ffff880845760000
[ 135.858399] Call Trace:
[ 135.858403] [<ffffffff812bb238>] dump_stack+0x4d/0x65
[ 135.858405] [<ffffffff8104f621>] __warn+0xc1/0xe0
[ 135.858406] [<ffffffff8104f748>] warn_slowpath_null+0x18/0x20
[ 135.858408] [<ffffffff813f8c15>] i915_sw_fence_complete+0x25/0x30
[ 135.858410] [<ffffffff813f8fad>] i915_sw_fence_commit+0xd/0x30
[ 135.858412] [<ffffffff8142e591>] __i915_gem_request_submit+0xe1/0xf0
[ 135.858413] [<ffffffff8142e5c8>] i915_gem_request_submit+0x28/0x40
[ 135.858415] [<ffffffff814433e7>] i915_guc_submit+0x47/0x210
[ 135.858417] [<ffffffff81443e98>] i915_guc_submission_enable+0x468/0x540
[ 135.858419] [<ffffffff81442495>] intel_guc_setup+0x715/0x810
[ 135.858421] [<ffffffff8142b6b4>] i915_gem_init_hw+0x114/0x2a0
[ 135.858423] [<ffffffff813eeaa8>] i915_reset+0xe8/0x120
[ 135.858424] [<ffffffff813f3937>] i915_reset_and_wakeup+0x157/0x180
[ 135.858426] [<ffffffff813f79db>] i915_handle_error+0x1ab/0x230
[ 135.858428] [<ffffffff812c760d>] ? scnprintf+0x4d/0x90
[ 135.858430] [<ffffffff81435985>] i915_hangcheck_elapsed+0x275/0x3d0
[ 135.858432] [<ffffffff810668cf>] process_one_work+0x12f/0x410
[ 135.858433] [<ffffffff81066bf3>] worker_thread+0x43/0x4d0
[ 135.858435] [<ffffffff81066bb0>] ? process_one_work+0x410/0x410
[ 135.858436] [<ffffffff81066bb0>] ? process_one_work+0x410/0x410
[ 135.858438] [<ffffffff8106bbb4>] kthread+0xd4/0xf0
[ 135.858440] [<ffffffff8106bae0>] ? kthread_park+0x60/0x60
v2: Only resubmit submitted requests
v3: Don't forget the pending requests have reserved space.
Fixes: d55ac5bf97c6 ("drm/i915: Defer transfer onto execution timeline to actual hw submission")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161129121024.22650-6-chris@chris-wilson.co.uk
2016-11-29 12:10:24 +00:00
|
|
|
static void i915_guc_submit(struct drm_i915_gem_request *rq)
|
|
|
|
{
|
|
|
|
i915_gem_request_submit(rq);
|
|
|
|
__i915_guc_submit(rq);
|
|
|
|
}
|
|
|
|
|
2015-08-12 14:43:41 +00:00
|
|
|
/*
|
|
|
|
* Everything below here is concerned with setup & teardown, and is
|
|
|
|
* therefore not part of the somewhat time-critical batch-submission
|
|
|
|
* path of i915_guc_submit() above.
|
|
|
|
*/
|
|
|
|
|
2015-08-12 14:43:39 +00:00
|
|
|
/**
|
2017-01-13 17:41:57 +00:00
|
|
|
* intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
|
2016-08-15 09:48:51 +00:00
|
|
|
* @guc: the guc
|
|
|
|
* @size: size of area to allocate (both virtual space and memory)
|
2015-08-12 14:43:39 +00:00
|
|
|
*
|
2016-08-15 09:48:51 +00:00
|
|
|
* This is a wrapper to create an object for use with the GuC. In order to
|
|
|
|
* use it inside the GuC, an object needs to be pinned lifetime, so we allocate
|
|
|
|
* both some backing storage and a range inside the Global GTT. We must pin
|
|
|
|
* it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
|
|
|
|
* range is reserved inside GuC.
|
2015-08-12 14:43:39 +00:00
|
|
|
*
|
2016-08-15 09:48:51 +00:00
|
|
|
* Return: A i915_vma if successful, otherwise an ERR_PTR.
|
2015-08-12 14:43:39 +00:00
|
|
|
*/
|
2017-01-13 17:41:57 +00:00
|
|
|
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
|
2015-08-12 14:43:39 +00:00
|
|
|
{
|
2016-08-15 09:48:51 +00:00
|
|
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
2015-08-12 14:43:39 +00:00
|
|
|
struct drm_i915_gem_object *obj;
|
2016-08-15 09:48:51 +00:00
|
|
|
struct i915_vma *vma;
|
|
|
|
int ret;
|
2015-08-12 14:43:39 +00:00
|
|
|
|
2016-12-01 14:16:37 +00:00
|
|
|
obj = i915_gem_object_create(dev_priv, size);
|
2016-04-25 12:32:13 +00:00
|
|
|
if (IS_ERR(obj))
|
2016-08-15 09:48:51 +00:00
|
|
|
return ERR_CAST(obj);
|
2015-08-12 14:43:39 +00:00
|
|
|
|
2017-01-16 15:21:30 +00:00
|
|
|
vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
|
2016-08-15 09:48:51 +00:00
|
|
|
if (IS_ERR(vma))
|
|
|
|
goto err;
|
2015-08-12 14:43:39 +00:00
|
|
|
|
2016-08-15 09:48:51 +00:00
|
|
|
ret = i915_vma_pin(vma, 0, PAGE_SIZE,
|
|
|
|
PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
|
|
|
|
if (ret) {
|
|
|
|
vma = ERR_PTR(ret);
|
|
|
|
goto err;
|
2015-08-12 14:43:39 +00:00
|
|
|
}
|
|
|
|
|
2016-08-15 09:48:51 +00:00
|
|
|
return vma;
|
|
|
|
|
|
|
|
err:
|
|
|
|
i915_gem_object_put(obj);
|
|
|
|
return vma;
|
2015-08-12 14:43:39 +00:00
|
|
|
}
|
|
|
|
|
2016-06-10 17:29:25 +00:00
|
|
|
static void
|
|
|
|
guc_client_free(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_guc_client *client)
|
2015-08-12 14:43:41 +00:00
|
|
|
{
|
|
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
|
|
|
|
|
|
if (!client)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* XXX: wait for any outstanding submissions before freeing memory.
|
|
|
|
* Be sure to drop any locks
|
|
|
|
*/
|
|
|
|
|
2016-11-02 17:50:47 +00:00
|
|
|
if (client->vaddr) {
|
2016-04-19 15:08:34 +00:00
|
|
|
/*
|
2016-06-13 16:57:32 +00:00
|
|
|
* If we got as far as setting up a doorbell, make sure we
|
|
|
|
* shut it down before unmapping & deallocating the memory.
|
2016-04-19 15:08:34 +00:00
|
|
|
*/
|
2016-06-13 16:57:32 +00:00
|
|
|
guc_disable_doorbell(guc, client);
|
2016-04-19 15:08:34 +00:00
|
|
|
|
2016-11-02 17:50:47 +00:00
|
|
|
i915_gem_object_unpin_map(client->vma->obj);
|
2016-04-19 15:08:34 +00:00
|
|
|
}
|
|
|
|
|
2016-08-15 09:49:05 +00:00
|
|
|
i915_vma_unpin_and_release(&client->vma);
|
2015-08-12 14:43:41 +00:00
|
|
|
|
|
|
|
if (client->ctx_index != GUC_INVALID_CTX_ID) {
|
2016-09-12 20:19:37 +00:00
|
|
|
guc_ctx_desc_fini(guc, client);
|
2015-08-12 14:43:41 +00:00
|
|
|
ida_simple_remove(&guc->ctx_ids, client->ctx_index);
|
|
|
|
}
|
|
|
|
|
|
|
|
kfree(client);
|
|
|
|
}
|
|
|
|
|
2016-08-09 14:19:20 +00:00
|
|
|
/* Check that a doorbell register is in the expected state */
|
|
|
|
static bool guc_doorbell_check(struct intel_guc *guc, uint16_t db_id)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
|
|
i915_reg_t drbreg = GEN8_DRBREGL(db_id);
|
|
|
|
uint32_t value = I915_READ(drbreg);
|
|
|
|
bool enabled = (value & GUC_DOORBELL_ENABLED) != 0;
|
|
|
|
bool expected = test_bit(db_id, guc->doorbell_bitmap);
|
|
|
|
|
|
|
|
if (enabled == expected)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) 0x%x, should be %s\n",
|
|
|
|
db_id, drbreg.reg, value,
|
|
|
|
expected ? "active" : "inactive");
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
drm/i915/guc: (re)initialise doorbell h/w when enabling GuC submission
During a hibernate/resume cycle, the whole system is reset, including
the GuC and the doorbell hardware. Then the system is booted up, drivers
are loaded, etc -- the GuC firmware may be loaded and set running at
this point. But then, the booted kernel is replaced by the hibernated
image, and this resumed kernel will also try to reload the GuC firmware
(which will fail). To recover, we reset the GuC and try again (which
should work). But this GuC reset doesn't also reset the doorbell
hardware, so it can be left in a state inconsistent with that assumed
by the driver and/or the newly-loaded GuC firmware.
It would be better if the GuC reset also cleared all doorbell state,
but that's not how the hardware currently works; also, the driver cannot
directly reprogram the doorbell hardware (only the GuC can do that).
So this patch cycles through all doorbells, assigning and releasing each
in turn, so that all the doorbell hardware is left in a consistent
state, no matter how it was programmed by the previously-running kernel
and/or GuC firmware.
v2: don't use kmap_atomic() now that client page 0 is kept mapped.
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465837054-16245-2-git-send-email-david.s.gordon@intel.com
2016-06-13 16:57:34 +00:00
|
|
|
/*
|
2016-08-09 14:19:19 +00:00
|
|
|
* Borrow the first client to set up & tear down each unused doorbell
|
drm/i915/guc: (re)initialise doorbell h/w when enabling GuC submission
During a hibernate/resume cycle, the whole system is reset, including
the GuC and the doorbell hardware. Then the system is booted up, drivers
are loaded, etc -- the GuC firmware may be loaded and set running at
this point. But then, the booted kernel is replaced by the hibernated
image, and this resumed kernel will also try to reload the GuC firmware
(which will fail). To recover, we reset the GuC and try again (which
should work). But this GuC reset doesn't also reset the doorbell
hardware, so it can be left in a state inconsistent with that assumed
by the driver and/or the newly-loaded GuC firmware.
It would be better if the GuC reset also cleared all doorbell state,
but that's not how the hardware currently works; also, the driver cannot
directly reprogram the doorbell hardware (only the GuC can do that).
So this patch cycles through all doorbells, assigning and releasing each
in turn, so that all the doorbell hardware is left in a consistent
state, no matter how it was programmed by the previously-running kernel
and/or GuC firmware.
v2: don't use kmap_atomic() now that client page 0 is kept mapped.
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465837054-16245-2-git-send-email-david.s.gordon@intel.com
2016-06-13 16:57:34 +00:00
|
|
|
* in turn, to ensure that all doorbell h/w is (re)initialised.
|
|
|
|
*/
|
|
|
|
static void guc_init_doorbell_hw(struct intel_guc *guc)
|
|
|
|
{
|
|
|
|
struct i915_guc_client *client = guc->execbuf_client;
|
2016-08-09 14:19:20 +00:00
|
|
|
uint16_t db_id;
|
|
|
|
int i, err;
|
drm/i915/guc: (re)initialise doorbell h/w when enabling GuC submission
During a hibernate/resume cycle, the whole system is reset, including
the GuC and the doorbell hardware. Then the system is booted up, drivers
are loaded, etc -- the GuC firmware may be loaded and set running at
this point. But then, the booted kernel is replaced by the hibernated
image, and this resumed kernel will also try to reload the GuC firmware
(which will fail). To recover, we reset the GuC and try again (which
should work). But this GuC reset doesn't also reset the doorbell
hardware, so it can be left in a state inconsistent with that assumed
by the driver and/or the newly-loaded GuC firmware.
It would be better if the GuC reset also cleared all doorbell state,
but that's not how the hardware currently works; also, the driver cannot
directly reprogram the doorbell hardware (only the GuC can do that).
So this patch cycles through all doorbells, assigning and releasing each
in turn, so that all the doorbell hardware is left in a consistent
state, no matter how it was programmed by the previously-running kernel
and/or GuC firmware.
v2: don't use kmap_atomic() now that client page 0 is kept mapped.
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465837054-16245-2-git-send-email-david.s.gordon@intel.com
2016-06-13 16:57:34 +00:00
|
|
|
|
2016-11-29 12:10:23 +00:00
|
|
|
guc_disable_doorbell(guc, client);
|
drm/i915/guc: (re)initialise doorbell h/w when enabling GuC submission
During a hibernate/resume cycle, the whole system is reset, including
the GuC and the doorbell hardware. Then the system is booted up, drivers
are loaded, etc -- the GuC firmware may be loaded and set running at
this point. But then, the booted kernel is replaced by the hibernated
image, and this resumed kernel will also try to reload the GuC firmware
(which will fail). To recover, we reset the GuC and try again (which
should work). But this GuC reset doesn't also reset the doorbell
hardware, so it can be left in a state inconsistent with that assumed
by the driver and/or the newly-loaded GuC firmware.
It would be better if the GuC reset also cleared all doorbell state,
but that's not how the hardware currently works; also, the driver cannot
directly reprogram the doorbell hardware (only the GuC can do that).
So this patch cycles through all doorbells, assigning and releasing each
in turn, so that all the doorbell hardware is left in a consistent
state, no matter how it was programmed by the previously-running kernel
and/or GuC firmware.
v2: don't use kmap_atomic() now that client page 0 is kept mapped.
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465837054-16245-2-git-send-email-david.s.gordon@intel.com
2016-06-13 16:57:34 +00:00
|
|
|
|
|
|
|
for (i = 0; i < GUC_MAX_DOORBELLS; ++i) {
|
2016-08-09 14:19:20 +00:00
|
|
|
/* Skip if doorbell is OK */
|
|
|
|
if (guc_doorbell_check(guc, i))
|
2016-08-09 14:19:19 +00:00
|
|
|
continue;
|
|
|
|
|
drm/i915/guc: (re)initialise doorbell h/w when enabling GuC submission
During a hibernate/resume cycle, the whole system is reset, including
the GuC and the doorbell hardware. Then the system is booted up, drivers
are loaded, etc -- the GuC firmware may be loaded and set running at
this point. But then, the booted kernel is replaced by the hibernated
image, and this resumed kernel will also try to reload the GuC firmware
(which will fail). To recover, we reset the GuC and try again (which
should work). But this GuC reset doesn't also reset the doorbell
hardware, so it can be left in a state inconsistent with that assumed
by the driver and/or the newly-loaded GuC firmware.
It would be better if the GuC reset also cleared all doorbell state,
but that's not how the hardware currently works; also, the driver cannot
directly reprogram the doorbell hardware (only the GuC can do that).
So this patch cycles through all doorbells, assigning and releasing each
in turn, so that all the doorbell hardware is left in a consistent
state, no matter how it was programmed by the previously-running kernel
and/or GuC firmware.
v2: don't use kmap_atomic() now that client page 0 is kept mapped.
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465837054-16245-2-git-send-email-david.s.gordon@intel.com
2016-06-13 16:57:34 +00:00
|
|
|
err = guc_update_doorbell_id(guc, client, i);
|
2016-08-09 14:19:20 +00:00
|
|
|
if (err)
|
|
|
|
DRM_DEBUG_DRIVER("Doorbell %d update failed, err %d\n",
|
|
|
|
i, err);
|
drm/i915/guc: (re)initialise doorbell h/w when enabling GuC submission
During a hibernate/resume cycle, the whole system is reset, including
the GuC and the doorbell hardware. Then the system is booted up, drivers
are loaded, etc -- the GuC firmware may be loaded and set running at
this point. But then, the booted kernel is replaced by the hibernated
image, and this resumed kernel will also try to reload the GuC firmware
(which will fail). To recover, we reset the GuC and try again (which
should work). But this GuC reset doesn't also reset the doorbell
hardware, so it can be left in a state inconsistent with that assumed
by the driver and/or the newly-loaded GuC firmware.
It would be better if the GuC reset also cleared all doorbell state,
but that's not how the hardware currently works; also, the driver cannot
directly reprogram the doorbell hardware (only the GuC can do that).
So this patch cycles through all doorbells, assigning and releasing each
in turn, so that all the doorbell hardware is left in a consistent
state, no matter how it was programmed by the previously-running kernel
and/or GuC firmware.
v2: don't use kmap_atomic() now that client page 0 is kept mapped.
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465837054-16245-2-git-send-email-david.s.gordon@intel.com
2016-06-13 16:57:34 +00:00
|
|
|
}
|
|
|
|
|
2016-11-29 12:10:23 +00:00
|
|
|
db_id = select_doorbell_register(guc, client->priority);
|
|
|
|
WARN_ON(db_id == GUC_INVALID_DOORBELL_ID);
|
|
|
|
|
drm/i915/guc: (re)initialise doorbell h/w when enabling GuC submission
During a hibernate/resume cycle, the whole system is reset, including
the GuC and the doorbell hardware. Then the system is booted up, drivers
are loaded, etc -- the GuC firmware may be loaded and set running at
this point. But then, the booted kernel is replaced by the hibernated
image, and this resumed kernel will also try to reload the GuC firmware
(which will fail). To recover, we reset the GuC and try again (which
should work). But this GuC reset doesn't also reset the doorbell
hardware, so it can be left in a state inconsistent with that assumed
by the driver and/or the newly-loaded GuC firmware.
It would be better if the GuC reset also cleared all doorbell state,
but that's not how the hardware currently works; also, the driver cannot
directly reprogram the doorbell hardware (only the GuC can do that).
So this patch cycles through all doorbells, assigning and releasing each
in turn, so that all the doorbell hardware is left in a consistent
state, no matter how it was programmed by the previously-running kernel
and/or GuC firmware.
v2: don't use kmap_atomic() now that client page 0 is kept mapped.
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465837054-16245-2-git-send-email-david.s.gordon@intel.com
2016-06-13 16:57:34 +00:00
|
|
|
err = guc_update_doorbell_id(guc, client, db_id);
|
|
|
|
if (err)
|
2016-08-18 17:17:23 +00:00
|
|
|
DRM_WARN("Failed to restore doorbell to %d, err %d\n",
|
|
|
|
db_id, err);
|
drm/i915/guc: (re)initialise doorbell h/w when enabling GuC submission
During a hibernate/resume cycle, the whole system is reset, including
the GuC and the doorbell hardware. Then the system is booted up, drivers
are loaded, etc -- the GuC firmware may be loaded and set running at
this point. But then, the booted kernel is replaced by the hibernated
image, and this resumed kernel will also try to reload the GuC firmware
(which will fail). To recover, we reset the GuC and try again (which
should work). But this GuC reset doesn't also reset the doorbell
hardware, so it can be left in a state inconsistent with that assumed
by the driver and/or the newly-loaded GuC firmware.
It would be better if the GuC reset also cleared all doorbell state,
but that's not how the hardware currently works; also, the driver cannot
directly reprogram the doorbell hardware (only the GuC can do that).
So this patch cycles through all doorbells, assigning and releasing each
in turn, so that all the doorbell hardware is left in a consistent
state, no matter how it was programmed by the previously-running kernel
and/or GuC firmware.
v2: don't use kmap_atomic() now that client page 0 is kept mapped.
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465837054-16245-2-git-send-email-david.s.gordon@intel.com
2016-06-13 16:57:34 +00:00
|
|
|
|
2016-08-09 14:19:20 +00:00
|
|
|
/* Read back & verify all doorbell registers */
|
|
|
|
for (i = 0; i < GUC_MAX_DOORBELLS; ++i)
|
|
|
|
(void)guc_doorbell_check(guc, i);
|
drm/i915/guc: (re)initialise doorbell h/w when enabling GuC submission
During a hibernate/resume cycle, the whole system is reset, including
the GuC and the doorbell hardware. Then the system is booted up, drivers
are loaded, etc -- the GuC firmware may be loaded and set running at
this point. But then, the booted kernel is replaced by the hibernated
image, and this resumed kernel will also try to reload the GuC firmware
(which will fail). To recover, we reset the GuC and try again (which
should work). But this GuC reset doesn't also reset the doorbell
hardware, so it can be left in a state inconsistent with that assumed
by the driver and/or the newly-loaded GuC firmware.
It would be better if the GuC reset also cleared all doorbell state,
but that's not how the hardware currently works; also, the driver cannot
directly reprogram the doorbell hardware (only the GuC can do that).
So this patch cycles through all doorbells, assigning and releasing each
in turn, so that all the doorbell hardware is left in a consistent
state, no matter how it was programmed by the previously-running kernel
and/or GuC firmware.
v2: don't use kmap_atomic() now that client page 0 is kept mapped.
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465837054-16245-2-git-send-email-david.s.gordon@intel.com
2016-06-13 16:57:34 +00:00
|
|
|
}
|
|
|
|
|
2015-08-12 14:43:41 +00:00
|
|
|
/**
|
|
|
|
* guc_client_alloc() - Allocate an i915_guc_client
|
2016-06-10 17:29:25 +00:00
|
|
|
* @dev_priv: driver private data structure
|
2016-08-17 12:42:42 +00:00
|
|
|
* @engines: The set of engines to enable for this client
|
2015-08-12 14:43:41 +00:00
|
|
|
* @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
|
|
|
|
* The kernel client to replace ExecList submission is created with
|
|
|
|
* NORMAL priority. Priority of a client for scheduler can be HIGH,
|
|
|
|
* while a preemption context can use CRITICAL.
|
2015-10-19 23:10:54 +00:00
|
|
|
* @ctx: the context that owns the client (we use the default render
|
|
|
|
* context)
|
2015-08-12 14:43:41 +00:00
|
|
|
*
|
2016-04-19 15:08:34 +00:00
|
|
|
* Return: An i915_guc_client object if success, else NULL.
|
2015-08-12 14:43:41 +00:00
|
|
|
*/
|
2016-06-10 17:29:25 +00:00
|
|
|
static struct i915_guc_client *
|
|
|
|
guc_client_alloc(struct drm_i915_private *dev_priv,
|
2016-08-09 14:19:21 +00:00
|
|
|
uint32_t engines,
|
2016-06-10 17:29:25 +00:00
|
|
|
uint32_t priority,
|
|
|
|
struct i915_gem_context *ctx)
|
2015-08-12 14:43:41 +00:00
|
|
|
{
|
|
|
|
struct i915_guc_client *client;
|
|
|
|
struct intel_guc *guc = &dev_priv->guc;
|
2016-08-15 09:48:51 +00:00
|
|
|
struct i915_vma *vma;
|
2016-11-02 17:50:47 +00:00
|
|
|
void *vaddr;
|
2016-06-13 16:57:32 +00:00
|
|
|
uint16_t db_id;
|
2015-08-12 14:43:41 +00:00
|
|
|
|
|
|
|
client = kzalloc(sizeof(*client), GFP_KERNEL);
|
|
|
|
if (!client)
|
|
|
|
return NULL;
|
|
|
|
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 14:43:43 +00:00
|
|
|
client->owner = ctx;
|
2015-08-12 14:43:41 +00:00
|
|
|
client->guc = guc;
|
2016-08-09 14:19:21 +00:00
|
|
|
client->engines = engines;
|
|
|
|
client->priority = priority;
|
|
|
|
client->doorbell_id = GUC_INVALID_DOORBELL_ID;
|
2015-08-12 14:43:41 +00:00
|
|
|
|
|
|
|
client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0,
|
|
|
|
GUC_MAX_GPU_CONTEXTS, GFP_KERNEL);
|
|
|
|
if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) {
|
|
|
|
client->ctx_index = GUC_INVALID_CTX_ID;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* The first page is doorbell/proc_desc. Two followed pages are wq. */
|
2017-01-13 17:41:57 +00:00
|
|
|
vma = intel_guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE);
|
2016-08-15 09:48:51 +00:00
|
|
|
if (IS_ERR(vma))
|
2015-08-12 14:43:41 +00:00
|
|
|
goto err;
|
|
|
|
|
2016-04-19 15:08:34 +00:00
|
|
|
/* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
|
2016-08-15 09:48:51 +00:00
|
|
|
client->vma = vma;
|
2016-11-02 17:50:47 +00:00
|
|
|
|
|
|
|
vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
|
|
|
|
if (IS_ERR(vaddr))
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
client->vaddr = vaddr;
|
2016-09-09 13:11:57 +00:00
|
|
|
|
|
|
|
spin_lock_init(&client->wq_lock);
|
2015-08-12 14:43:41 +00:00
|
|
|
client->wq_offset = GUC_DB_SIZE;
|
|
|
|
client->wq_size = GUC_WQ_SIZE;
|
|
|
|
|
2016-06-13 16:57:33 +00:00
|
|
|
db_id = select_doorbell_register(guc, client->priority);
|
|
|
|
if (db_id == GUC_INVALID_DOORBELL_ID)
|
|
|
|
/* XXX: evict a doorbell instead? */
|
|
|
|
goto err;
|
|
|
|
|
2015-08-12 14:43:41 +00:00
|
|
|
client->doorbell_offset = select_doorbell_cacheline(guc);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Since the doorbell only requires a single cacheline, we can save
|
|
|
|
* space by putting the application process descriptor in the same
|
|
|
|
* page. Use the half of the page that doesn't include the doorbell.
|
|
|
|
*/
|
|
|
|
if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
|
|
|
|
client->proc_desc_offset = 0;
|
|
|
|
else
|
|
|
|
client->proc_desc_offset = (GUC_DB_SIZE / 2);
|
|
|
|
|
2016-09-12 20:19:37 +00:00
|
|
|
guc_proc_desc_init(guc, client);
|
|
|
|
guc_ctx_desc_init(guc, client);
|
2016-11-29 12:10:23 +00:00
|
|
|
|
|
|
|
/* For runtime client allocation we need to enable the doorbell. Not
|
|
|
|
* required yet for the static execbuf_client as this special kernel
|
|
|
|
* client is enabled from i915_guc_submission_enable().
|
|
|
|
*
|
|
|
|
* guc_update_doorbell_id(guc, client, db_id);
|
|
|
|
*/
|
2015-08-12 14:43:41 +00:00
|
|
|
|
2016-08-09 14:19:21 +00:00
|
|
|
DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: ctx_index %u\n",
|
|
|
|
priority, client, client->engines, client->ctx_index);
|
2016-06-13 16:57:32 +00:00
|
|
|
DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n",
|
|
|
|
client->doorbell_id, client->doorbell_offset);
|
2015-08-12 14:43:41 +00:00
|
|
|
|
|
|
|
return client;
|
|
|
|
|
|
|
|
err:
|
2016-06-10 17:29:25 +00:00
|
|
|
guc_client_free(dev_priv, client);
|
2015-08-12 14:43:41 +00:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
drm/i915: Handle log buffer flush interrupt event from GuC
GuC ukernel sends an interrupt to Host to flush the log buffer
and expects Host to correspondingly update the read pointer
information in the state structure, once it has consumed the
log buffer contents by copying them to a file or buffer.
Even if Host couldn't copy the contents, it can still update the
read pointer so that logging state is not disturbed on GuC side.
v2:
- Use a dedicated workqueue for handling flush interrupt. (Tvrtko)
- Reduce the overall log buffer copying time by skipping the copy of
crash buffer area for regular cases and copying only the state
structure data in first page.
v3:
- Create a vmalloc mapping of log buffer. (Chris)
- Cover the flush acknowledgment under rpm get & put.(Chris)
- Revert the change of skipping the copy of crash dump area, as
not really needed, will be covered by subsequent patch.
v4:
- Destroy the wq under the same condition in which it was created,
pass dev_piv pointer instead of dev to newly added GuC function,
add more comments & rename variable for clarity. (Tvrtko)
v5:
- Allocate & destroy the dedicated wq, for handling flush interrupt,
from the setup/teardown routines of GuC logging. (Chris)
- Validate the log buffer size value retrieved from state structure
and do some minor cleanup. (Tvrtko)
- Fix error/warnings reported by checkpatch. (Tvrtko)
- Rebase.
v6:
- Remove the interrupts_enabled check from guc_capture_logs_work, need
to process that last work item also, queued just before disabling the
interrupt as log buffer flush interrupt handling is a bit different
case where GuC is actually expecting an ACK from host, which should be
provided to keep the logging going.
Sync against the work will be done by caller disabling the interrupt.
- Don't sample the log buffer size value from state structure, directly
use the expected value to move the pointer & do the copy and that cannot
go wrong (out of bounds) as Driver only allocated the log buffer and the
relay buffers. Driver should refrain from interpreting the log packet,
as much possible and let Userspace parser detect the anomaly. (Chris)
v7:
- Use switch statement instead of 'if else' for retrieving the GuC log
buffer size. (Tvrtko)
- Refactored the log buffer copying function and shortended the name of
couple of variables for better readability. (Tvrtko)
v8:
- Make the dedicated wq as a high priority one to further reduce the
turnaround time of handing log buffer flush event from GuC.
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2016-10-12 16:24:32 +00:00
|
|
|
|
2016-10-12 16:24:34 +00:00
|
|
|
|
2016-09-12 20:19:37 +00:00
|
|
|
static void guc_policies_init(struct guc_policies *policies)
|
2015-12-18 20:00:10 +00:00
|
|
|
{
|
|
|
|
struct guc_policy *policy;
|
|
|
|
u32 p, i;
|
|
|
|
|
|
|
|
policies->dpc_promote_time = 500000;
|
|
|
|
policies->max_num_work_items = POLICY_MAX_NUM_WI;
|
|
|
|
|
|
|
|
for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) {
|
2016-01-23 19:58:14 +00:00
|
|
|
for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
|
2015-12-18 20:00:10 +00:00
|
|
|
policy = &policies->policy[p][i];
|
|
|
|
|
|
|
|
policy->execution_quantum = 1000000;
|
|
|
|
policy->preemption_time = 500000;
|
|
|
|
policy->fault_time = 250000;
|
|
|
|
policy->policy_flags = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
policies->is_valid = 1;
|
|
|
|
}
|
|
|
|
|
2016-09-12 20:19:37 +00:00
|
|
|
static void guc_addon_create(struct intel_guc *guc)
|
2015-12-18 20:00:09 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
2016-08-15 09:48:51 +00:00
|
|
|
struct i915_vma *vma;
|
2015-12-18 20:00:09 +00:00
|
|
|
struct guc_ads *ads;
|
2015-12-18 20:00:10 +00:00
|
|
|
struct guc_policies *policies;
|
2015-12-18 20:00:11 +00:00
|
|
|
struct guc_mmio_reg_state *reg_state;
|
2016-03-16 11:00:36 +00:00
|
|
|
struct intel_engine_cs *engine;
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
enum intel_engine_id id;
|
2015-12-18 20:00:09 +00:00
|
|
|
struct page *page;
|
2016-03-24 11:20:38 +00:00
|
|
|
u32 size;
|
2015-12-18 20:00:09 +00:00
|
|
|
|
|
|
|
/* The ads obj includes the struct itself and buffers passed to GuC */
|
2015-12-18 20:00:11 +00:00
|
|
|
size = sizeof(struct guc_ads) + sizeof(struct guc_policies) +
|
|
|
|
sizeof(struct guc_mmio_reg_state) +
|
|
|
|
GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE;
|
2015-12-18 20:00:09 +00:00
|
|
|
|
2016-08-15 09:48:51 +00:00
|
|
|
vma = guc->ads_vma;
|
|
|
|
if (!vma) {
|
2017-01-13 17:41:57 +00:00
|
|
|
vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(size));
|
2016-08-15 09:48:51 +00:00
|
|
|
if (IS_ERR(vma))
|
2015-12-18 20:00:09 +00:00
|
|
|
return;
|
|
|
|
|
2016-08-15 09:48:51 +00:00
|
|
|
guc->ads_vma = vma;
|
2015-12-18 20:00:09 +00:00
|
|
|
}
|
|
|
|
|
2016-08-15 09:48:51 +00:00
|
|
|
page = i915_vma_first_page(vma);
|
2015-12-18 20:00:09 +00:00
|
|
|
ads = kmap(page);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The GuC requires a "Golden Context" when it reinitialises
|
|
|
|
* engines after a reset. Here we use the Render ring default
|
|
|
|
* context, which must already exist and be pinned in the GGTT,
|
|
|
|
* so its address won't change after we've told the GuC where
|
|
|
|
* to find it.
|
|
|
|
*/
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
engine = dev_priv->engine[RCS];
|
2016-08-15 09:48:57 +00:00
|
|
|
ads->golden_context_lrca = engine->status_page.ggtt_offset;
|
2015-12-18 20:00:09 +00:00
|
|
|
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
for_each_engine(engine, dev_priv, id)
|
2016-03-16 11:00:36 +00:00
|
|
|
ads->eng_state_size[engine->guc_id] = intel_lr_context_size(engine);
|
2015-12-18 20:00:09 +00:00
|
|
|
|
2015-12-18 20:00:10 +00:00
|
|
|
/* GuC scheduling policies */
|
|
|
|
policies = (void *)ads + sizeof(struct guc_ads);
|
2016-09-12 20:19:37 +00:00
|
|
|
guc_policies_init(policies);
|
2015-12-18 20:00:10 +00:00
|
|
|
|
2016-08-15 09:49:07 +00:00
|
|
|
ads->scheduler_policies =
|
2016-12-24 19:31:46 +00:00
|
|
|
guc_ggtt_offset(vma) + sizeof(struct guc_ads);
|
2015-12-18 20:00:10 +00:00
|
|
|
|
2015-12-18 20:00:11 +00:00
|
|
|
/* MMIO reg state */
|
|
|
|
reg_state = (void *)policies + sizeof(struct guc_policies);
|
|
|
|
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
for_each_engine(engine, dev_priv, id) {
|
2016-03-16 11:00:36 +00:00
|
|
|
reg_state->mmio_white_list[engine->guc_id].mmio_start =
|
|
|
|
engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
|
2015-12-18 20:00:11 +00:00
|
|
|
|
|
|
|
/* Nothing to be saved or restored for now. */
|
2016-03-16 11:00:36 +00:00
|
|
|
reg_state->mmio_white_list[engine->guc_id].count = 0;
|
2015-12-18 20:00:11 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
ads->reg_state_addr = ads->scheduler_policies +
|
|
|
|
sizeof(struct guc_policies);
|
|
|
|
|
|
|
|
ads->reg_state_buffer = ads->reg_state_addr +
|
|
|
|
sizeof(struct guc_mmio_reg_state);
|
|
|
|
|
2015-12-18 20:00:09 +00:00
|
|
|
kunmap(page);
|
|
|
|
}
|
|
|
|
|
2015-08-12 14:43:39 +00:00
|
|
|
/*
|
|
|
|
* Set up the memory resources to be shared with the GuC. At this point,
|
|
|
|
* we require just one object that can be mapped through the GGTT.
|
|
|
|
*/
|
2016-06-10 17:29:26 +00:00
|
|
|
int i915_guc_submission_init(struct drm_i915_private *dev_priv)
|
2015-08-12 14:43:39 +00:00
|
|
|
{
|
2016-09-12 20:19:37 +00:00
|
|
|
const size_t ctxsize = sizeof(struct guc_context_desc);
|
|
|
|
const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize;
|
|
|
|
const size_t gemsize = round_up(poolsize, PAGE_SIZE);
|
2015-08-12 14:43:39 +00:00
|
|
|
struct intel_guc *guc = &dev_priv->guc;
|
2016-08-15 09:48:51 +00:00
|
|
|
struct i915_vma *vma;
|
2015-08-12 14:43:39 +00:00
|
|
|
|
2016-11-29 12:10:23 +00:00
|
|
|
if (!HAS_GUC_SCHED(dev_priv))
|
|
|
|
return 0;
|
|
|
|
|
drm/i915/guc: disable GuC submission earlier during GuC (re)load
When resetting and reloading the GuC, the GuC submission management code
also needs to destroy and recreate the GuC client(s). Currently this is
done by a separate call from the GuC loader, but really, it's just an
internal detail of the submission code. So here we remove the call from
the loader (which is too late, really, because the GuC has already been
reloaded at this point) and put it into guc_submission_init() instead.
This means that any preexisting client is destroyed *before* the GuC
(re)load and then recreated after, iff the firmware was successfully
loaded. If the GuC reload fails, we don't recreate the client, so
fallback to execlists mode (if active) won't leak the client object
(previously, the now-unusable client would have been left allocated,
and leaked if the driver were unloaded).
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2016-06-07 08:14:50 +00:00
|
|
|
/* Wipe bitmap & delete client in case of reinitialisation */
|
|
|
|
bitmap_clear(guc->doorbell_bitmap, 0, GUC_MAX_DOORBELLS);
|
2016-06-10 17:29:26 +00:00
|
|
|
i915_guc_submission_disable(dev_priv);
|
drm/i915/guc: disable GuC submission earlier during GuC (re)load
When resetting and reloading the GuC, the GuC submission management code
also needs to destroy and recreate the GuC client(s). Currently this is
done by a separate call from the GuC loader, but really, it's just an
internal detail of the submission code. So here we remove the call from
the loader (which is too late, really, because the GuC has already been
reloaded at this point) and put it into guc_submission_init() instead.
This means that any preexisting client is destroyed *before* the GuC
(re)load and then recreated after, iff the firmware was successfully
loaded. If the GuC reload fails, we don't recreate the client, so
fallback to execlists mode (if active) won't leak the client object
(previously, the now-unusable client would have been left allocated,
and leaked if the driver were unloaded).
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2016-06-07 08:14:50 +00:00
|
|
|
|
2015-08-12 14:43:39 +00:00
|
|
|
if (!i915.enable_guc_submission)
|
|
|
|
return 0; /* not enabled */
|
|
|
|
|
2016-08-15 09:48:51 +00:00
|
|
|
if (guc->ctx_pool_vma)
|
2015-08-12 14:43:39 +00:00
|
|
|
return 0; /* already allocated */
|
|
|
|
|
2017-01-13 17:41:57 +00:00
|
|
|
vma = intel_guc_allocate_vma(guc, gemsize);
|
2016-08-15 09:48:51 +00:00
|
|
|
if (IS_ERR(vma))
|
|
|
|
return PTR_ERR(vma);
|
2015-08-12 14:43:39 +00:00
|
|
|
|
2016-08-15 09:48:51 +00:00
|
|
|
guc->ctx_pool_vma = vma;
|
2015-08-12 14:43:39 +00:00
|
|
|
ida_init(&guc->ctx_ids);
|
2017-01-13 17:41:57 +00:00
|
|
|
intel_guc_log_create(guc);
|
2016-09-12 20:19:37 +00:00
|
|
|
guc_addon_create(guc);
|
2015-12-18 20:00:09 +00:00
|
|
|
|
2016-11-29 12:10:23 +00:00
|
|
|
guc->execbuf_client = guc_client_alloc(dev_priv,
|
|
|
|
INTEL_INFO(dev_priv)->ring_mask,
|
|
|
|
GUC_CTX_PRIORITY_KMD_NORMAL,
|
|
|
|
dev_priv->kernel_context);
|
|
|
|
if (!guc->execbuf_client) {
|
|
|
|
DRM_ERROR("Failed to create GuC client for execbuf!\n");
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
2015-08-12 14:43:39 +00:00
|
|
|
return 0;
|
2016-11-29 12:10:23 +00:00
|
|
|
|
|
|
|
err:
|
|
|
|
i915_guc_submission_fini(dev_priv);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2016-12-15 19:53:21 +00:00
|
|
|
static void guc_reset_wq(struct i915_guc_client *client)
|
2016-11-29 12:10:23 +00:00
|
|
|
{
|
2016-12-15 19:53:21 +00:00
|
|
|
struct guc_process_desc *desc = client->vaddr +
|
|
|
|
client->proc_desc_offset;
|
2016-11-29 12:10:23 +00:00
|
|
|
|
|
|
|
desc->head = 0;
|
|
|
|
desc->tail = 0;
|
|
|
|
|
2016-12-15 19:53:21 +00:00
|
|
|
client->wq_tail = 0;
|
2015-08-12 14:43:39 +00:00
|
|
|
}
|
|
|
|
|
2016-06-10 17:29:26 +00:00
|
|
|
int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
|
2015-08-12 14:43:41 +00:00
|
|
|
{
|
|
|
|
struct intel_guc *guc = &dev_priv->guc;
|
2016-11-29 12:10:23 +00:00
|
|
|
struct i915_guc_client *client = guc->execbuf_client;
|
2016-08-02 21:50:31 +00:00
|
|
|
struct intel_engine_cs *engine;
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
enum intel_engine_id id;
|
2015-08-12 14:43:41 +00:00
|
|
|
|
2016-11-29 12:10:23 +00:00
|
|
|
if (!client)
|
|
|
|
return -ENODEV;
|
2015-08-12 14:43:41 +00:00
|
|
|
|
2016-11-25 17:59:35 +00:00
|
|
|
intel_guc_sample_forcewake(guc);
|
2016-11-29 12:10:23 +00:00
|
|
|
|
|
|
|
guc_reset_wq(client);
|
drm/i915/guc: (re)initialise doorbell h/w when enabling GuC submission
During a hibernate/resume cycle, the whole system is reset, including
the GuC and the doorbell hardware. Then the system is booted up, drivers
are loaded, etc -- the GuC firmware may be loaded and set running at
this point. But then, the booted kernel is replaced by the hibernated
image, and this resumed kernel will also try to reload the GuC firmware
(which will fail). To recover, we reset the GuC and try again (which
should work). But this GuC reset doesn't also reset the doorbell
hardware, so it can be left in a state inconsistent with that assumed
by the driver and/or the newly-loaded GuC firmware.
It would be better if the GuC reset also cleared all doorbell state,
but that's not how the hardware currently works; also, the driver cannot
directly reprogram the doorbell hardware (only the GuC can do that).
So this patch cycles through all doorbells, assigning and releasing each
in turn, so that all the doorbell hardware is left in a consistent
state, no matter how it was programmed by the previously-running kernel
and/or GuC firmware.
v2: don't use kmap_atomic() now that client page 0 is kept mapped.
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465837054-16245-2-git-send-email-david.s.gordon@intel.com
2016-06-13 16:57:34 +00:00
|
|
|
guc_init_doorbell_hw(guc);
|
2015-08-18 21:34:47 +00:00
|
|
|
|
2016-08-02 21:50:31 +00:00
|
|
|
/* Take over from manual control of ELSP (execlists) */
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
for_each_engine(engine, dev_priv, id) {
|
2016-11-29 12:10:23 +00:00
|
|
|
struct drm_i915_gem_request *rq;
|
|
|
|
|
2016-08-02 21:50:31 +00:00
|
|
|
engine->submit_request = i915_guc_submit;
|
2016-11-14 20:41:03 +00:00
|
|
|
engine->schedule = NULL;
|
2016-08-02 21:50:31 +00:00
|
|
|
|
2016-09-09 13:11:53 +00:00
|
|
|
/* Replay the current set of previously submitted requests */
|
2016-11-29 12:10:23 +00:00
|
|
|
list_for_each_entry(rq, &engine->timeline->requests, link) {
|
2016-09-09 13:11:57 +00:00
|
|
|
client->wq_rsvd += sizeof(struct guc_wq_item);
|
drm/i915/guc: Split hw submission for replay after GPU reset
Something I missed before sending off the partial series was that the
non-scheduler guc reset path was broken (in the full series, this is
pushed to the execlists reset handler). The issue is that after a reset,
we have to refill the GuC workqueues, which we do by resubmitting the
requests. However, if we already have submitted them, the fences within
them have already been used and triggering them again is an error.
Instead, just repopulate the guc workqueue.
[ 115.858560] [IGT] gem_busy: starting subtest hang-render
[ 135.839867] [drm] GPU HANG: ecode 9:0:0xe757fefe, in gem_busy [1716], reason: Hang on render ring, action: reset
[ 135.839902] drm/i915: Resetting chip after gpu hang
[ 135.839957] [drm] RC6 on
[ 135.858351] ------------[ cut here ]------------
[ 135.858357] WARNING: CPU: 2 PID: 45 at drivers/gpu/drm/i915/i915_sw_fence.c:108 i915_sw_fence_complete+0x25/0x30
[ 135.858357] Modules linked in: rfcomm bnep binfmt_misc nls_iso8859_1 input_leds snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hda_core btusb btrtl snd_hwdep snd_pcm 8250_dw snd_seq_midi hid_lenovo snd_seq_midi_event snd_rawmidi iwlwifi x86_pkg_temp_thermal coretemp snd_seq crct10dif_pclmul snd_seq_device hci_uart snd_timer crc32_pclmul ghash_clmulni_intel idma64 aesni_intel virt_dma btbcm snd btqca aes_x86_64 btintel lrw cfg80211 bluetooth gf128mul glue_helper ablk_helper cryptd soundcore intel_lpss_pci intel_pch_thermal intel_lpss_acpi intel_lpss acpi_als mfd_core kfifo_buf acpi_pad industrialio autofs4 hid_plantronics usbhid dm_mirror dm_region_hash dm_log sdhci_pci ahci sdhci libahci i2c_hid hid
[ 135.858389] CPU: 2 PID: 45 Comm: kworker/2:1 Tainted: G W 4.9.0-rc4+ #238
[ 135.858389] Hardware name: /NUC6i3SYB, BIOS SYSKLi35.86A.0024.2015.1027.2142 10/27/2015
[ 135.858392] Workqueue: events_long i915_hangcheck_elapsed
[ 135.858394] ffffc900001bf9b8 ffffffff812bb238 0000000000000000 0000000000000000
[ 135.858396] ffffc900001bf9f8 ffffffff8104f621 0000006c00000000 ffff8808296137f8
[ 135.858398] 0000000000000a00 ffff8808457a0000 ffff880845764e60 ffff880845760000
[ 135.858399] Call Trace:
[ 135.858403] [<ffffffff812bb238>] dump_stack+0x4d/0x65
[ 135.858405] [<ffffffff8104f621>] __warn+0xc1/0xe0
[ 135.858406] [<ffffffff8104f748>] warn_slowpath_null+0x18/0x20
[ 135.858408] [<ffffffff813f8c15>] i915_sw_fence_complete+0x25/0x30
[ 135.858410] [<ffffffff813f8fad>] i915_sw_fence_commit+0xd/0x30
[ 135.858412] [<ffffffff8142e591>] __i915_gem_request_submit+0xe1/0xf0
[ 135.858413] [<ffffffff8142e5c8>] i915_gem_request_submit+0x28/0x40
[ 135.858415] [<ffffffff814433e7>] i915_guc_submit+0x47/0x210
[ 135.858417] [<ffffffff81443e98>] i915_guc_submission_enable+0x468/0x540
[ 135.858419] [<ffffffff81442495>] intel_guc_setup+0x715/0x810
[ 135.858421] [<ffffffff8142b6b4>] i915_gem_init_hw+0x114/0x2a0
[ 135.858423] [<ffffffff813eeaa8>] i915_reset+0xe8/0x120
[ 135.858424] [<ffffffff813f3937>] i915_reset_and_wakeup+0x157/0x180
[ 135.858426] [<ffffffff813f79db>] i915_handle_error+0x1ab/0x230
[ 135.858428] [<ffffffff812c760d>] ? scnprintf+0x4d/0x90
[ 135.858430] [<ffffffff81435985>] i915_hangcheck_elapsed+0x275/0x3d0
[ 135.858432] [<ffffffff810668cf>] process_one_work+0x12f/0x410
[ 135.858433] [<ffffffff81066bf3>] worker_thread+0x43/0x4d0
[ 135.858435] [<ffffffff81066bb0>] ? process_one_work+0x410/0x410
[ 135.858436] [<ffffffff81066bb0>] ? process_one_work+0x410/0x410
[ 135.858438] [<ffffffff8106bbb4>] kthread+0xd4/0xf0
[ 135.858440] [<ffffffff8106bae0>] ? kthread_park+0x60/0x60
v2: Only resubmit submitted requests
v3: Don't forget the pending requests have reserved space.
Fixes: d55ac5bf97c6 ("drm/i915: Defer transfer onto execution timeline to actual hw submission")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161129121024.22650-6-chris@chris-wilson.co.uk
2016-11-29 12:10:24 +00:00
|
|
|
__i915_guc_submit(rq);
|
2016-09-09 13:11:57 +00:00
|
|
|
}
|
2016-09-09 13:11:53 +00:00
|
|
|
}
|
|
|
|
|
2015-08-12 14:43:41 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-06-10 17:29:26 +00:00
|
|
|
void i915_guc_submission_disable(struct drm_i915_private *dev_priv)
|
2015-08-12 14:43:41 +00:00
|
|
|
{
|
|
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
|
|
|
2016-08-02 21:50:31 +00:00
|
|
|
if (!guc->execbuf_client)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Revert back to manual ELSP submission */
|
|
|
|
intel_execlists_enable_submission(dev_priv);
|
2015-08-12 14:43:41 +00:00
|
|
|
}
|
|
|
|
|
2016-06-10 17:29:26 +00:00
|
|
|
void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
|
2015-08-12 14:43:39 +00:00
|
|
|
{
|
|
|
|
struct intel_guc *guc = &dev_priv->guc;
|
2016-11-29 12:10:23 +00:00
|
|
|
struct i915_guc_client *client;
|
|
|
|
|
|
|
|
client = fetch_and_zero(&guc->execbuf_client);
|
|
|
|
if (!client)
|
|
|
|
return;
|
|
|
|
|
|
|
|
guc_client_free(dev_priv, client);
|
2015-08-12 14:43:39 +00:00
|
|
|
|
2016-08-15 09:49:05 +00:00
|
|
|
i915_vma_unpin_and_release(&guc->ads_vma);
|
2016-10-12 16:24:29 +00:00
|
|
|
i915_vma_unpin_and_release(&guc->log.vma);
|
2015-08-12 14:43:40 +00:00
|
|
|
|
2016-08-15 09:48:51 +00:00
|
|
|
if (guc->ctx_pool_vma)
|
2015-08-12 14:43:39 +00:00
|
|
|
ida_destroy(&guc->ctx_ids);
|
2016-08-15 09:49:05 +00:00
|
|
|
i915_vma_unpin_and_release(&guc->ctx_pool_vma);
|
2015-08-12 14:43:39 +00:00
|
|
|
}
|
2015-09-30 16:46:37 +00:00
|
|
|
|
|
|
|
/**
|
|
|
|
* intel_guc_suspend() - notify GuC entering suspend state
|
2016-12-01 14:16:38 +00:00
|
|
|
* @dev_priv: i915 device private
|
2015-09-30 16:46:37 +00:00
|
|
|
*/
|
2016-12-01 14:16:38 +00:00
|
|
|
int intel_guc_suspend(struct drm_i915_private *dev_priv)
|
2015-09-30 16:46:37 +00:00
|
|
|
{
|
|
|
|
struct intel_guc *guc = &dev_priv->guc;
|
2016-05-24 13:53:34 +00:00
|
|
|
struct i915_gem_context *ctx;
|
2015-09-30 16:46:37 +00:00
|
|
|
u32 data[3];
|
|
|
|
|
2017-01-14 01:17:04 +00:00
|
|
|
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
|
2015-09-30 16:46:37 +00:00
|
|
|
return 0;
|
|
|
|
|
2016-10-12 16:24:31 +00:00
|
|
|
gen9_disable_guc_interrupts(dev_priv);
|
|
|
|
|
2016-01-19 19:02:54 +00:00
|
|
|
ctx = dev_priv->kernel_context;
|
2015-09-30 16:46:37 +00:00
|
|
|
|
2016-11-25 17:59:34 +00:00
|
|
|
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
|
2015-09-30 16:46:37 +00:00
|
|
|
/* any value greater than GUC_POWER_D0 */
|
|
|
|
data[1] = GUC_POWER_D1;
|
|
|
|
/* first page is shared data with GuC */
|
2016-12-24 19:31:46 +00:00
|
|
|
data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
|
2015-09-30 16:46:37 +00:00
|
|
|
|
2016-11-25 17:59:35 +00:00
|
|
|
return intel_guc_send(guc, data, ARRAY_SIZE(data));
|
2015-09-30 16:46:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
* intel_guc_resume() - notify GuC resuming from suspend state
|
2016-12-01 14:16:38 +00:00
|
|
|
* @dev_priv: i915 device private
|
2015-09-30 16:46:37 +00:00
|
|
|
*/
|
2016-12-01 14:16:38 +00:00
|
|
|
int intel_guc_resume(struct drm_i915_private *dev_priv)
|
2015-09-30 16:46:37 +00:00
|
|
|
{
|
|
|
|
struct intel_guc *guc = &dev_priv->guc;
|
2016-05-24 13:53:34 +00:00
|
|
|
struct i915_gem_context *ctx;
|
2015-09-30 16:46:37 +00:00
|
|
|
u32 data[3];
|
|
|
|
|
2017-01-14 01:17:04 +00:00
|
|
|
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
|
2015-09-30 16:46:37 +00:00
|
|
|
return 0;
|
|
|
|
|
2016-10-12 16:24:31 +00:00
|
|
|
if (i915.guc_log_level >= 0)
|
|
|
|
gen9_enable_guc_interrupts(dev_priv);
|
|
|
|
|
2016-01-19 19:02:54 +00:00
|
|
|
ctx = dev_priv->kernel_context;
|
2015-09-30 16:46:37 +00:00
|
|
|
|
2016-11-25 17:59:34 +00:00
|
|
|
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
|
2015-09-30 16:46:37 +00:00
|
|
|
data[1] = GUC_POWER_D0;
|
|
|
|
/* first page is shared data with GuC */
|
2016-12-24 19:31:46 +00:00
|
|
|
data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
|
2015-09-30 16:46:37 +00:00
|
|
|
|
2016-11-25 17:59:35 +00:00
|
|
|
return intel_guc_send(guc, data, ARRAY_SIZE(data));
|
2015-09-30 16:46:37 +00:00
|
|
|
}
|
drm/i915: Handle log buffer flush interrupt event from GuC
GuC ukernel sends an interrupt to Host to flush the log buffer
and expects Host to correspondingly update the read pointer
information in the state structure, once it has consumed the
log buffer contents by copying them to a file or buffer.
Even if Host couldn't copy the contents, it can still update the
read pointer so that logging state is not disturbed on GuC side.
v2:
- Use a dedicated workqueue for handling flush interrupt. (Tvrtko)
- Reduce the overall log buffer copying time by skipping the copy of
crash buffer area for regular cases and copying only the state
structure data in first page.
v3:
- Create a vmalloc mapping of log buffer. (Chris)
- Cover the flush acknowledgment under rpm get & put.(Chris)
- Revert the change of skipping the copy of crash dump area, as
not really needed, will be covered by subsequent patch.
v4:
- Destroy the wq under the same condition in which it was created,
pass dev_piv pointer instead of dev to newly added GuC function,
add more comments & rename variable for clarity. (Tvrtko)
v5:
- Allocate & destroy the dedicated wq, for handling flush interrupt,
from the setup/teardown routines of GuC logging. (Chris)
- Validate the log buffer size value retrieved from state structure
and do some minor cleanup. (Tvrtko)
- Fix error/warnings reported by checkpatch. (Tvrtko)
- Rebase.
v6:
- Remove the interrupts_enabled check from guc_capture_logs_work, need
to process that last work item also, queued just before disabling the
interrupt as log buffer flush interrupt handling is a bit different
case where GuC is actually expecting an ACK from host, which should be
provided to keep the logging going.
Sync against the work will be done by caller disabling the interrupt.
- Don't sample the log buffer size value from state structure, directly
use the expected value to move the pointer & do the copy and that cannot
go wrong (out of bounds) as Driver only allocated the log buffer and the
relay buffers. Driver should refrain from interpreting the log packet,
as much possible and let Userspace parser detect the anomaly. (Chris)
v7:
- Use switch statement instead of 'if else' for retrieving the GuC log
buffer size. (Tvrtko)
- Refactored the log buffer copying function and shortended the name of
couple of variables for better readability. (Tvrtko)
v8:
- Make the dedicated wq as a high priority one to further reduce the
turnaround time of handing log buffer flush event from GuC.
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2016-10-12 16:24:32 +00:00
|
|
|
|
2016-10-12 16:24:34 +00:00
|
|
|
|