drm/i915/guc: Decouple GuC engine id from ring id
Previously GuC uses ring id as engine id because of same definition.
But this is not true since this commit:
commit de1add3605
Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Fri Jan 15 15:12:50 2016 +0000
drm/i915: Decouple execbuf uAPI from internal implementation
Added GuC engine id into GuC interface to decouple it from ring id used
by driver.
v2: Keep ring name print out in debugfs; using for_each_ring() where
possible to keep driver consistent. (Chris W.)
Signed-off-by: Alex Dai <yu.dai@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453579094-29860-1-git-send-email-yu.dai@intel.com
This commit is contained in:
Alex Dai
Tvrtko Ursulin
parent
77b04a0428
commit
397097b026
@ -2463,9 +2463,9 @@ static void i915_guc_client_info(struct seq_file *m,
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for_each_ring(ring, dev_priv, i) {
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seq_printf(m, "\tSubmissions: %llu %s\n",
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client->submissions[i],
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client->submissions[ring->guc_id],
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ring->name);
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tot += client->submissions[i];
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tot += client->submissions[ring->guc_id];
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}
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seq_printf(m, "\tTotal: %llu\n", tot);
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}
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@ -2502,10 +2502,10 @@ static int i915_guc_info(struct seq_file *m, void *data)
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seq_printf(m, "\nGuC submissions:\n");
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for_each_ring(ring, dev_priv, i) {
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seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
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ring->name, guc.submissions[i],
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guc.last_seqno[i], guc.last_seqno[i]);
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total += guc.submissions[i];
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seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
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ring->name, guc.submissions[ring->guc_id],
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guc.last_seqno[ring->guc_id]);
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total += guc.submissions[ring->guc_id];
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}
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seq_printf(m, "\t%s: %llu\n", "Total", total);
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@ -376,6 +376,8 @@ static void guc_init_proc_desc(struct intel_guc *guc,
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static void guc_init_ctx_desc(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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struct intel_engine_cs *ring;
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struct intel_context *ctx = client->owner;
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struct guc_context_desc desc;
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struct sg_table *sg;
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@ -388,10 +390,8 @@ static void guc_init_ctx_desc(struct intel_guc *guc,
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desc.priority = client->priority;
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desc.db_id = client->doorbell_id;
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for (i = 0; i < I915_NUM_RINGS; i++) {
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struct guc_execlist_context *lrc = &desc.lrc[i];
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struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf;
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struct intel_engine_cs *ring;
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for_each_ring(ring, dev_priv, i) {
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struct guc_execlist_context *lrc = &desc.lrc[ring->guc_id];
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struct drm_i915_gem_object *obj;
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uint64_t ctx_desc;
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@ -406,7 +406,6 @@ static void guc_init_ctx_desc(struct intel_guc *guc,
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if (!obj)
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break; /* XXX: continue? */
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ring = ringbuf->ring;
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ctx_desc = intel_lr_context_descriptor(ctx, ring);
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lrc->context_desc = (u32)ctx_desc;
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@ -414,16 +413,16 @@ static void guc_init_ctx_desc(struct intel_guc *guc,
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lrc->ring_lcra = i915_gem_obj_ggtt_offset(obj) +
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LRC_STATE_PN * PAGE_SIZE;
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lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
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(ring->id << GUC_ELC_ENGINE_OFFSET);
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(ring->guc_id << GUC_ELC_ENGINE_OFFSET);
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obj = ringbuf->obj;
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obj = ctx->engine[i].ringbuf->obj;
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lrc->ring_begin = i915_gem_obj_ggtt_offset(obj);
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lrc->ring_end = lrc->ring_begin + obj->base.size - 1;
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lrc->ring_next_free_location = lrc->ring_begin;
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lrc->ring_current_tail_pointer_value = 0;
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desc.engines_used |= (1 << ring->id);
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desc.engines_used |= (1 << ring->guc_id);
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}
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WARN_ON(desc.engines_used == 0);
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@ -510,7 +509,6 @@ int i915_guc_wq_check_space(struct i915_guc_client *gc)
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static int guc_add_workqueue_item(struct i915_guc_client *gc,
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struct drm_i915_gem_request *rq)
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{
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enum intel_ring_id ring_id = rq->ring->id;
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struct guc_wq_item *wqi;
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void *base;
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u32 tail, wq_len, wq_off, space;
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@ -544,7 +542,7 @@ static int guc_add_workqueue_item(struct i915_guc_client *gc,
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wq_len = sizeof(struct guc_wq_item) / sizeof(u32) - 1;
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wqi->header = WQ_TYPE_INORDER |
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(wq_len << WQ_LEN_SHIFT) |
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(ring_id << WQ_TARGET_SHIFT) |
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(rq->ring->guc_id << WQ_TARGET_SHIFT) |
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WQ_NO_WCFLUSH_WAIT;
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/* The GuC wants only the low-order word of the context descriptor */
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@ -571,14 +569,14 @@ int i915_guc_submit(struct i915_guc_client *client,
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struct drm_i915_gem_request *rq)
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{
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struct intel_guc *guc = client->guc;
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enum intel_ring_id ring_id = rq->ring->id;
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unsigned int engine_id = rq->ring->guc_id;
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int q_ret, b_ret;
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q_ret = guc_add_workqueue_item(client, rq);
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if (q_ret == 0)
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b_ret = guc_ring_doorbell(client);
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client->submissions[ring_id] += 1;
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client->submissions[engine_id] += 1;
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if (q_ret) {
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client->q_fail += 1;
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client->retcode = q_ret;
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@ -588,8 +586,8 @@ int i915_guc_submit(struct i915_guc_client *client,
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} else {
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client->retcode = 0;
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}
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guc->submissions[ring_id] += 1;
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guc->last_seqno[ring_id] = rq->seqno;
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guc->submissions[engine_id] += 1;
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guc->last_seqno[engine_id] = rq->seqno;
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return q_ret;
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}
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@ -821,7 +819,7 @@ static void init_guc_policies(struct guc_policies *policies)
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policies->max_num_work_items = POLICY_MAX_NUM_WI;
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for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) {
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for (i = 0; i < I915_NUM_RINGS; i++) {
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for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
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policy = &policies->policy[p][i];
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policy->execution_quantum = 1000000;
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@ -873,7 +871,7 @@ static void guc_create_ads(struct intel_guc *guc)
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ads->golden_context_lrca = ring->status_page.gfx_addr;
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for_each_ring(ring, dev_priv, i)
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ads->eng_state_size[i] = intel_lr_context_size(ring);
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ads->eng_state_size[ring->guc_id] = intel_lr_context_size(ring);
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/* GuC scheduling policies */
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policies = (void *)ads + sizeof(struct guc_ads);
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@ -885,12 +883,12 @@ static void guc_create_ads(struct intel_guc *guc)
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/* MMIO reg state */
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reg_state = (void *)policies + sizeof(struct guc_policies);
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for (i = 0; i < I915_NUM_RINGS; i++) {
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reg_state->mmio_white_list[i].mmio_start =
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dev_priv->ring[i].mmio_base + GUC_MMIO_WHITE_LIST_START;
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for_each_ring(ring, dev_priv, i) {
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reg_state->mmio_white_list[ring->guc_id].mmio_start =
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ring->mmio_base + GUC_MMIO_WHITE_LIST_START;
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/* Nothing to be saved or restored for now. */
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reg_state->mmio_white_list[i].count = 0;
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reg_state->mmio_white_list[ring->guc_id].count = 0;
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}
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ads->reg_state_addr = ads->scheduler_policies +
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@ -46,7 +46,7 @@ struct i915_guc_client {
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uint32_t wq_head;
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/* GuC submission statistics & status */
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uint64_t submissions[I915_NUM_RINGS];
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uint64_t submissions[GUC_MAX_ENGINES_NUM];
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uint32_t q_fail;
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uint32_t b_fail;
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int retcode;
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@ -106,8 +106,8 @@ struct intel_guc {
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uint32_t action_fail; /* Total number of failures */
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int32_t action_err; /* Last error code */
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uint64_t submissions[I915_NUM_RINGS];
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uint32_t last_seqno[I915_NUM_RINGS];
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uint64_t submissions[GUC_MAX_ENGINES_NUM];
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uint32_t last_seqno[GUC_MAX_ENGINES_NUM];
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};
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/* intel_guc_loader.c */
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@ -44,6 +44,13 @@
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#define GUC_MAX_GPU_CONTEXTS 1024
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#define GUC_INVALID_CTX_ID GUC_MAX_GPU_CONTEXTS
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#define GUC_RENDER_ENGINE 0
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#define GUC_VIDEO_ENGINE 1
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#define GUC_BLITTER_ENGINE 2
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#define GUC_VIDEOENHANCE_ENGINE 3
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#define GUC_VIDEO_ENGINE2 4
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#define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
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/* Work queue item header definitions */
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#define WQ_STATUS_ACTIVE 1
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#define WQ_STATUS_SUSPENDED 2
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@ -285,7 +292,7 @@ struct guc_context_desc {
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u64 db_trigger_phy;
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u16 db_id;
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struct guc_execlist_context lrc[I915_NUM_RINGS];
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struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM];
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u8 attribute;
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@ -344,7 +351,7 @@ struct guc_policy {
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} __packed;
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struct guc_policies {
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struct guc_policy policy[GUC_CTX_PRIORITY_NUM][I915_NUM_RINGS];
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struct guc_policy policy[GUC_CTX_PRIORITY_NUM][GUC_MAX_ENGINES_NUM];
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/* In micro seconds. How much time to allow before DPC processing is
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* called back via interrupt (to prevent DPC queue drain starving).
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@ -388,14 +395,14 @@ struct guc_mmio_regset {
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struct guc_mmio_reg_state {
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struct guc_mmio_regset global_reg;
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struct guc_mmio_regset engine_reg[I915_NUM_RINGS];
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struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM];
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/* MMIO registers that are set as non privileged */
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struct __packed {
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u32 mmio_start;
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u32 offsets[GUC_MMIO_WHITE_LIST_MAX];
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u32 count;
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} mmio_white_list[I915_NUM_RINGS];
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} mmio_white_list[GUC_MAX_ENGINES_NUM];
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} __packed;
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/* GuC Additional Data Struct */
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@ -406,7 +413,7 @@ struct guc_ads {
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u32 golden_context_lrca;
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u32 scheduler_policies;
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u32 reserved0[3];
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u32 eng_state_size[I915_NUM_RINGS];
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u32 eng_state_size[GUC_MAX_ENGINES_NUM];
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u32 reserved2[4];
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} __packed;
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@ -2088,6 +2088,7 @@ static int logical_render_ring_init(struct drm_device *dev)
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ring->name = "render ring";
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ring->id = RCS;
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ring->exec_id = I915_EXEC_RENDER;
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ring->guc_id = GUC_RENDER_ENGINE;
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ring->mmio_base = RENDER_RING_BASE;
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logical_ring_default_irqs(ring, GEN8_RCS_IRQ_SHIFT);
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@ -2139,6 +2140,7 @@ static int logical_bsd_ring_init(struct drm_device *dev)
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ring->name = "bsd ring";
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ring->id = VCS;
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ring->exec_id = I915_EXEC_BSD;
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ring->guc_id = GUC_VIDEO_ENGINE;
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ring->mmio_base = GEN6_BSD_RING_BASE;
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logical_ring_default_irqs(ring, GEN8_VCS1_IRQ_SHIFT);
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@ -2155,6 +2157,7 @@ static int logical_bsd2_ring_init(struct drm_device *dev)
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ring->name = "bsd2 ring";
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ring->id = VCS2;
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ring->exec_id = I915_EXEC_BSD;
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ring->guc_id = GUC_VIDEO_ENGINE2;
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ring->mmio_base = GEN8_BSD2_RING_BASE;
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logical_ring_default_irqs(ring, GEN8_VCS2_IRQ_SHIFT);
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@ -2171,6 +2174,7 @@ static int logical_blt_ring_init(struct drm_device *dev)
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ring->name = "blitter ring";
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ring->id = BCS;
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ring->exec_id = I915_EXEC_BLT;
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ring->guc_id = GUC_BLITTER_ENGINE;
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ring->mmio_base = BLT_RING_BASE;
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logical_ring_default_irqs(ring, GEN8_BCS_IRQ_SHIFT);
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@ -2187,6 +2191,7 @@ static int logical_vebox_ring_init(struct drm_device *dev)
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ring->name = "video enhancement ring";
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ring->id = VECS;
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ring->exec_id = I915_EXEC_VEBOX;
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ring->guc_id = GUC_VIDEOENHANCE_ENGINE;
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ring->mmio_base = VEBOX_RING_BASE;
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logical_ring_default_irqs(ring, GEN8_VECS_IRQ_SHIFT);
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@ -158,6 +158,7 @@ struct intel_engine_cs {
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#define I915_NUM_RINGS 5
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#define _VCS(n) (VCS + (n))
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unsigned int exec_id;
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unsigned int guc_id;
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u32 mmio_base;
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struct drm_device *dev;
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struct intel_ringbuffer *buffer;
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