License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
|
|
|
// SPDX-License-Identifier: GPL-2.0
|
2017-01-24 08:57:28 +00:00
|
|
|
/*
|
|
|
|
|
* dts file for Hisilicon Hi3660 SoC
|
|
|
|
|
*
|
|
|
|
|
* Copyright (C) 2016, Hisilicon Ltd.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
2017-06-15 03:04:01 +00:00
|
|
|
#include <dt-bindings/clock/hi3660-clock.h>
|
2017-01-24 08:57:28 +00:00
|
|
|
|
|
|
|
|
/ {
|
|
|
|
|
compatible = "hisilicon,hi3660";
|
|
|
|
|
interrupt-parent = <&gic>;
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
|
|
|
|
|
psci {
|
|
|
|
|
compatible = "arm,psci-0.2";
|
|
|
|
|
method = "smc";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpus {
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
cpu-map {
|
|
|
|
|
cluster0 {
|
|
|
|
|
core0 {
|
|
|
|
|
cpu = <&cpu0>;
|
|
|
|
|
};
|
|
|
|
|
core1 {
|
|
|
|
|
cpu = <&cpu1>;
|
|
|
|
|
};
|
|
|
|
|
core2 {
|
|
|
|
|
cpu = <&cpu2>;
|
|
|
|
|
};
|
|
|
|
|
core3 {
|
|
|
|
|
cpu = <&cpu3>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
cluster1 {
|
|
|
|
|
core0 {
|
|
|
|
|
cpu = <&cpu4>;
|
|
|
|
|
};
|
|
|
|
|
core1 {
|
|
|
|
|
cpu = <&cpu5>;
|
|
|
|
|
};
|
|
|
|
|
core2 {
|
|
|
|
|
cpu = <&cpu6>;
|
|
|
|
|
};
|
|
|
|
|
core3 {
|
|
|
|
|
cpu = <&cpu7>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpu0: cpu@0 {
|
|
|
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
|
|
|
device_type = "cpu";
|
|
|
|
|
reg = <0x0 0x0>;
|
|
|
|
|
enable-method = "psci";
|
2017-08-14 09:50:41 +00:00
|
|
|
next-level-cache = <&A53_L2>;
|
2017-08-14 09:50:40 +00:00
|
|
|
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
|
2017-01-24 08:57:28 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpu1: cpu@1 {
|
|
|
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
|
|
|
device_type = "cpu";
|
|
|
|
|
reg = <0x0 0x1>;
|
|
|
|
|
enable-method = "psci";
|
2017-08-14 09:50:41 +00:00
|
|
|
next-level-cache = <&A53_L2>;
|
2017-08-14 09:50:40 +00:00
|
|
|
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
|
2017-01-24 08:57:28 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpu2: cpu@2 {
|
|
|
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
|
|
|
device_type = "cpu";
|
|
|
|
|
reg = <0x0 0x2>;
|
|
|
|
|
enable-method = "psci";
|
2017-08-14 09:50:41 +00:00
|
|
|
next-level-cache = <&A53_L2>;
|
2017-08-14 09:50:40 +00:00
|
|
|
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
|
2017-01-24 08:57:28 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpu3: cpu@3 {
|
|
|
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
|
|
|
device_type = "cpu";
|
|
|
|
|
reg = <0x0 0x3>;
|
|
|
|
|
enable-method = "psci";
|
2017-08-14 09:50:41 +00:00
|
|
|
next-level-cache = <&A53_L2>;
|
2017-08-14 09:50:40 +00:00
|
|
|
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
|
2017-01-24 08:57:28 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpu4: cpu@100 {
|
|
|
|
|
compatible = "arm,cortex-a73", "arm,armv8";
|
|
|
|
|
device_type = "cpu";
|
|
|
|
|
reg = <0x0 0x100>;
|
|
|
|
|
enable-method = "psci";
|
2017-08-14 09:50:41 +00:00
|
|
|
next-level-cache = <&A73_L2>;
|
2017-08-14 09:50:40 +00:00
|
|
|
cpu-idle-states = <
|
|
|
|
|
&CPU_NAP
|
|
|
|
|
&CPU_SLEEP
|
|
|
|
|
&CLUSTER_SLEEP_1
|
|
|
|
|
>;
|
2017-01-24 08:57:28 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpu5: cpu@101 {
|
|
|
|
|
compatible = "arm,cortex-a73", "arm,armv8";
|
|
|
|
|
device_type = "cpu";
|
|
|
|
|
reg = <0x0 0x101>;
|
|
|
|
|
enable-method = "psci";
|
2017-08-14 09:50:41 +00:00
|
|
|
next-level-cache = <&A73_L2>;
|
2017-08-14 09:50:40 +00:00
|
|
|
cpu-idle-states = <
|
|
|
|
|
&CPU_NAP
|
|
|
|
|
&CPU_SLEEP
|
|
|
|
|
&CLUSTER_SLEEP_1
|
|
|
|
|
>;
|
2017-01-24 08:57:28 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpu6: cpu@102 {
|
|
|
|
|
compatible = "arm,cortex-a73", "arm,armv8";
|
|
|
|
|
device_type = "cpu";
|
|
|
|
|
reg = <0x0 0x102>;
|
|
|
|
|
enable-method = "psci";
|
2017-08-14 09:50:41 +00:00
|
|
|
next-level-cache = <&A73_L2>;
|
2017-08-14 09:50:40 +00:00
|
|
|
cpu-idle-states = <
|
|
|
|
|
&CPU_NAP
|
|
|
|
|
&CPU_SLEEP
|
|
|
|
|
&CLUSTER_SLEEP_1
|
|
|
|
|
>;
|
2017-01-24 08:57:28 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpu7: cpu@103 {
|
|
|
|
|
compatible = "arm,cortex-a73", "arm,armv8";
|
|
|
|
|
device_type = "cpu";
|
|
|
|
|
reg = <0x0 0x103>;
|
|
|
|
|
enable-method = "psci";
|
2017-08-14 09:50:41 +00:00
|
|
|
next-level-cache = <&A73_L2>;
|
2017-08-14 09:50:40 +00:00
|
|
|
cpu-idle-states = <
|
|
|
|
|
&CPU_NAP
|
|
|
|
|
&CPU_SLEEP
|
|
|
|
|
&CLUSTER_SLEEP_1
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
idle-states {
|
|
|
|
|
entry-method = "psci";
|
|
|
|
|
|
|
|
|
|
CPU_NAP: cpu-nap {
|
|
|
|
|
compatible = "arm,idle-state";
|
|
|
|
|
arm,psci-suspend-param = <0x0000001>;
|
|
|
|
|
entry-latency-us = <7>;
|
|
|
|
|
exit-latency-us = <2>;
|
|
|
|
|
min-residency-us = <15>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
CPU_SLEEP: cpu-sleep {
|
|
|
|
|
compatible = "arm,idle-state";
|
|
|
|
|
local-timer-stop;
|
|
|
|
|
arm,psci-suspend-param = <0x0010000>;
|
|
|
|
|
entry-latency-us = <40>;
|
|
|
|
|
exit-latency-us = <70>;
|
|
|
|
|
min-residency-us = <3000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
|
|
|
|
compatible = "arm,idle-state";
|
|
|
|
|
local-timer-stop;
|
|
|
|
|
arm,psci-suspend-param = <0x1010000>;
|
|
|
|
|
entry-latency-us = <500>;
|
|
|
|
|
exit-latency-us = <5000>;
|
|
|
|
|
min-residency-us = <20000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
CLUSTER_SLEEP_1: cluster-sleep-1 {
|
|
|
|
|
compatible = "arm,idle-state";
|
|
|
|
|
local-timer-stop;
|
|
|
|
|
arm,psci-suspend-param = <0x1010000>;
|
|
|
|
|
entry-latency-us = <1000>;
|
|
|
|
|
exit-latency-us = <5000>;
|
|
|
|
|
min-residency-us = <20000>;
|
|
|
|
|
};
|
2017-01-24 08:57:28 +00:00
|
|
|
};
|
2017-08-14 09:50:41 +00:00
|
|
|
|
|
|
|
|
A53_L2: l2-cache0 {
|
|
|
|
|
compatible = "cache";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
A73_L2: l2-cache1 {
|
|
|
|
|
compatible = "cache";
|
|
|
|
|
};
|
2017-01-24 08:57:28 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gic: interrupt-controller@e82b0000 {
|
|
|
|
|
compatible = "arm,gic-400";
|
|
|
|
|
reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
|
|
|
|
|
<0x0 0xe82b2000 0 0x2000>, /* GICC */
|
|
|
|
|
<0x0 0xe82b4000 0 0x2000>, /* GICH */
|
|
|
|
|
<0x0 0xe82b6000 0 0x2000>; /* GICV */
|
|
|
|
|
#address-cells = <0>;
|
|
|
|
|
#interrupt-cells = <3>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
|
|
|
|
|
IRQ_TYPE_LEVEL_HIGH)>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-08-14 09:50:42 +00:00
|
|
|
pmu {
|
|
|
|
|
compatible = "arm,armv8-pmuv3";
|
|
|
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-affinity = <&cpu0>,
|
|
|
|
|
<&cpu1>,
|
|
|
|
|
<&cpu2>,
|
|
|
|
|
<&cpu3>,
|
|
|
|
|
<&cpu4>,
|
|
|
|
|
<&cpu5>,
|
|
|
|
|
<&cpu6>,
|
|
|
|
|
<&cpu7>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-01-24 08:57:28 +00:00
|
|
|
timer {
|
|
|
|
|
compatible = "arm,armv8-timer";
|
|
|
|
|
interrupt-parent = <&gic>;
|
|
|
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
|
|
|
|
|
IRQ_TYPE_LEVEL_LOW)>,
|
|
|
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
|
|
|
|
|
IRQ_TYPE_LEVEL_LOW)>,
|
|
|
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
|
|
|
|
|
IRQ_TYPE_LEVEL_LOW)>,
|
|
|
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
|
|
|
|
|
IRQ_TYPE_LEVEL_LOW)>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
soc {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
ranges;
|
|
|
|
|
|
2017-06-15 03:04:01 +00:00
|
|
|
crg_ctrl: crg_ctrl@fff35000 {
|
|
|
|
|
compatible = "hisilicon,hi3660-crgctrl", "syscon";
|
|
|
|
|
reg = <0x0 0xfff35000 0x0 0x1000>;
|
|
|
|
|
#clock-cells = <1>;
|
2017-01-24 08:57:28 +00:00
|
|
|
};
|
|
|
|
|
|
2017-06-15 03:04:01 +00:00
|
|
|
crg_rst: crg_rst_controller {
|
|
|
|
|
compatible = "hisilicon,hi3660-reset";
|
|
|
|
|
#reset-cells = <2>;
|
|
|
|
|
hisi,rst-syscon = <&crg_ctrl>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
pctrl: pctrl@e8a09000 {
|
|
|
|
|
compatible = "hisilicon,hi3660-pctrl", "syscon";
|
|
|
|
|
reg = <0x0 0xe8a09000 0x0 0x2000>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmuctrl: crg_ctrl@fff34000 {
|
|
|
|
|
compatible = "hisilicon,hi3660-pmuctrl", "syscon";
|
|
|
|
|
reg = <0x0 0xfff34000 0x0 0x1000>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sctrl: sctrl@fff0a000 {
|
|
|
|
|
compatible = "hisilicon,hi3660-sctrl", "syscon";
|
|
|
|
|
reg = <0x0 0xfff0a000 0x0 0x1000>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
iomcu: iomcu@ffd7e000 {
|
|
|
|
|
compatible = "hisilicon,hi3660-iomcu", "syscon";
|
|
|
|
|
reg = <0x0 0xffd7e000 0x0 0x1000>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
iomcu_rst: reset {
|
|
|
|
|
compatible = "hisilicon,hi3660-reset";
|
|
|
|
|
hisi,rst-syscon = <&iomcu>;
|
|
|
|
|
#reset-cells = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-06-15 03:04:10 +00:00
|
|
|
dual_timer0: timer@fff14000 {
|
|
|
|
|
compatible = "arm,sp804", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xfff14000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_OSC32K>,
|
|
|
|
|
<&crg_ctrl HI3660_OSC32K>,
|
|
|
|
|
<&crg_ctrl HI3660_OSC32K>;
|
|
|
|
|
clock-names = "timer1", "timer2", "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
2017-06-15 03:04:02 +00:00
|
|
|
i2c0: i2c@ffd71000 {
|
|
|
|
|
compatible = "snps,designware-i2c";
|
|
|
|
|
reg = <0x0 0xffd71000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-frequency = <400000>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
|
|
|
|
|
resets = <&iomcu_rst 0x20 3>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c1: i2c@ffd72000 {
|
|
|
|
|
compatible = "snps,designware-i2c";
|
|
|
|
|
reg = <0x0 0xffd72000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-frequency = <400000>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
|
|
|
|
|
resets = <&iomcu_rst 0x20 4>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c3: i2c@fdf0c000 {
|
|
|
|
|
compatible = "snps,designware-i2c";
|
|
|
|
|
reg = <0x0 0xfdf0c000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-frequency = <400000>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
|
|
|
|
|
resets = <&crg_rst 0x78 7>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c7: i2c@fdf0b000 {
|
|
|
|
|
compatible = "snps,designware-i2c";
|
|
|
|
|
reg = <0x0 0xfdf0b000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-frequency = <400000>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
|
|
|
|
|
resets = <&crg_rst 0x60 14>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2017-06-15 03:04:04 +00:00
|
|
|
uart0: serial@fdf02000 {
|
|
|
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xfdf02000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
|
|
|
|
|
<&crg_ctrl HI3660_PCLK>;
|
|
|
|
|
clock-names = "uartclk", "apb_pclk";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart1: serial@fdf00000 {
|
|
|
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xfdf00000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
|
|
|
|
|
<&crg_ctrl HI3660_CLK_GATE_UART1>;
|
|
|
|
|
clock-names = "uartclk", "apb_pclk";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart2: serial@fdf03000 {
|
|
|
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xfdf03000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
|
|
|
|
|
<&crg_ctrl HI3660_PCLK>;
|
|
|
|
|
clock-names = "uartclk", "apb_pclk";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart3: serial@ffd74000 {
|
|
|
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xffd74000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
|
|
|
|
|
<&crg_ctrl HI3660_PCLK>;
|
|
|
|
|
clock-names = "uartclk", "apb_pclk";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart4: serial@fdf01000 {
|
|
|
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xfdf01000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
|
|
|
|
|
<&crg_ctrl HI3660_CLK_GATE_UART4>;
|
|
|
|
|
clock-names = "uartclk", "apb_pclk";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2017-06-15 03:04:01 +00:00
|
|
|
uart5: serial@fdf05000 {
|
2017-01-24 08:57:28 +00:00
|
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xfdf05000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
2017-06-15 03:04:01 +00:00
|
|
|
clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
|
|
|
|
|
<&crg_ctrl HI3660_CLK_GATE_UART5>;
|
2017-01-24 08:57:28 +00:00
|
|
|
clock-names = "uartclk", "apb_pclk";
|
2017-06-15 03:04:04 +00:00
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart6: serial@fff32000 {
|
|
|
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xfff32000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_CLK_UART6>,
|
|
|
|
|
<&crg_ctrl HI3660_PCLK>;
|
|
|
|
|
clock-names = "uartclk", "apb_pclk";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
|
2017-01-24 08:57:28 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2017-06-15 03:04:03 +00:00
|
|
|
|
2017-08-14 09:50:48 +00:00
|
|
|
dma0: dma@fdf30000 {
|
|
|
|
|
compatible = "hisilicon,k3-dma-1.0";
|
|
|
|
|
reg = <0x0 0xfdf30000 0x0 0x1000>;
|
|
|
|
|
#dma-cells = <1>;
|
|
|
|
|
dma-channels = <16>;
|
|
|
|
|
dma-requests = <32>;
|
|
|
|
|
dma-min-chan = <1>;
|
|
|
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
|
|
|
|
|
dma-no-cci;
|
|
|
|
|
dma-type = "hi3660_dma";
|
|
|
|
|
};
|
|
|
|
|
|
2017-06-15 03:04:06 +00:00
|
|
|
rtc0: rtc@fff04000 {
|
|
|
|
|
compatible = "arm,pl031", "arm,primecell";
|
|
|
|
|
reg = <0x0 0Xfff04000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
2017-06-15 03:04:03 +00:00
|
|
|
gpio0: gpio@e8a0b000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a0b000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx0 1 0 7>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio1: gpio@e8a0c000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a0c000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx0 1 7 7>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio2: gpio@e8a0d000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a0d000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx0 0 14 8>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio3: gpio@e8a0e000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a0e000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx0 0 22 8>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio4: gpio@e8a0f000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a0f000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx0 0 30 8>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio5: gpio@e8a10000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a10000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx0 0 38 8>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio6: gpio@e8a11000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a11000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx0 0 46 8>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio7: gpio@e8a12000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a12000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx0 0 54 8>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio8: gpio@e8a13000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a13000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx0 0 62 8>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio9: gpio@e8a14000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a14000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx0 0 70 8>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio10: gpio@e8a15000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a15000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx0 0 78 8>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio11: gpio@e8a16000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a16000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx0 0 86 8>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio12: gpio@e8a17000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a17000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio13: gpio@e8a18000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a18000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx0 0 102 8>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio14: gpio@e8a19000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a19000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx0 0 110 8>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio15: gpio@e8a1a000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a1a000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx0 0 118 6>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio16: gpio@e8a1b000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a1b000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio17: gpio@e8a1c000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a1c000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio18: gpio@ff3b4000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xff3b4000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx2 0 0 8>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio19: gpio@ff3b5000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xff3b5000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx2 0 8 4>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio20: gpio@e8a1f000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a1f000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx1 0 0 6>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio21: gpio@e8a20000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xe8a20000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx3 0 0 6>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio22: gpio@fff0b000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xfff0b000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
/* GPIO176 */
|
|
|
|
|
gpio-ranges = <&pmx4 2 0 6>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio23: gpio@fff0c000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xfff0c000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
/* GPIO184 */
|
|
|
|
|
gpio-ranges = <&pmx4 0 6 7>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio24: gpio@fff0d000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xfff0d000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
/* GPIO192 */
|
|
|
|
|
gpio-ranges = <&pmx4 0 13 8>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio25: gpio@fff0e000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xfff0e000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
/* GPIO200 */
|
|
|
|
|
gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio26: gpio@fff0f000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xfff0f000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
/* GPIO208 */
|
|
|
|
|
gpio-ranges = <&pmx4 0 28 8>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio27: gpio@fff10000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xfff10000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
/* GPIO216 */
|
|
|
|
|
gpio-ranges = <&pmx4 0 36 6>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio28: gpio@fff1d000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0 0xfff1d000 0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
2017-06-15 03:04:09 +00:00
|
|
|
|
|
|
|
|
spi2: spi@ffd68000 {
|
|
|
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xffd68000 0x0 0x1000>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&spi2_pmx_func>;
|
|
|
|
|
num-cs = <1>;
|
|
|
|
|
cs-gpios = <&gpio27 2 0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi3: spi@ff3b3000 {
|
|
|
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xff3b3000 0x0 0x1000>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&spi3_pmx_func>;
|
|
|
|
|
num-cs = <1>;
|
|
|
|
|
cs-gpios = <&gpio18 5 0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2017-06-16 14:13:22 +00:00
|
|
|
|
|
|
|
|
pcie@f4000000 {
|
|
|
|
|
compatible = "hisilicon,kirin960-pcie";
|
|
|
|
|
reg = <0x0 0xf4000000 0x0 0x1000>,
|
|
|
|
|
<0x0 0xff3fe000 0x0 0x1000>,
|
|
|
|
|
<0x0 0xf3f20000 0x0 0x40000>,
|
|
|
|
|
<0x0 0xf5000000 0x0 0x2000>;
|
|
|
|
|
reg-names = "dbi", "apb", "phy", "config";
|
|
|
|
|
bus-range = <0x0 0x1>;
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
ranges = <0x02000000 0x0 0x00000000
|
|
|
|
|
0x0 0xf6000000
|
|
|
|
|
0x0 0x02000000>;
|
|
|
|
|
num-lanes = <1>;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
|
|
|
interrupt-map = <0x0 0 0 1
|
|
|
|
|
&gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0x0 0 0 2
|
|
|
|
|
&gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0x0 0 0 3
|
|
|
|
|
&gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0x0 0 0 4
|
|
|
|
|
&gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
|
|
|
|
|
<&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
|
|
|
|
|
<&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
|
|
|
|
|
<&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
|
|
|
|
|
<&crg_ctrl HI3660_ACLK_GATE_PCIE>;
|
|
|
|
|
clock-names = "pcie_phy_ref", "pcie_aux",
|
|
|
|
|
"pcie_apb_phy", "pcie_apb_sys",
|
|
|
|
|
"pcie_aclk";
|
|
|
|
|
reset-gpios = <&gpio11 1 0 >;
|
|
|
|
|
};
|
2017-06-15 03:04:16 +00:00
|
|
|
|
|
|
|
|
/* SD */
|
|
|
|
|
dwmmc1: dwmmc1@ff37f000 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
cd-inverted;
|
|
|
|
|
compatible = "hisilicon,hi3660-dw-mshc";
|
|
|
|
|
num-slots = <1>;
|
|
|
|
|
bus-width = <0x4>;
|
|
|
|
|
disable-wp;
|
|
|
|
|
cap-sd-highspeed;
|
|
|
|
|
supports-highspeed;
|
|
|
|
|
card-detect-delay = <200>;
|
|
|
|
|
reg = <0x0 0xff37f000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
|
|
|
|
|
<&crg_ctrl HI3660_HCLK_GATE_SD>;
|
|
|
|
|
clock-names = "ciu", "biu";
|
|
|
|
|
clock-frequency = <3200000>;
|
|
|
|
|
resets = <&crg_rst 0x94 18>;
|
2017-08-14 09:50:46 +00:00
|
|
|
reset-names = "reset";
|
2017-06-15 03:04:16 +00:00
|
|
|
cd-gpios = <&gpio25 3 0>;
|
|
|
|
|
hisilicon,peripheral-syscon = <&sctrl>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&sd_pmx_func
|
|
|
|
|
&sd_clk_cfg_func
|
|
|
|
|
&sd_cfg_func>;
|
|
|
|
|
sd-uhs-sdr12;
|
|
|
|
|
sd-uhs-sdr25;
|
|
|
|
|
sd-uhs-sdr50;
|
|
|
|
|
sd-uhs-sdr104;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
slot@0 {
|
|
|
|
|
reg = <0x0>;
|
|
|
|
|
bus-width = <4>;
|
|
|
|
|
disable-wp;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* SDIO */
|
|
|
|
|
dwmmc2: dwmmc2@ff3ff000 {
|
|
|
|
|
compatible = "hisilicon,hi3660-dw-mshc";
|
|
|
|
|
reg = <0x0 0xff3ff000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
num-slots = <1>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
|
|
|
|
|
<&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
|
|
|
|
|
clock-names = "ciu", "biu";
|
|
|
|
|
resets = <&crg_rst 0x94 20>;
|
2017-08-14 09:50:46 +00:00
|
|
|
reset-names = "reset";
|
2017-06-15 03:04:16 +00:00
|
|
|
card-detect-delay = <200>;
|
|
|
|
|
supports-highspeed;
|
|
|
|
|
keep-power-in-suspend;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&sdio_pmx_func
|
|
|
|
|
&sdio_clk_cfg_func
|
|
|
|
|
&sdio_cfg_func>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2017-08-14 09:50:49 +00:00
|
|
|
|
|
|
|
|
watchdog0: watchdog@e8a06000 {
|
|
|
|
|
compatible = "arm,sp805-wdt", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xe8a06000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_OSC32K>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
watchdog1: watchdog@e8a07000 {
|
|
|
|
|
compatible = "arm,sp805-wdt", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xe8a07000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&crg_ctrl HI3660_OSC32K>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
2017-10-10 18:02:50 +00:00
|
|
|
|
|
|
|
|
tsensor: tsensor@fff30000 {
|
|
|
|
|
compatible = "hisilicon,hi3660-tsensor";
|
|
|
|
|
reg = <0x0 0xfff30000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#thermal-sensor-cells = <1>;
|
|
|
|
|
};
|
2017-01-24 08:57:28 +00:00
|
|
|
};
|
|
|
|
|
};
|
