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'origin/GT-3529_ghidorahrex_cr16c_abs20_fix' Fixes #1518
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89f1aa9574
@ -3,7 +3,7 @@ Module.manifest||GHIDRA||||END|
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build.gradle||GHIDRA||||END|
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data/build.xml||GHIDRA||||END|
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data/languages/CR16.cspec||GHIDRA||||END|
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data/languages/CR16.ldefs||GHIDRA||reviewed||END|
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data/languages/CR16.ldefs||GHIDRA||||END|
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data/languages/CR16.opinion||GHIDRA||reviewed||END|
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data/languages/CR16.pspec||GHIDRA||reviewed||END|
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data/languages/CR16B.sinc||GHIDRA||reviewed||END|
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@ -6,7 +6,7 @@
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endian="little"
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size="16"
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variant="default"
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version="1.0"
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version="1.1"
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slafile="CR16B.sla"
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processorspec="CR16.pspec"
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manualindexfile="../manuals/CR16.idx"
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@ -19,7 +19,7 @@
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endian="little"
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size="16"
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variant="default"
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version="1.0"
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version="1.1"
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slafile="CR16C.sla"
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processorspec="CR16.pspec"
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manualindexfile="../manuals/CR16.idx"
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@ -287,12 +287,12 @@ cnt3b: "$"tmp is b0_2 [ tmp = b0_2 + 1; ] { export *[const]:1 tmp;
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# If (abs20 > 0xEFFFF) the resulting address is logically ORed with 0xF00000
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# i.e. addresses from 1M-64k to 1M are re-mapped by the core to 16M-64k to 16M.
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abs20: tmp is n5=0xf & dw_w2 [ tmp = 0xff0000 | dw_w2; ] {
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export *[const]:3 tmp;
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}
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abs20: tmp is n5 & dw_w2 [ tmp = (n5 << 16) + dw_w2; ] {
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tmp2:3 = tmp;
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if (tmp2 <= 0xefffff) goto <abs20end>;
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tmp2 = tmp2 | 0xf00000;
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<abs20end>
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export *[const]:3 tmp2;
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export *[const]:3 tmp;
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}
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abs24: "*"tmp is n5 & n7 & b0_15
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