diff --git a/Ghidra/Processors/CR16/certification.manifest b/Ghidra/Processors/CR16/certification.manifest
index e0749c9be4..a45e792966 100644
--- a/Ghidra/Processors/CR16/certification.manifest
+++ b/Ghidra/Processors/CR16/certification.manifest
@@ -3,7 +3,7 @@ Module.manifest||GHIDRA||||END|
 build.gradle||GHIDRA||||END|
 data/build.xml||GHIDRA||||END|
 data/languages/CR16.cspec||GHIDRA||||END|
-data/languages/CR16.ldefs||GHIDRA||reviewed||END|
+data/languages/CR16.ldefs||GHIDRA||||END|
 data/languages/CR16.opinion||GHIDRA||reviewed||END|
 data/languages/CR16.pspec||GHIDRA||reviewed||END|
 data/languages/CR16B.sinc||GHIDRA||reviewed||END|
diff --git a/Ghidra/Processors/CR16/data/languages/CR16.ldefs b/Ghidra/Processors/CR16/data/languages/CR16.ldefs
index e0837a9200..bbaafd28c5 100644
--- a/Ghidra/Processors/CR16/data/languages/CR16.ldefs
+++ b/Ghidra/Processors/CR16/data/languages/CR16.ldefs
@@ -6,7 +6,7 @@
             endian="little"
             size="16"
             variant="default"
-            version="1.0"
+            version="1.1"
             slafile="CR16B.sla"
             processorspec="CR16.pspec"
             manualindexfile="../manuals/CR16.idx"
@@ -19,7 +19,7 @@
             endian="little"
             size="16"
             variant="default"
-            version="1.0"
+            version="1.1"
             slafile="CR16C.sla"
             processorspec="CR16.pspec"
             manualindexfile="../manuals/CR16.idx"
diff --git a/Ghidra/Processors/CR16/data/languages/CR16C.sinc b/Ghidra/Processors/CR16/data/languages/CR16C.sinc
index a1e6aa21f9..f70a45749d 100644
--- a/Ghidra/Processors/CR16/data/languages/CR16C.sinc
+++ b/Ghidra/Processors/CR16/data/languages/CR16C.sinc
@@ -287,12 +287,12 @@ cnt3b:  "$"tmp  is b0_2         [ tmp = b0_2 + 1; ]     { export *[const]:1 tmp;
 
 # If (abs20 > 0xEFFFF) the resulting address is logically ORed with 0xF00000 
 #   i.e. addresses from 1M-64k to 1M are re-mapped by the core to 16M-64k to 16M.
+abs20:  tmp     is n5=0xf & dw_w2       [ tmp = 0xff0000 | dw_w2; ]   { 
+    export *[const]:3 tmp; 
+}
+
 abs20:  tmp     is n5 & dw_w2       [ tmp = (n5 << 16) + dw_w2; ]   { 
-    tmp2:3 = tmp;
-    if (tmp2 <= 0xefffff) goto <abs20end>;
-        tmp2 = tmp2 | 0xf00000;
-    <abs20end>
-    export *[const]:3 tmp2; 
+    export *[const]:3 tmp; 
 }
 
 abs24:  "*"tmp  is n5 & n7 & b0_15