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Merge remote-tracking branch 'origin/GP-1817_ghidorahrex_PR-3222_aeflores_add-vfma-to-arm'

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Ryan Kurtz 2022-06-08 01:42:30 -04:00
commit 18bc6afb95
5 changed files with 84 additions and 0 deletions
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1
Ghidra/Processors/ARM/data/languages/ARM7_be.slaspec
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@ -10,6 +10,7 @@
@define VERSION_7M ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""
@include "ARM.sinc"

1
Ghidra/Processors/ARM/data/languages/ARM7_le.slaspec
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@ -10,6 +10,7 @@
@define VERSION_7M ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""
@include "ARM.sinc"

1
Ghidra/Processors/ARM/data/languages/ARM8_be.slaspec
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@ -11,6 +11,7 @@
@define VERSION_8 ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""
@include "ARM.sinc"

1
Ghidra/Processors/ARM/data/languages/ARM8_le.slaspec
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@ -11,6 +11,7 @@
@define VERSION_8 ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""
@include "ARM.sinc"

80
Ghidra/Processors/ARM/data/languages/ARMneon.sinc
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@ -1814,6 +1814,86 @@ extImm: "#"^thv_c0811 is TMode=1 & thv_c0811 { tmp:1 = thv_c0811; export tmp; }
Qd = VectorHalvingSubtract(Qn,Qm,esize2021,udt);
}
#######
# VFMA VFMS VFNMA and VFNMS
#
@if defined(VFPv4)
:vfma^COND^".f16" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=1 & c0606=0 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=1 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = zext(Sd:2 f+ (Sn:2 f* Sm:2));
}
:vfma^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=2 & c0606=0 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=2 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = Sd f+ (Sn f* Sm);
}
:vfma^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=3 & c0606=0 & c0404=0) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=3 & thv_c0606=0 & thv_c0404=0)) & Dm & Dn & Dd
{
Dd = Dd f+ (Dn f* Dm);
}
:vfms^COND^".f16" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=1 & c0606=1 & c0404=0) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=1 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = zext(Sd:2 f+ ((f- Sn:2) f* Sm:2));
}
:vfms^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=2 & c0606=1 & c0404=0) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=2 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = Sd f+ ((f- Sn) f* Sm);
}
:vfms^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=3 & c0606=1 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=3 & thv_c0606=1 & thv_c0404=0)) & Dm & Dn & Dd
{
Dd = Dd f+ ((f- Dn) f* Dm);
}
:vfnma^COND^".f16" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=1 & c0606=1 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=1 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = zext((f- Sd:2) f+ ((f- Sn:2) f* Sm:2));
}
:vfnma^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=2 & c0606=1 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=2 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = (f- Sd) f+ ((f- Sn) f* Sm);
}
:vfnma^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=3 & c0606=1 & c0404=0) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=3 & thv_c0606=1 & thv_c0404=0)) & Dm & Dn & Dd
{
Dd = (f- Dd) f+ ((f- Dn) f* Dm);
}
:vfnms^COND^".f16" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=1 & c0606=0 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=1 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = zext((f- Sd:2) f+ (Sn:2 f* Sm:2));
}
:vfnms^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=2 & c0606=0 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=2 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = (f- Sd) f+ (Sn f* Sm);
}
:vfnms^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=3 & c0606=0 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=3 & thv_c0606=0 & thv_c0404=0)) & Dm & Dn & Dd
{
Dd = (f- Dd) f+ (Dn f* Dm);
}
@endif # VFPv4
#######
# VLD1 (multiple single elements)
#