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correct vfnma vfnms semantics

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and rewrite vfms expression to match manual more closely.
This commit is contained in:
Antonio Flores Montoya 2022-05-27 10:33:32 -04:00
parent 128118b51b
commit 808143cd60
1 changed files with 9 additions and 9 deletions
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18
Ghidra/Processors/ARM/data/languages/ARMneon.sinc
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@ -1841,55 +1841,55 @@ extImm: "#"^thv_c0811 is TMode=1 & thv_c0811 { tmp:1 = thv_c0811; export tmp; }
:vfms^COND^".f16" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=1 & c0606=1 & c0404=0) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=1 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = zext(Sd:2 f- (Sn:2 f* Sm:2));
Sd = zext(Sd:2 f+ ((f- Sn:2) f* Sm:2));
}
:vfms^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=2 & c0606=1 & c0404=0) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=2 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = Sd f- (Sn f* Sm);
Sd = Sd f+ ((f- Sn) f* Sm);
}
:vfms^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=3 & c0606=1 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=3 & thv_c0606=1 & thv_c0404=0)) & Dm & Dn & Dd
{
Dd = Dd f- (Dn f* Dm);
Dd = Dd f+ ((f- Dn) f* Dm);
}
:vfnma^COND^".f16" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=1 & c0606=1 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=1 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = zext(Sd:2 f+ ((0 f- Sn:2) f* Sm:2));
Sd = zext((f- Sd:2) f+ ((f- Sn:2) f* Sm:2));
}
:vfnma^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=2 & c0606=1 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=2 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = Sd f+ ((0 f- Sn) f* Sm);
Sd = (f- Sd) f+ ((f- Sn) f* Sm);
}
:vfnma^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=3 & c0606=1 & c0404=0) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=3 & thv_c0606=1 & thv_c0404=0)) & Dm & Dn & Dd
{
Dd = Dd f+ ((0 f- Dn) f* Dm);
Dd = (f- Dd) f+ ((f- Dn) f* Dm);
}
:vfnms^COND^".f16" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=1 & c0606=0 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=1 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = zext(Sd:2 f- ((0 f- Sn:2) f* Sm:2));
Sd = zext((f- Sd:2) f+ (Sn:2 f* Sm:2));
}
:vfnms^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=2 & c0606=0 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=2 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = Sd f- ((0 f- Sn) f* Sm);
Sd = (f- Sd) f+ (Sn f* Sm);
}
:vfnms^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=3 & c0606=0 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=3 & thv_c0606=0 & thv_c0404=0)) & Dm & Dn & Dd
{
Dd = Dd f- ((0 f- Dn) f* Dm);
Dd = (f- Dd) f+ (Dn f* Dm);
}
@endif # VFPv4