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Use just one memory access for SDBD reads/writes.
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@ -78,25 +78,27 @@ impliedval16: reg3_5 is reg3_5 & target3_5=6 & doublebyte=0 {
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}
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impliedval16: reg3_5 is reg3_5 & (target3_5=4 | target3_5=5) & doublebyte=1 {
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local tmp:2 = zext(*:1 reg3_5);
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reg3_5 = reg3_5 + 1;
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tmp = tmp | (zext(*:1 reg3_5) << 8);
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reg3_5 = reg3_5 + 1;
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local val:4 = *:4 reg3_5;
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local low:1 = val(2);
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local high:1 = val(0);
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local tmp:2 = (zext(high) << 8) | zext(low);
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reg3_5 = reg3_5 + 2;
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export tmp;
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}
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impliedval16: reg3_5 is reg3_5 & target3_5=6 & doublebyte=1 {
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reg3_5 = reg3_5 - 1;
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local tmp:2 = zext(*:1 reg3_5);
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reg3_5 = reg3_5 - 1;
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tmp = tmp | (zext(*:1 reg3_5) << 8);
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reg3_5 = reg3_5 - 2;
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local val:4 = *:4 reg3_5;
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local low:1 = val(2);
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local high:1 = val(0);
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local tmp:2 = (zext(high) << 8) | zext(low);
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export tmp;
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}
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impliedval16: reg3_5 is reg3_5 & (target3_5=0 | target3_5=1 | target3_5=2 | target3_5=3 | target3_5=7) & doublebyte=1 {
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local tmp:2 = zext(*:1 reg3_5);
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tmp = tmp | (zext(*:1 reg3_5) << 8);
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export tmp;
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local val:2 = *:1 reg3_5;
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val = (zext(val) << 8) | zext(val);
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export val;
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}
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checkbranch: is reg0_2=7 { goto [R7]; }
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