Samuel Holland dc892fb443 riscv: Use IPIs for remote cache/TLB flushes by default ... An IPI backend is always required in an SMP configuration, but an SBI implementation is not. For example, SBI will be unavailable when the kernel runs in M mode. For this reason, consider IPI delivery of cache and TLB flushes to be the base case, and any other implementation (such as the SBI remote fence extension) to be an optimization. Generally, if IPIs can be delivered without firmware assistance, they are assumed to be faster than SBI calls due to the SBI context switch overhead. However, when SBI is used as the IPI backend, then the context switch cost must be paid anyway, and performing the cache/TLB flush directly in the SBI implementation is more efficient than injecting an interrupt to S-mode. This is the only existing scenario where riscv_ipi_set_virq_range() is called with use_for_rfence set to false. sbi_ipi_init() already checks riscv_ipi_have_virq_range(), so it only calls riscv_ipi_set_virq_range() when no other IPI device is available. This allows moving the static key and dropping the use_for_rfence parameter. This decouples the static key from the irqchip driver probe order. Furthermore, the static branch only makes sense when CONFIG_RISCV_SBI is enabled. Optherwise, IPIs must be used. Add a fallback definition of riscv_use_sbi_for_rfence() which handles this case and removes the need to check CONFIG_RISCV_SBI elsewhere, such as in cacheflush.c. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20240327045035.368512-4-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2024-04-29 10:49:26 -07:00
..
cache-ops.c	riscv: split cache ops out of dma-noncoherent.c	2023-11-07 09:37:42 -08:00
cacheflush.c	riscv: Use IPIs for remote cache/TLB flushes by default	2024-04-29 10:49:26 -07:00
context.c	membarrier: riscv: Add full memory barrier in switch_mm()	2024-02-15 08:04:11 -08:00
dma-noncoherent.c	iommu: Remove struct iommu_ops *iommu from arch_setup_dma_ops()	2023-12-12 10:18:45 +01:00
extable.c	riscv: select DCACHE_WORD_ACCESS for efficient unaligned access HW	2024-01-09 20:18:20 -08:00
fault.c	RISC-V Patches for the 6.8 Merge Window, Part 1	2024-01-17 10:50:46 -08:00
hugetlbpage.c	riscv: Fix build error if !CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION	2024-02-22 12:28:25 -08:00
init.c	RISC-V Patches for the 6.9 Merge Window	2024-03-22 10:41:13 -07:00
kasan_init.c	percpu:	2024-01-18 15:01:28 -08:00
Makefile	riscv: mm: Only compile pgtable.c if MMU	2023-12-20 10:48:14 -08:00
pageattr.c	Merge remote-tracking branch 'palmer/fixes' into for-next	2024-01-09 20:10:32 -08:00
pgtable.c	riscv: Only flush the mm icache when setting an exec pte	2024-03-20 08:56:08 -07:00
physaddr.c	riscv: Use PUD/P4D/PGD pages for the linear mapping	2023-04-18 20:43:04 -07:00
pmem.c	RISC-V: capitalise CMO op macros	2023-11-05 09:11:23 -08:00
ptdump.c	mm: ptdump: have ptdump_check_wx() return bool	2024-02-22 10:24:47 -08:00
tlbflush.c	riscv: Use IPIs for remote cache/TLB flushes by default	2024-04-29 10:49:26 -07:00