linux/arch/riscv
Samuel Holland dc892fb443
riscv: Use IPIs for remote cache/TLB flushes by default
An IPI backend is always required in an SMP configuration, but an SBI
implementation is not. For example, SBI will be unavailable when the
kernel runs in M mode. For this reason, consider IPI delivery of cache
and TLB flushes to be the base case, and any other implementation (such
as the SBI remote fence extension) to be an optimization.

Generally, if IPIs can be delivered without firmware assistance, they
are assumed to be faster than SBI calls due to the SBI context switch
overhead. However, when SBI is used as the IPI backend, then the context
switch cost must be paid anyway, and performing the cache/TLB flush
directly in the SBI implementation is more efficient than injecting an
interrupt to S-mode. This is the only existing scenario where
riscv_ipi_set_virq_range() is called with use_for_rfence set to false.

sbi_ipi_init() already checks riscv_ipi_have_virq_range(), so it only
calls riscv_ipi_set_virq_range() when no other IPI device is available.
This allows moving the static key and dropping the use_for_rfence
parameter. This decouples the static key from the irqchip driver probe
order.

Furthermore, the static branch only makes sense when CONFIG_RISCV_SBI is
enabled. Optherwise, IPIs must be used. Add a fallback definition of
riscv_use_sbi_for_rfence() which handles this case and removes the need
to check CONFIG_RISCV_SBI elsewhere, such as in cacheflush.c.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20240327045035.368512-4-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-04-29 10:49:26 -07:00
..
boot RISC-V Patches for the 6.9 Merge Window 2024-03-22 10:41:13 -07:00
configs RISC-V Patches for the 6.9 Merge Window 2024-03-22 10:41:13 -07:00
crypto crypto: riscv - add vector crypto accelerated AES-CBC-CTS 2024-03-20 08:56:11 -07:00
errata riscv: errata: Rename defines for Andes 2024-03-12 07:13:12 -07:00
include riscv: Use IPIs for remote cache/TLB flushes by default 2024-04-29 10:49:26 -07:00
kernel riscv: Use IPIs for remote cache/TLB flushes by default 2024-04-29 10:49:26 -07:00
kvm KVM/riscv changes for 6.9 2024-03-11 10:10:48 -04:00
lib RISC-V Patches for the 6.9 Merge Window 2024-03-22 10:41:13 -07:00
mm riscv: Use IPIs for remote cache/TLB flushes by default 2024-04-29 10:49:26 -07:00
net bpf, riscv64/cfi: Support kCFI + BPF on riscv64 2024-03-06 15:18:16 -08:00
purgatory riscv: Use SYM_*() assembly macros instead of deprecated ones 2023-11-06 09:42:47 -08:00
tools riscv: Check relocations at compile time 2023-04-19 07:46:32 -07:00
Kbuild RISC-V: hook new crypto subdir into build-system 2024-01-22 17:55:17 -08:00
Kconfig RISC-V Patches for the 6.9 Merge Window 2024-03-22 10:41:13 -07:00
Kconfig.debug riscv: Add tests for riscv module loading 2023-11-07 14:59:32 -08:00
Kconfig.errata RISC-V Patches for the 6.8 Merge Window, Part 4 2024-01-20 11:06:04 -08:00
Kconfig.socs riscv: dts: Move BUILTIN_DTB_SOURCE to common Kconfig 2024-03-06 00:08:32 +00:00
Makefile RISC-V: build: Allow LTO to be selected 2024-01-22 10:06:29 -08:00
Makefile.postlink kbuild: remove ARCH_POSTLINK from module builds 2023-10-28 21:10:08 +09:00