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9f2febf3f0
Restoration of the host IA32_SPEC_CTRL value is probably too late
with respect to the return thunk training sequence.
With respect to the user/kernel boundary, AMD says, "If software chooses
to toggle STIBP (e.g., set STIBP on kernel entry, and clear it on kernel
exit), software should set STIBP to 1 before executing the return thunk
training sequence." I assume the same requirements apply to the guest/host
boundary. The return thunk training sequence is in vmenter.S, quite close
to the VM-exit. On hosts without V_SPEC_CTRL, however, the host's
IA32_SPEC_CTRL value is not restored until much later.
To avoid this, move the restoration of host SPEC_CTRL to assembly and,
for consistency, move the restoration of the guest SPEC_CTRL as well.
This is not particularly difficult, apart from some care to cover both
32- and 64-bit, and to share code between SEV-ES and normal vmentry.
Cc: stable@vger.kernel.org
Fixes: a149180fbc ("x86: Add magic AMD return-thunk")
Suggested-by: Jim Mattson <jmattson@google.com>
Reviewed-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
390 lines
9.2 KiB
ArmAsm
390 lines
9.2 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/linkage.h>
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#include <asm/asm.h>
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#include <asm/bitsperlong.h>
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#include <asm/kvm_vcpu_regs.h>
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#include <asm/nospec-branch.h>
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#include "kvm-asm-offsets.h"
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#define WORD_SIZE (BITS_PER_LONG / 8)
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/* Intentionally omit RAX as it's context switched by hardware */
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#define VCPU_RCX (SVM_vcpu_arch_regs + __VCPU_REGS_RCX * WORD_SIZE)
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#define VCPU_RDX (SVM_vcpu_arch_regs + __VCPU_REGS_RDX * WORD_SIZE)
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#define VCPU_RBX (SVM_vcpu_arch_regs + __VCPU_REGS_RBX * WORD_SIZE)
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/* Intentionally omit RSP as it's context switched by hardware */
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#define VCPU_RBP (SVM_vcpu_arch_regs + __VCPU_REGS_RBP * WORD_SIZE)
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#define VCPU_RSI (SVM_vcpu_arch_regs + __VCPU_REGS_RSI * WORD_SIZE)
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#define VCPU_RDI (SVM_vcpu_arch_regs + __VCPU_REGS_RDI * WORD_SIZE)
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#ifdef CONFIG_X86_64
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#define VCPU_R8 (SVM_vcpu_arch_regs + __VCPU_REGS_R8 * WORD_SIZE)
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#define VCPU_R9 (SVM_vcpu_arch_regs + __VCPU_REGS_R9 * WORD_SIZE)
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#define VCPU_R10 (SVM_vcpu_arch_regs + __VCPU_REGS_R10 * WORD_SIZE)
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#define VCPU_R11 (SVM_vcpu_arch_regs + __VCPU_REGS_R11 * WORD_SIZE)
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#define VCPU_R12 (SVM_vcpu_arch_regs + __VCPU_REGS_R12 * WORD_SIZE)
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#define VCPU_R13 (SVM_vcpu_arch_regs + __VCPU_REGS_R13 * WORD_SIZE)
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#define VCPU_R14 (SVM_vcpu_arch_regs + __VCPU_REGS_R14 * WORD_SIZE)
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#define VCPU_R15 (SVM_vcpu_arch_regs + __VCPU_REGS_R15 * WORD_SIZE)
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#endif
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#define SVM_vmcb01_pa (SVM_vmcb01 + KVM_VMCB_pa)
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.section .noinstr.text, "ax"
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.macro RESTORE_GUEST_SPEC_CTRL
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/* No need to do anything if SPEC_CTRL is unset or V_SPEC_CTRL is set */
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ALTERNATIVE_2 "", \
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"jmp 800f", X86_FEATURE_MSR_SPEC_CTRL, \
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"", X86_FEATURE_V_SPEC_CTRL
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801:
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.endm
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.macro RESTORE_GUEST_SPEC_CTRL_BODY
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800:
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/*
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* SPEC_CTRL handling: if the guest's SPEC_CTRL value differs from the
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* host's, write the MSR. This is kept out-of-line so that the common
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* case does not have to jump.
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*
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* IMPORTANT: To avoid RSB underflow attacks and any other nastiness,
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* there must not be any returns or indirect branches between this code
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* and vmentry.
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*/
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movl SVM_spec_ctrl(%_ASM_DI), %eax
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cmp PER_CPU_VAR(x86_spec_ctrl_current), %eax
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je 801b
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mov $MSR_IA32_SPEC_CTRL, %ecx
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xor %edx, %edx
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wrmsr
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jmp 801b
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.endm
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.macro RESTORE_HOST_SPEC_CTRL
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/* No need to do anything if SPEC_CTRL is unset or V_SPEC_CTRL is set */
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ALTERNATIVE_2 "", \
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"jmp 900f", X86_FEATURE_MSR_SPEC_CTRL, \
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"", X86_FEATURE_V_SPEC_CTRL
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901:
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.endm
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.macro RESTORE_HOST_SPEC_CTRL_BODY
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900:
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/* Same for after vmexit. */
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mov $MSR_IA32_SPEC_CTRL, %ecx
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/*
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* Load the value that the guest had written into MSR_IA32_SPEC_CTRL,
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* if it was not intercepted during guest execution.
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*/
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cmpb $0, (%_ASM_SP)
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jnz 998f
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rdmsr
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movl %eax, SVM_spec_ctrl(%_ASM_DI)
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998:
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/* Now restore the host value of the MSR if different from the guest's. */
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movl PER_CPU_VAR(x86_spec_ctrl_current), %eax
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cmp SVM_spec_ctrl(%_ASM_DI), %eax
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je 901b
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xor %edx, %edx
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wrmsr
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jmp 901b
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.endm
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/**
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* __svm_vcpu_run - Run a vCPU via a transition to SVM guest mode
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* @svm: struct vcpu_svm *
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* @spec_ctrl_intercepted: bool
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*/
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SYM_FUNC_START(__svm_vcpu_run)
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push %_ASM_BP
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#ifdef CONFIG_X86_64
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push %r15
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push %r14
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push %r13
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push %r12
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#else
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push %edi
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push %esi
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#endif
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push %_ASM_BX
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/*
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* Save variables needed after vmexit on the stack, in inverse
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* order compared to when they are needed.
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*/
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/* Accessed directly from the stack in RESTORE_HOST_SPEC_CTRL. */
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push %_ASM_ARG2
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/* Needed to restore access to percpu variables. */
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__ASM_SIZE(push) PER_CPU_VAR(svm_data + SD_save_area_pa)
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/* Finally save @svm. */
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push %_ASM_ARG1
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.ifnc _ASM_ARG1, _ASM_DI
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/*
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* Stash @svm in RDI early. On 32-bit, arguments are in RAX, RCX
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* and RDX which are clobbered by RESTORE_GUEST_SPEC_CTRL.
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*/
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mov %_ASM_ARG1, %_ASM_DI
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.endif
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/* Clobbers RAX, RCX, RDX. */
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RESTORE_GUEST_SPEC_CTRL
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/*
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* Use a single vmcb (vmcb01 because it's always valid) for
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* context switching guest state via VMLOAD/VMSAVE, that way
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* the state doesn't need to be copied between vmcb01 and
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* vmcb02 when switching vmcbs for nested virtualization.
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*/
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mov SVM_vmcb01_pa(%_ASM_DI), %_ASM_AX
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1: vmload %_ASM_AX
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2:
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/* Get svm->current_vmcb->pa into RAX. */
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mov SVM_current_vmcb(%_ASM_DI), %_ASM_AX
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mov KVM_VMCB_pa(%_ASM_AX), %_ASM_AX
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/* Load guest registers. */
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mov VCPU_RCX(%_ASM_DI), %_ASM_CX
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mov VCPU_RDX(%_ASM_DI), %_ASM_DX
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mov VCPU_RBX(%_ASM_DI), %_ASM_BX
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mov VCPU_RBP(%_ASM_DI), %_ASM_BP
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mov VCPU_RSI(%_ASM_DI), %_ASM_SI
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#ifdef CONFIG_X86_64
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mov VCPU_R8 (%_ASM_DI), %r8
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mov VCPU_R9 (%_ASM_DI), %r9
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mov VCPU_R10(%_ASM_DI), %r10
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mov VCPU_R11(%_ASM_DI), %r11
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mov VCPU_R12(%_ASM_DI), %r12
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mov VCPU_R13(%_ASM_DI), %r13
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mov VCPU_R14(%_ASM_DI), %r14
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mov VCPU_R15(%_ASM_DI), %r15
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#endif
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mov VCPU_RDI(%_ASM_DI), %_ASM_DI
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/* Enter guest mode */
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sti
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3: vmrun %_ASM_AX
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4:
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cli
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/* Pop @svm to RAX while it's the only available register. */
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pop %_ASM_AX
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/* Save all guest registers. */
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mov %_ASM_CX, VCPU_RCX(%_ASM_AX)
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mov %_ASM_DX, VCPU_RDX(%_ASM_AX)
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mov %_ASM_BX, VCPU_RBX(%_ASM_AX)
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mov %_ASM_BP, VCPU_RBP(%_ASM_AX)
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mov %_ASM_SI, VCPU_RSI(%_ASM_AX)
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mov %_ASM_DI, VCPU_RDI(%_ASM_AX)
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#ifdef CONFIG_X86_64
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mov %r8, VCPU_R8 (%_ASM_AX)
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mov %r9, VCPU_R9 (%_ASM_AX)
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mov %r10, VCPU_R10(%_ASM_AX)
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mov %r11, VCPU_R11(%_ASM_AX)
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mov %r12, VCPU_R12(%_ASM_AX)
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mov %r13, VCPU_R13(%_ASM_AX)
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mov %r14, VCPU_R14(%_ASM_AX)
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mov %r15, VCPU_R15(%_ASM_AX)
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#endif
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/* @svm can stay in RDI from now on. */
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mov %_ASM_AX, %_ASM_DI
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mov SVM_vmcb01_pa(%_ASM_DI), %_ASM_AX
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5: vmsave %_ASM_AX
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6:
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/* Restores GSBASE among other things, allowing access to percpu data. */
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pop %_ASM_AX
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7: vmload %_ASM_AX
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8:
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#ifdef CONFIG_RETPOLINE
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/* IMPORTANT: Stuff the RSB immediately after VM-Exit, before RET! */
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FILL_RETURN_BUFFER %_ASM_AX, RSB_CLEAR_LOOPS, X86_FEATURE_RETPOLINE
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#endif
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/* Clobbers RAX, RCX, RDX. */
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RESTORE_HOST_SPEC_CTRL
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/*
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* Mitigate RETBleed for AMD/Hygon Zen uarch. RET should be
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* untrained as soon as we exit the VM and are back to the
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* kernel. This should be done before re-enabling interrupts
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* because interrupt handlers won't sanitize 'ret' if the return is
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* from the kernel.
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*/
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UNTRAIN_RET
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/*
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* Clear all general purpose registers except RSP and RAX to prevent
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* speculative use of the guest's values, even those that are reloaded
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* via the stack. In theory, an L1 cache miss when restoring registers
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* could lead to speculative execution with the guest's values.
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* Zeroing XORs are dirt cheap, i.e. the extra paranoia is essentially
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* free. RSP and RAX are exempt as they are restored by hardware
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* during VM-Exit.
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*/
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xor %ecx, %ecx
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xor %edx, %edx
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xor %ebx, %ebx
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xor %ebp, %ebp
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xor %esi, %esi
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xor %edi, %edi
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#ifdef CONFIG_X86_64
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xor %r8d, %r8d
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xor %r9d, %r9d
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xor %r10d, %r10d
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xor %r11d, %r11d
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xor %r12d, %r12d
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xor %r13d, %r13d
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xor %r14d, %r14d
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xor %r15d, %r15d
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#endif
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/* "Pop" @spec_ctrl_intercepted. */
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pop %_ASM_BX
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pop %_ASM_BX
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#ifdef CONFIG_X86_64
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pop %r12
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pop %r13
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pop %r14
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pop %r15
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#else
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pop %esi
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pop %edi
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#endif
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pop %_ASM_BP
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RET
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RESTORE_GUEST_SPEC_CTRL_BODY
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RESTORE_HOST_SPEC_CTRL_BODY
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10: cmpb $0, kvm_rebooting
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jne 2b
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ud2
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30: cmpb $0, kvm_rebooting
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jne 4b
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ud2
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50: cmpb $0, kvm_rebooting
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jne 6b
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ud2
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70: cmpb $0, kvm_rebooting
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jne 8b
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ud2
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_ASM_EXTABLE(1b, 10b)
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_ASM_EXTABLE(3b, 30b)
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_ASM_EXTABLE(5b, 50b)
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_ASM_EXTABLE(7b, 70b)
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SYM_FUNC_END(__svm_vcpu_run)
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/**
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* __svm_sev_es_vcpu_run - Run a SEV-ES vCPU via a transition to SVM guest mode
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* @svm: struct vcpu_svm *
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* @spec_ctrl_intercepted: bool
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*/
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SYM_FUNC_START(__svm_sev_es_vcpu_run)
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push %_ASM_BP
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#ifdef CONFIG_X86_64
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push %r15
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push %r14
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push %r13
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push %r12
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#else
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push %edi
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push %esi
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#endif
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push %_ASM_BX
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/*
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* Save variables needed after vmexit on the stack, in inverse
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* order compared to when they are needed.
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*/
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/* Accessed directly from the stack in RESTORE_HOST_SPEC_CTRL. */
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push %_ASM_ARG2
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/* Save @svm. */
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push %_ASM_ARG1
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.ifnc _ASM_ARG1, _ASM_DI
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/*
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* Stash @svm in RDI early. On 32-bit, arguments are in RAX, RCX
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* and RDX which are clobbered by RESTORE_GUEST_SPEC_CTRL.
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*/
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mov %_ASM_ARG1, %_ASM_DI
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.endif
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/* Clobbers RAX, RCX, RDX. */
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RESTORE_GUEST_SPEC_CTRL
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/* Get svm->current_vmcb->pa into RAX. */
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mov SVM_current_vmcb(%_ASM_DI), %_ASM_AX
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mov KVM_VMCB_pa(%_ASM_AX), %_ASM_AX
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/* Enter guest mode */
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sti
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1: vmrun %_ASM_AX
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2: cli
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/* Pop @svm to RDI, guest registers have been saved already. */
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pop %_ASM_DI
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#ifdef CONFIG_RETPOLINE
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/* IMPORTANT: Stuff the RSB immediately after VM-Exit, before RET! */
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FILL_RETURN_BUFFER %_ASM_AX, RSB_CLEAR_LOOPS, X86_FEATURE_RETPOLINE
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#endif
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/* Clobbers RAX, RCX, RDX. */
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RESTORE_HOST_SPEC_CTRL
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/*
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* Mitigate RETBleed for AMD/Hygon Zen uarch. RET should be
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* untrained as soon as we exit the VM and are back to the
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* kernel. This should be done before re-enabling interrupts
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* because interrupt handlers won't sanitize RET if the return is
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* from the kernel.
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*/
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UNTRAIN_RET
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/* "Pop" @spec_ctrl_intercepted. */
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pop %_ASM_BX
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pop %_ASM_BX
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#ifdef CONFIG_X86_64
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pop %r12
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pop %r13
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pop %r14
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pop %r15
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#else
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pop %esi
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pop %edi
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#endif
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pop %_ASM_BP
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RET
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RESTORE_GUEST_SPEC_CTRL_BODY
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RESTORE_HOST_SPEC_CTRL_BODY
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3: cmpb $0, kvm_rebooting
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jne 2b
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ud2
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_ASM_EXTABLE(1b, 3b)
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SYM_FUNC_END(__svm_sev_es_vcpu_run)
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