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x86: Add magic AMD return-thunk
Note: needs to be in a section distinct from Retpolines such that the Retpoline RET substitution cannot possibly use immediate jumps. ORC unwinding for zen_untrain_ret() and __x86_return_thunk() is a little tricky but works due to the fact that zen_untrain_ret() doesn't have any stack ops and as such will emit a single ORC entry at the start (+0x3f). Meanwhile, unwinding an IP, including the __x86_return_thunk() one (+0x40) will search for the largest ORC entry smaller or equal to the IP, these will find the one ORC entry (+0x3f) and all works. [ Alexandre: SVM part. ] [ bp: Build fix, massages. ] Suggested-by: Andrew Cooper <Andrew.Cooper3@citrix.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Josh Poimboeuf <jpoimboe@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
Peter Zijlstra
Borislav Petkov
parent
951ddecf43
commit
a149180fbc
@ -96,6 +96,7 @@ SYM_CODE_START(entry_SYSCALL_64)
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SYM_INNER_LABEL(entry_SYSCALL_64_safe_stack, SYM_L_GLOBAL)
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ANNOTATE_NOENDBR
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UNTRAIN_RET
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/* Construct struct pt_regs on stack */
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pushq $__USER_DS /* pt_regs->ss */
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@ -717,6 +718,7 @@ native_irq_return_ldt:
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pushq %rdi /* Stash user RDI */
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swapgs /* to kernel GS */
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */
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UNTRAIN_RET
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movq PER_CPU_VAR(espfix_waddr), %rdi
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movq %rax, (0*8)(%rdi) /* user RAX */
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@ -911,6 +913,7 @@ SYM_CODE_START_LOCAL(paranoid_entry)
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* be retrieved from a kernel internal table.
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*/
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SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
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UNTRAIN_RET
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/*
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* Handling GSBASE depends on the availability of FSGSBASE.
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@ -1020,6 +1023,7 @@ SYM_CODE_START_LOCAL(error_entry)
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FENCE_SWAPGS_USER_ENTRY
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/* We have user CR3. Change to kernel CR3. */
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
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UNTRAIN_RET
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leaq 8(%rsp), %rdi /* arg0 = pt_regs pointer */
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.Lerror_entry_from_usermode_after_swapgs:
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@ -1072,6 +1076,7 @@ SYM_CODE_START_LOCAL(error_entry)
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swapgs
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FENCE_SWAPGS_USER_ENTRY
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
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UNTRAIN_RET
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/*
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* Pretend that the exception came from user mode: set up pt_regs
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@ -1167,6 +1172,7 @@ SYM_CODE_START(asm_exc_nmi)
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movq %rsp, %rdx
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movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
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UNWIND_HINT_IRET_REGS base=%rdx offset=8
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UNTRAIN_RET
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pushq 5*8(%rdx) /* pt_regs->ss */
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pushq 4*8(%rdx) /* pt_regs->rsp */
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pushq 3*8(%rdx) /* pt_regs->flags */
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@ -14,6 +14,7 @@
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#include <asm/irqflags.h>
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#include <asm/asm.h>
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#include <asm/smap.h>
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#include <asm/nospec-branch.h>
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#include <linux/linkage.h>
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#include <linux/err.h>
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@ -72,6 +73,7 @@ SYM_CODE_START(entry_SYSENTER_compat)
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pushq $__USER32_CS /* pt_regs->cs */
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pushq $0 /* pt_regs->ip = 0 (placeholder) */
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SYM_INNER_LABEL(entry_SYSENTER_compat_after_hwframe, SYM_L_GLOBAL)
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UNTRAIN_RET
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/*
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* User tracing code (ptrace or signal handlers) might assume that
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@ -190,6 +192,7 @@ SYM_CODE_START(entry_SYSCALL_compat)
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SYM_INNER_LABEL(entry_SYSCALL_compat_safe_stack, SYM_L_GLOBAL)
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ANNOTATE_NOENDBR
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UNTRAIN_RET
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/* Construct struct pt_regs on stack */
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pushq $__USER32_DS /* pt_regs->ss */
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@ -332,6 +335,7 @@ SYM_CODE_START(entry_INT80_compat)
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pushq 0*8(%rax) /* regs->orig_ax */
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.Lint80_keep_stack:
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UNTRAIN_RET
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PUSH_AND_CLEAR_REGS rax=$-ENOSYS
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UNWIND_HINT_REGS
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@ -301,6 +301,7 @@
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#define X86_FEATURE_RETPOLINE (11*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
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#define X86_FEATURE_RETPOLINE_LFENCE (11*32+13) /* "" Use LFENCE for Spectre variant 2 */
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#define X86_FEATURE_RETHUNK (11*32+14) /* "" Use REturn THUNK */
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#define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */
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/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
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#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
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@ -55,7 +55,8 @@
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#else
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# define DISABLE_RETPOLINE ((1 << (X86_FEATURE_RETPOLINE & 31)) | \
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(1 << (X86_FEATURE_RETPOLINE_LFENCE & 31)) | \
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(1 << (X86_FEATURE_RETHUNK & 31)))
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(1 << (X86_FEATURE_RETHUNK & 31)) | \
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(1 << (X86_FEATURE_UNRET & 31)))
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#endif
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#ifdef CONFIG_INTEL_IOMMU_SVM
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@ -112,6 +112,22 @@
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#endif
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.endm
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/*
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* Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the
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* return thunk isn't mapped into the userspace tables (then again, AMD
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* typically has NO_MELTDOWN).
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*
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* Doesn't clobber any registers but does require a stable stack.
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*
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* As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point
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* where we have a stack but before any RET instruction.
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*/
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.macro UNTRAIN_RET
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#ifdef CONFIG_RETPOLINE
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ALTERNATIVE "", "call zen_untrain_ret", X86_FEATURE_UNRET
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#endif
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.endm
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#else /* __ASSEMBLY__ */
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#define ANNOTATE_RETPOLINE_SAFE \
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@ -124,6 +140,7 @@ typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE];
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extern retpoline_thunk_t __x86_indirect_thunk_array[];
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extern void __x86_return_thunk(void);
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extern void zen_untrain_ret(void);
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#ifdef CONFIG_RETPOLINE
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@ -141,7 +141,7 @@ SECTIONS
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#ifdef CONFIG_RETPOLINE
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__indirect_thunk_start = .;
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*(.text.__x86.indirect_thunk)
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*(.text.__x86.*)
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__indirect_thunk_end = .;
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#endif
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} :text =0xcccc
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@ -110,6 +110,15 @@ SYM_FUNC_START(__svm_vcpu_run)
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mov %r15, VCPU_R15(%_ASM_AX)
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#endif
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/*
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* Mitigate RETBleed for AMD/Hygon Zen uarch. RET should be
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* untrained as soon as we exit the VM and are back to the
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* kernel. This should be done before re-enabling interrupts
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* because interrupt handlers won't sanitize 'ret' if the return is
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* from the kernel.
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*/
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UNTRAIN_RET
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/*
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* Clear all general purpose registers except RSP and RAX to prevent
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* speculative use of the guest's values, even those that are reloaded
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@ -190,6 +199,15 @@ SYM_FUNC_START(__svm_sev_es_vcpu_run)
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FILL_RETURN_BUFFER %_ASM_AX, RSB_CLEAR_LOOPS, X86_FEATURE_RETPOLINE
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#endif
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/*
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* Mitigate RETBleed for AMD/Hygon Zen uarch. RET should be
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* untrained as soon as we exit the VM and are back to the
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* kernel. This should be done before re-enabling interrupts
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* because interrupt handlers won't sanitize RET if the return is
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* from the kernel.
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*/
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UNTRAIN_RET
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pop %_ASM_BX
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#ifdef CONFIG_X86_64
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@ -72,11 +72,67 @@ SYM_CODE_END(__x86_indirect_thunk_array)
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* This function name is magical and is used by -mfunction-return=thunk-extern
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* for the compiler to generate JMPs to it.
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*/
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SYM_CODE_START(__x86_return_thunk)
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UNWIND_HINT_EMPTY
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ANNOTATE_NOENDBR
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.section .text.__x86.return_thunk
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/*
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* Safety details here pertain to the AMD Zen{1,2} microarchitecture:
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* 1) The RET at __x86_return_thunk must be on a 64 byte boundary, for
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* alignment within the BTB.
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* 2) The instruction at zen_untrain_ret must contain, and not
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* end with, the 0xc3 byte of the RET.
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* 3) STIBP must be enabled, or SMT disabled, to prevent the sibling thread
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* from re-poisioning the BTB prediction.
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*/
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.align 64
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.skip 63, 0xcc
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SYM_FUNC_START_NOALIGN(zen_untrain_ret);
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/*
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* As executed from zen_untrain_ret, this is:
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*
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* TEST $0xcc, %bl
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* LFENCE
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* JMP __x86_return_thunk
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*
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* Executing the TEST instruction has a side effect of evicting any BTB
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* prediction (potentially attacker controlled) attached to the RET, as
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* __x86_return_thunk + 1 isn't an instruction boundary at the moment.
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*/
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.byte 0xf6
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/*
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* As executed from __x86_return_thunk, this is a plain RET.
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*
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* As part of the TEST above, RET is the ModRM byte, and INT3 the imm8.
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*
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* We subsequently jump backwards and architecturally execute the RET.
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* This creates a correct BTB prediction (type=ret), but in the
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* meantime we suffer Straight Line Speculation (because the type was
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* no branch) which is halted by the INT3.
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*
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* With SMT enabled and STIBP active, a sibling thread cannot poison
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* RET's prediction to a type of its choice, but can evict the
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* prediction due to competitive sharing. If the prediction is
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* evicted, __x86_return_thunk will suffer Straight Line Speculation
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* which will be contained safely by the INT3.
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*/
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SYM_INNER_LABEL(__x86_return_thunk, SYM_L_GLOBAL)
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ret
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int3
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SYM_CODE_END(__x86_return_thunk)
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__EXPORT_THUNK(__x86_return_thunk)
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/*
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* Ensure the TEST decoding / BTB invalidation is complete.
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*/
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lfence
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/*
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* Jump back and execute the RET in the middle of the TEST instruction.
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* INT3 is for SLS protection.
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*/
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jmp __x86_return_thunk
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int3
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SYM_FUNC_END(zen_untrain_ret)
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__EXPORT_THUNK(zen_untrain_ret)
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EXPORT_SYMBOL(__x86_return_thunk)
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@ -1302,7 +1302,7 @@ static void add_retpoline_call(struct objtool_file *file, struct instruction *in
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annotate_call_site(file, insn, false);
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}
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static void add_return_call(struct objtool_file *file, struct instruction *insn)
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static void add_return_call(struct objtool_file *file, struct instruction *insn, bool add)
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{
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/*
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* Return thunk tail calls are really just returns in disguise,
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@ -1311,7 +1311,8 @@ static void add_return_call(struct objtool_file *file, struct instruction *insn)
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insn->type = INSN_RETURN;
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insn->retpoline_safe = true;
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list_add_tail(&insn->call_node, &file->return_thunk_list);
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if (add)
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list_add_tail(&insn->call_node, &file->return_thunk_list);
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}
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static bool same_function(struct instruction *insn1, struct instruction *insn2)
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@ -1367,7 +1368,7 @@ static int add_jump_destinations(struct objtool_file *file)
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add_retpoline_call(file, insn);
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continue;
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} else if (reloc->sym->return_thunk) {
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add_return_call(file, insn);
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add_return_call(file, insn, true);
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continue;
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} else if (insn->func) {
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/*
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@ -1387,6 +1388,21 @@ static int add_jump_destinations(struct objtool_file *file)
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jump_dest = find_insn(file, dest_sec, dest_off);
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if (!jump_dest) {
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struct symbol *sym = find_symbol_by_offset(dest_sec, dest_off);
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/*
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* This is a special case for zen_untrain_ret().
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* It jumps to __x86_return_thunk(), but objtool
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* can't find the thunk's starting RET
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* instruction, because the RET is also in the
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* middle of another instruction. Objtool only
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* knows about the outer instruction.
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*/
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if (sym && sym->return_thunk) {
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add_return_call(file, insn, false);
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continue;
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}
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WARN_FUNC("can't find jump dest instruction at %s+0x%lx",
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insn->sec, insn->offset, dest_sec->name,
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dest_off);
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