Dan Williams c1915142e8 tools/testing/cxl: Mock one level of switches ... The CXL port enumeration process adds intermediate CXL ports that are discovered between "root" CXL ports enumerated by 'cxl_acpi' and endpoints enumerated by 'cxl_pci + cxl_mem'. Test the dynamic discovery of intermediate switch ports in a CXL topology. Link: https://lore.kernel.org/r/164298432189.3018233.13142151550113000967.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2022-02-08 22:57:33 -08:00
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test	tools/testing/cxl: Mock one level of switches	2022-02-08 22:57:33 -08:00
config_check.c
Kbuild	cxl/mem: Add the cxl_mem driver	2022-02-08 22:57:32 -08:00
mock_acpi.c	cxl/core: Generalize dport enumeration in the core	2022-02-08 22:57:30 -08:00
mock_mem.c	cxl/mem: Add the cxl_mem driver	2022-02-08 22:57:32 -08:00