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tools/testing/cxl: Mock one level of switches
The CXL port enumeration process adds intermediate CXL ports that are discovered between "root" CXL ports enumerated by 'cxl_acpi' and endpoints enumerated by 'cxl_pci + cxl_mem'. Test the dynamic discovery of intermediate switch ports in a CXL topology. Link: https://lore.kernel.org/r/164298432189.3018233.13142151550113000967.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams
parent
a4a0ce242f
commit
c1915142e8
@ -11,14 +11,21 @@
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#include <cxlmem.h>
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#include "mock.h"
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#define NR_CXL_HOST_BRIDGES 4
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#define NR_CXL_HOST_BRIDGES 2
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#define NR_CXL_ROOT_PORTS 2
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#define NR_CXL_SWITCH_PORTS 2
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static struct platform_device *cxl_acpi;
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static struct platform_device *cxl_host_bridge[NR_CXL_HOST_BRIDGES];
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static struct platform_device
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*cxl_root_port[NR_CXL_HOST_BRIDGES * NR_CXL_ROOT_PORTS];
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struct platform_device *cxl_mem[NR_CXL_HOST_BRIDGES * NR_CXL_ROOT_PORTS];
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static struct platform_device
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*cxl_switch_uport[NR_CXL_HOST_BRIDGES * NR_CXL_ROOT_PORTS];
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static struct platform_device
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*cxl_switch_dport[NR_CXL_HOST_BRIDGES * NR_CXL_ROOT_PORTS *
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NR_CXL_SWITCH_PORTS];
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struct platform_device
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*cxl_mem[NR_CXL_HOST_BRIDGES * NR_CXL_ROOT_PORTS * NR_CXL_SWITCH_PORTS];
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static struct acpi_device acpi0017_mock;
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static struct acpi_device host_bridge[NR_CXL_HOST_BRIDGES] = {
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@ -28,12 +35,6 @@ static struct acpi_device host_bridge[NR_CXL_HOST_BRIDGES] = {
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[1] = {
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.handle = &host_bridge[1],
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},
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[2] = {
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.handle = &host_bridge[2],
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},
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[3] = {
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.handle = &host_bridge[3],
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},
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};
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static bool is_mock_dev(struct device *dev)
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@ -71,7 +72,7 @@ static struct {
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} cfmws0;
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struct {
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struct acpi_cedt_cfmws cfmws;
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u32 target[4];
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u32 target[2];
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} cfmws1;
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struct {
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struct acpi_cedt_cfmws cfmws;
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@ -79,7 +80,7 @@ static struct {
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} cfmws2;
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struct {
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struct acpi_cedt_cfmws cfmws;
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u32 target[4];
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u32 target[2];
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} cfmws3;
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} __packed mock_cedt = {
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.cedt = {
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@ -105,22 +106,6 @@ static struct {
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.uid = 1,
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.cxl_version = ACPI_CEDT_CHBS_VERSION_CXL20,
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},
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.chbs[2] = {
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.header = {
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.type = ACPI_CEDT_TYPE_CHBS,
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.length = sizeof(mock_cedt.chbs[0]),
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},
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.uid = 2,
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.cxl_version = ACPI_CEDT_CHBS_VERSION_CXL20,
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},
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.chbs[3] = {
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.header = {
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.type = ACPI_CEDT_TYPE_CHBS,
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.length = sizeof(mock_cedt.chbs[0]),
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},
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.uid = 3,
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.cxl_version = ACPI_CEDT_CHBS_VERSION_CXL20,
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},
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.cfmws0 = {
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.cfmws = {
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.header = {
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@ -142,14 +127,14 @@ static struct {
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.type = ACPI_CEDT_TYPE_CFMWS,
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.length = sizeof(mock_cedt.cfmws1),
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},
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.interleave_ways = 2,
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.interleave_ways = 1,
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.granularity = 4,
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.restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
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ACPI_CEDT_CFMWS_RESTRICT_VOLATILE,
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.qtg_id = 1,
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.window_size = SZ_256M * 4,
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.window_size = SZ_256M * 2,
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},
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.target = { 0, 1, 2, 3 },
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.target = { 0, 1, },
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},
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.cfmws2 = {
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.cfmws = {
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@ -172,14 +157,14 @@ static struct {
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.type = ACPI_CEDT_TYPE_CFMWS,
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.length = sizeof(mock_cedt.cfmws3),
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},
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.interleave_ways = 2,
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.interleave_ways = 1,
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.granularity = 4,
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.restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
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ACPI_CEDT_CFMWS_RESTRICT_PMEM,
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.qtg_id = 3,
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.window_size = SZ_256M * 4,
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.window_size = SZ_256M * 2,
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},
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.target = { 0, 1, 2, 3 },
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.target = { 0, 1, },
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},
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};
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@ -332,6 +317,17 @@ static bool is_mock_port(struct device *dev)
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if (dev == &cxl_root_port[i]->dev)
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return true;
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for (i = 0; i < ARRAY_SIZE(cxl_switch_uport); i++)
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if (dev == &cxl_switch_uport[i]->dev)
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return true;
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for (i = 0; i < ARRAY_SIZE(cxl_switch_dport); i++)
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if (dev == &cxl_switch_dport[i]->dev)
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return true;
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if (is_cxl_memdev(dev))
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return is_mock_dev(dev->parent);
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return false;
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}
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@ -372,12 +368,6 @@ static struct acpi_pci_root mock_pci_root[NR_CXL_HOST_BRIDGES] = {
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[1] = {
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.bus = &mock_pci_bus[1],
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},
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[2] = {
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.bus = &mock_pci_bus[2],
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},
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[3] = {
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.bus = &mock_pci_bus[3],
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},
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};
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static bool is_mock_bus(struct pci_bus *bus)
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@ -446,6 +436,26 @@ static int mock_cxl_port_enumerate_dports(struct cxl_port *port)
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dev_name(&pdev->dev));
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}
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for (i = 0; i < ARRAY_SIZE(cxl_switch_dport); i++) {
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struct platform_device *pdev = cxl_switch_dport[i];
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struct cxl_dport *dport;
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if (pdev->dev.parent != port->uport)
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continue;
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dport = devm_cxl_add_dport(port, &pdev->dev, pdev->id,
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CXL_RESOURCE_NONE);
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if (IS_ERR(dport)) {
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dev_err(dev, "failed to add dport: %s (%ld)\n",
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dev_name(&pdev->dev), PTR_ERR(dport));
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return PTR_ERR(dport);
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}
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dev_dbg(dev, "add dport%d: %s\n", pdev->id,
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dev_name(&pdev->dev));
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}
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return 0;
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}
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@ -574,15 +584,51 @@ static __init int cxl_test_init(void)
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cxl_root_port[i] = pdev;
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}
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BUILD_BUG_ON(ARRAY_SIZE(cxl_mem) != ARRAY_SIZE(cxl_root_port));
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BUILD_BUG_ON(ARRAY_SIZE(cxl_switch_uport) != ARRAY_SIZE(cxl_root_port));
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for (i = 0; i < ARRAY_SIZE(cxl_switch_uport); i++) {
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struct platform_device *root_port = cxl_root_port[i];
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struct platform_device *pdev;
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pdev = platform_device_alloc("cxl_switch_uport", i);
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if (!pdev)
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goto err_port;
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pdev->dev.parent = &root_port->dev;
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rc = platform_device_add(pdev);
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if (rc) {
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platform_device_put(pdev);
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goto err_uport;
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}
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cxl_switch_uport[i] = pdev;
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}
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for (i = 0; i < ARRAY_SIZE(cxl_switch_dport); i++) {
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struct platform_device *uport =
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cxl_switch_uport[i % ARRAY_SIZE(cxl_switch_uport)];
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struct platform_device *pdev;
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pdev = platform_device_alloc("cxl_switch_dport", i);
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if (!pdev)
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goto err_port;
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pdev->dev.parent = &uport->dev;
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rc = platform_device_add(pdev);
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if (rc) {
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platform_device_put(pdev);
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goto err_dport;
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}
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cxl_switch_dport[i] = pdev;
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}
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BUILD_BUG_ON(ARRAY_SIZE(cxl_mem) != ARRAY_SIZE(cxl_switch_dport));
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for (i = 0; i < ARRAY_SIZE(cxl_mem); i++) {
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struct platform_device *port = cxl_root_port[i];
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struct platform_device *dport = cxl_switch_dport[i];
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struct platform_device *pdev;
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pdev = alloc_memdev(i);
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if (!pdev)
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goto err_mem;
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pdev->dev.parent = &port->dev;
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pdev->dev.parent = &dport->dev;
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set_dev_node(&pdev->dev, i % 2);
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rc = platform_device_add(pdev);
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@ -611,6 +657,12 @@ err_add:
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err_mem:
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for (i = ARRAY_SIZE(cxl_mem) - 1; i >= 0; i--)
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platform_device_unregister(cxl_mem[i]);
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err_dport:
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for (i = ARRAY_SIZE(cxl_switch_dport) - 1; i >= 0; i--)
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platform_device_unregister(cxl_switch_dport[i]);
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err_uport:
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for (i = ARRAY_SIZE(cxl_switch_uport) - 1; i >= 0; i--)
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platform_device_unregister(cxl_switch_uport[i]);
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err_port:
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for (i = ARRAY_SIZE(cxl_root_port) - 1; i >= 0; i--)
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platform_device_unregister(cxl_root_port[i]);
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@ -633,6 +685,10 @@ static __exit void cxl_test_exit(void)
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platform_device_unregister(cxl_acpi);
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for (i = ARRAY_SIZE(cxl_mem) - 1; i >= 0; i--)
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platform_device_unregister(cxl_mem[i]);
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for (i = ARRAY_SIZE(cxl_switch_dport) - 1; i >= 0; i--)
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platform_device_unregister(cxl_switch_dport[i]);
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for (i = ARRAY_SIZE(cxl_switch_uport) - 1; i >= 0; i--)
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platform_device_unregister(cxl_switch_uport[i]);
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for (i = ARRAY_SIZE(cxl_root_port) - 1; i >= 0; i--)
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platform_device_unregister(cxl_root_port[i]);
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for (i = ARRAY_SIZE(cxl_host_bridge) - 1; i >= 0; i--)
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