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5b22c33e8e
Numerous updates to the various Tegra device trees are made: * Addition of NVIDIA Beaver (Tegra30) and Toradex Colibri T20 and Iris carrier boards. * Enablement of the HDMI connector on most boards. * Enablement of the keyboard controller on a few boards. * Addition of the AC'97 controller to Tegra20. * Addition of a GPIO poweroff node for TrimSlice. * Changes to support the new "high speed UART" (DMA-capable) driver for Tegra serial ports, and enablement for Cardhu's UART C. * A few cleanups, such as compatible flag fixes, node renames, node ordering fixes, commonizing properties into SoC .dtsi files, etc.. This pull request is based on (most of) the previous pull request with tag tegra-for-3.9-soc-t114. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRCY++AAoJEMzrak5tbycx6BMQALRuxbStMPDVBmOp65kF8B/s u8wynnbL1qs6dJ81LW9IcVCEqzsR/7tfda9h4p+SPnihF4OxLMYyG95qzK0rR+ZR pA+yIhRQjEq4q4+TgvHNblpSGN1wguLVC/FmN7kpJlSI6IMQsK3iQmPEsUE4gSfK aaCwWaFuUUed7B6gpzJY6pX5C7H4EkwJZxOGBmr/houuoaEKz0vjGY8KaSwBd9RZ oACibtHbhvkkYY6LCkBHSWNHAcwpMZRw+b0SDQ5ephShPK4gMGC44lwTz4RFJawS pgZVYOUpb5OFivZFPKqXglCNe3PMwNgb9ntFm7UU//99ibQiGGB49oIkDL2HJx1g KKeyEOZLN+h0CbgxDu5p2ItCcID1Z5CzD/ryqE7ofFx1iQrUc7b0RsIlM9chUjei xumU5rQJRxwNIvyvYu+zvuV3J7luSe9W+2teXkvKccAwmr1YIbwQeFPGYgkchFOz efKhESGVaoUMKdVyg09nPkDRpM/NwHkxcPCga7ypOJl9oKU3B6t5mmMxI9+sUxet iYL50iDBoulHtBDlCFjYfjnq1Go9sCE+fXxGaWJ5Yec3qsB9zhHDE72hZ3NF1tWj 3YWq5dhyAYz90N6RUhXBHfWvZ4a188Z3tPAUt3C/TUQ9dttzZqkRsCnu7A5nAKyN f9Ul9sK48KSub5+Zb7+7 =UMMs -----END PGP SIGNATURE----- Merge tag 'tegra-for-3.9-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt From Stephen Warren: ARM: tegra: device tree updates Numerous updates to the various Tegra device trees are made: * Addition of NVIDIA Beaver (Tegra30) and Toradex Colibri T20 and Iris carrier boards. * Enablement of the HDMI connector on most boards. * Enablement of the keyboard controller on a few boards. * Addition of the AC'97 controller to Tegra20. * Addition of a GPIO poweroff node for TrimSlice. * Changes to support the new "high speed UART" (DMA-capable) driver for Tegra serial ports, and enablement for Cardhu's UART C. * A few cleanups, such as compatible flag fixes, node renames, node ordering fixes, commonizing properties into SoC .dtsi files, etc.. This pull request is based on (most of) the previous pull request with tag tegra-for-3.9-soc-t114. * tag 'tegra-for-3.9-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (22 commits) ARM: dt: tegra30: Rename "smmu" to "iommu" ARM: dt: tegra20: Rename "gart" to "iommu" ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi ARM: tegra: Add Toradex Iris carrier board DT with T20 512MB COM ARM: tegra: Add Colibri T20 512MB COM device tree ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsi ARM: tegra: harmony: enable keyboard in DT ARM: tegra: whistler: enable keyboard in DT ARM: tegra: cardhu: register UARTC ARM: tegra: seaboard: enable keyboard in DT ARM: tegra: add DT entry for KBC controller ARM: tegra: swap cache-/interrupt-ctrlr nodes in DT ASoC: tegra: add ac97 host controller to device tree ARM: DT: tegra: Add Tegra30 Beaver board support ARM: DT: tegra: Add board level compatible properties ARM: tegra: paz00: enable HDMI port ARM: tegra: ventana: enable HDMI port ARM: tegra: seaboard: enable HDMI port ARM: tegra: trimslice: add gpio-poweroff node to DT ARM: DT: tegra: Unify the description of Tegra20 boards ...
368 lines
7.4 KiB
Plaintext
368 lines
7.4 KiB
Plaintext
/dts-v1/;
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/include/ "tegra20.dtsi"
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/ {
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model = "Compulab TrimSlice board";
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compatible = "compulab,trimslice", "nvidia,tegra20";
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memory {
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reg = <0x00000000 0x40000000>;
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};
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host1x {
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hdmi {
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status = "okay";
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vdd-supply = <&hdmi_vdd_reg>;
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pll-supply = <&hdmi_pll_reg>;
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nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
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};
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};
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pinmux {
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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ata {
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nvidia,pins = "ata";
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nvidia,function = "ide";
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};
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atb {
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nvidia,pins = "atb", "gma";
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nvidia,function = "sdio4";
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};
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atc {
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nvidia,pins = "atc", "gmb";
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nvidia,function = "nand";
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};
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atd {
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nvidia,pins = "atd", "ate", "gme", "pta";
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nvidia,function = "gmi";
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};
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cdev1 {
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nvidia,pins = "cdev1";
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nvidia,function = "plla_out";
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};
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cdev2 {
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nvidia,pins = "cdev2";
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nvidia,function = "pllp_out4";
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};
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crtp {
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nvidia,pins = "crtp";
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nvidia,function = "crt";
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};
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csus {
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nvidia,pins = "csus";
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nvidia,function = "vi_sensor_clk";
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};
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dap1 {
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nvidia,pins = "dap1";
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nvidia,function = "dap1";
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};
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dap2 {
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nvidia,pins = "dap2";
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nvidia,function = "dap2";
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};
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dap3 {
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nvidia,pins = "dap3";
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nvidia,function = "dap3";
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};
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dap4 {
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nvidia,pins = "dap4";
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nvidia,function = "dap4";
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};
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ddc {
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nvidia,pins = "ddc";
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nvidia,function = "i2c2";
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};
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dta {
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nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
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nvidia,function = "vi";
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};
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dtf {
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nvidia,pins = "dtf";
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nvidia,function = "i2c3";
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};
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gmc {
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nvidia,pins = "gmc", "gmd";
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nvidia,function = "sflash";
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};
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gpu {
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nvidia,pins = "gpu";
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nvidia,function = "uarta";
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};
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gpu7 {
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nvidia,pins = "gpu7";
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nvidia,function = "rtck";
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};
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gpv {
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nvidia,pins = "gpv", "slxa", "slxk";
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nvidia,function = "pcie";
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};
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hdint {
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nvidia,pins = "hdint";
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nvidia,function = "hdmi";
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};
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i2cp {
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nvidia,pins = "i2cp";
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nvidia,function = "i2cp";
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};
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irrx {
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nvidia,pins = "irrx", "irtx";
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nvidia,function = "uartb";
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};
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kbca {
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nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
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"kbce", "kbcf";
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nvidia,function = "kbc";
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};
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lcsn {
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nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
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"ld3", "ld4", "ld5", "ld6", "ld7",
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"ld8", "ld9", "ld10", "ld11", "ld12",
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"ld13", "ld14", "ld15", "ld16", "ld17",
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"ldc", "ldi", "lhp0", "lhp1", "lhp2",
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"lhs", "lm0", "lm1", "lpp", "lpw0",
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"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
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"lsda", "lsdi", "lspi", "lvp0", "lvp1",
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"lvs";
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nvidia,function = "displaya";
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};
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owc {
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nvidia,pins = "owc", "uac";
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nvidia,function = "rsvd2";
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};
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pmc {
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nvidia,pins = "pmc";
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nvidia,function = "pwr_on";
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};
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rm {
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nvidia,pins = "rm";
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nvidia,function = "i2c1";
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};
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sdb {
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nvidia,pins = "sdb", "sdc", "sdd";
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nvidia,function = "pwm";
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};
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sdio1 {
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nvidia,pins = "sdio1";
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nvidia,function = "sdio1";
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};
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slxc {
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nvidia,pins = "slxc", "slxd";
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nvidia,function = "sdio3";
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};
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spdi {
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nvidia,pins = "spdi", "spdo";
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nvidia,function = "spdif";
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};
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spia {
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nvidia,pins = "spia", "spib", "spic";
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nvidia,function = "spi2";
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};
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spid {
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nvidia,pins = "spid", "spie", "spif";
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nvidia,function = "spi1";
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};
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spig {
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nvidia,pins = "spig", "spih";
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nvidia,function = "spi2_alt";
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};
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uaa {
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nvidia,pins = "uaa", "uab", "uda";
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nvidia,function = "ulpi";
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};
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uad {
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nvidia,pins = "uad";
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nvidia,function = "irda";
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};
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uca {
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nvidia,pins = "uca", "ucb";
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nvidia,function = "uartc";
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};
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conf_ata {
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nvidia,pins = "ata", "atc", "atd", "ate",
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"crtp", "dap2", "dap3", "dap4", "dta",
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"dtb", "dtc", "dtd", "dte", "gmb",
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"gme", "i2cp", "pta", "slxc", "slxd",
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"spdi", "spdo", "uda";
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nvidia,pull = <0>;
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nvidia,tristate = <1>;
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};
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conf_atb {
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nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
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"gma", "gmc", "gmd", "gpu", "gpu7",
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"gpv", "sdio1", "slxa", "slxk", "uac";
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nvidia,pull = <0>;
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nvidia,tristate = <0>;
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};
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conf_ck32 {
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nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
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"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
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nvidia,pull = <0>;
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};
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conf_csus {
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nvidia,pins = "csus", "spia", "spib",
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"spid", "spif";
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nvidia,pull = <1>;
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nvidia,tristate = <1>;
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};
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conf_ddc {
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nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
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nvidia,pull = <2>;
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nvidia,tristate = <0>;
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};
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conf_hdint {
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nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
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"lpw1", "lsc1", "lsck", "lsda", "lsdi",
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"lvp0", "pmc";
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nvidia,tristate = <1>;
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};
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conf_irrx {
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nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
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"kbcc", "kbcd", "kbce", "kbcf", "owc",
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"spic", "spie", "spig", "spih", "uaa",
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"uab", "uad", "uca", "ucb";
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nvidia,pull = <2>;
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nvidia,tristate = <1>;
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};
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conf_lc {
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nvidia,pins = "lc", "ls";
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nvidia,pull = <2>;
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};
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conf_ld0 {
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nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
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"ld5", "ld6", "ld7", "ld8", "ld9",
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"ld10", "ld11", "ld12", "ld13", "ld14",
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"ld15", "ld16", "ld17", "ldi", "lhp0",
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"lhp1", "lhp2", "lhs", "lm0", "lpp",
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"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
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"lvs", "sdb";
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nvidia,tristate = <0>;
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};
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conf_ld17_0 {
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nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
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"ld23_22";
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nvidia,pull = <1>;
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};
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conf_spif {
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nvidia,pins = "spif";
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nvidia,pull = <1>;
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nvidia,tristate = <0>;
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};
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};
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};
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i2s@70002800 {
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status = "okay";
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};
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serial@70006000 {
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status = "okay";
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};
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dvi_ddc: i2c@7000c000 {
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status = "okay";
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clock-frequency = <100000>;
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};
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spi@7000c380 {
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status = "okay";
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spi-max-frequency = <48000000>;
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spi-flash@0 {
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compatible = "winbond,w25q80bl";
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reg = <0>;
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spi-max-frequency = <48000000>;
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};
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};
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hdmi_ddc: i2c@7000c400 {
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status = "okay";
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clock-frequency = <100000>;
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};
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i2c@7000c500 {
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status = "okay";
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clock-frequency = <400000>;
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codec: codec@1a {
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compatible = "ti,tlv320aic23";
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reg = <0x1a>;
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};
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rtc@56 {
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compatible = "emmicro,em3027";
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reg = <0x56>;
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};
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};
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usb@c5000000 {
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status = "okay";
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nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
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};
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usb@c5004000 {
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status = "okay";
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nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
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};
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usb@c5008000 {
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status = "okay";
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};
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usb-phy@c5004400 {
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nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
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};
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sdhci@c8000000 {
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status = "okay";
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bus-width = <4>;
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};
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sdhci@c8000600 {
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status = "okay";
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cd-gpios = <&gpio 121 0>; /* gpio PP1 */
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wp-gpios = <&gpio 122 0>; /* gpio PP2 */
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bus-width = <4>;
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};
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poweroff {
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compatible = "gpio-poweroff";
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gpios = <&gpio 191 1>; /* gpio PX7, active low */
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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hdmi_vdd_reg: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "avdd_hdmi";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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hdmi_pll_reg: regulator@1 {
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compatible = "regulator-fixed";
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reg = <1>;
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regulator-name = "avdd_hdmi_pll";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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};
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sound {
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compatible = "nvidia,tegra-audio-trimslice";
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nvidia,i2s-controller = <&tegra_i2s1>;
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nvidia,audio-codec = <&codec>;
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};
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};
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