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ARM: tegra: device tree updates
Numerous updates to the various Tegra device trees are made: * Addition of NVIDIA Beaver (Tegra30) and Toradex Colibri T20 and Iris carrier boards. * Enablement of the HDMI connector on most boards. * Enablement of the keyboard controller on a few boards. * Addition of the AC'97 controller to Tegra20. * Addition of a GPIO poweroff node for TrimSlice. * Changes to support the new "high speed UART" (DMA-capable) driver for Tegra serial ports, and enablement for Cardhu's UART C. * A few cleanups, such as compatible flag fixes, node renames, node ordering fixes, commonizing properties into SoC .dtsi files, etc.. This pull request is based on (most of) the previous pull request with tag tegra-for-3.9-soc-t114. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRCY++AAoJEMzrak5tbycx6BMQALRuxbStMPDVBmOp65kF8B/s u8wynnbL1qs6dJ81LW9IcVCEqzsR/7tfda9h4p+SPnihF4OxLMYyG95qzK0rR+ZR pA+yIhRQjEq4q4+TgvHNblpSGN1wguLVC/FmN7kpJlSI6IMQsK3iQmPEsUE4gSfK aaCwWaFuUUed7B6gpzJY6pX5C7H4EkwJZxOGBmr/houuoaEKz0vjGY8KaSwBd9RZ oACibtHbhvkkYY6LCkBHSWNHAcwpMZRw+b0SDQ5ephShPK4gMGC44lwTz4RFJawS pgZVYOUpb5OFivZFPKqXglCNe3PMwNgb9ntFm7UU//99ibQiGGB49oIkDL2HJx1g KKeyEOZLN+h0CbgxDu5p2ItCcID1Z5CzD/ryqE7ofFx1iQrUc7b0RsIlM9chUjei xumU5rQJRxwNIvyvYu+zvuV3J7luSe9W+2teXkvKccAwmr1YIbwQeFPGYgkchFOz efKhESGVaoUMKdVyg09nPkDRpM/NwHkxcPCga7ypOJl9oKU3B6t5mmMxI9+sUxet iYL50iDBoulHtBDlCFjYfjnq1Go9sCE+fXxGaWJ5Yec3qsB9zhHDE72hZ3NF1tWj 3YWq5dhyAYz90N6RUhXBHfWvZ4a188Z3tPAUt3C/TUQ9dttzZqkRsCnu7A5nAKyN f9Ul9sK48KSub5+Zb7+7 =UMMs -----END PGP SIGNATURE----- Merge tag 'tegra-for-3.9-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt From Stephen Warren: ARM: tegra: device tree updates Numerous updates to the various Tegra device trees are made: * Addition of NVIDIA Beaver (Tegra30) and Toradex Colibri T20 and Iris carrier boards. * Enablement of the HDMI connector on most boards. * Enablement of the keyboard controller on a few boards. * Addition of the AC'97 controller to Tegra20. * Addition of a GPIO poweroff node for TrimSlice. * Changes to support the new "high speed UART" (DMA-capable) driver for Tegra serial ports, and enablement for Cardhu's UART C. * A few cleanups, such as compatible flag fixes, node renames, node ordering fixes, commonizing properties into SoC .dtsi files, etc.. This pull request is based on (most of) the previous pull request with tag tegra-for-3.9-soc-t114. * tag 'tegra-for-3.9-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (22 commits) ARM: dt: tegra30: Rename "smmu" to "iommu" ARM: dt: tegra20: Rename "gart" to "iommu" ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi ARM: tegra: Add Toradex Iris carrier board DT with T20 512MB COM ARM: tegra: Add Colibri T20 512MB COM device tree ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsi ARM: tegra: harmony: enable keyboard in DT ARM: tegra: whistler: enable keyboard in DT ARM: tegra: cardhu: register UARTC ARM: tegra: seaboard: enable keyboard in DT ARM: tegra: add DT entry for KBC controller ARM: tegra: swap cache-/interrupt-ctrlr nodes in DT ASoC: tegra: add ac97 host controller to device tree ARM: DT: tegra: Add Tegra30 Beaver board support ARM: DT: tegra: Add board level compatible properties ARM: tegra: paz00: enable HDMI port ARM: tegra: ventana: enable HDMI port ARM: tegra: seaboard: enable HDMI port ARM: tegra: trimslice: add gpio-poweroff node to DT ARM: DT: tegra: Unify the description of Tegra20 boards ...
This commit is contained in:
Olof Johansson
commit
5b22c33e8e
@ -1,14 +1,34 @@
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NVIDIA Tegra device tree bindings
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-------------------------------------------
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Boards with the tegra20 SoC shall have the following properties:
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SoCs
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-------------------------------------------
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Required root node property:
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Each device tree must specify which Tegra SoC it uses, using one of the
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following compatible values:
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compatible = "nvidia,tegra20";
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nvidia,tegra20
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nvidia,tegra30
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Boards with the tegra30 SoC shall have the following properties:
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Boards
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-------------------------------------------
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Required root node property:
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Each device tree must specify which one or more of the following
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board-specific compatible values:
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compatible = "nvidia,tegra30";
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ad,medcom-wide
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ad,plutux
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ad,tamonten
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ad,tec
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compal,paz00
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compulab,trimslice
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nvidia,beaver
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nvidia,cardhu
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nvidia,cardhu-a02
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nvidia,cardhu-a04
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nvidia,harmony
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nvidia,seaboard
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nvidia,ventana
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nvidia,whistler
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toradex,colibri_t20-512
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toradex,iris
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@ -136,6 +136,7 @@ dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \
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sun5i-a13-olinuxino.dtb
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dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
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tegra20-iris-512.dtb \
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tegra20-medcom-wide.dtb \
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tegra20-paz00.dtb \
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tegra20-plutux.dtb \
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@ -144,6 +145,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
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tegra20-trimslice.dtb \
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tegra20-ventana.dtb \
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tegra20-whistler.dtb \
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tegra30-beaver.dtb \
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tegra30-cardhu-a02.dtb \
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tegra30-cardhu-a04.dtb \
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tegra114-dalmore.dtb \
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491
arch/arm/boot/dts/tegra20-colibri-512.dtsi
Normal file
491
arch/arm/boot/dts/tegra20-colibri-512.dtsi
Normal file
@ -0,0 +1,491 @@
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/include/ "tegra20.dtsi"
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/ {
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model = "Toradex Colibri T20 512MB";
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compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
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memory {
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reg = <0x00000000 0x20000000>;
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};
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host1x {
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hdmi {
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vdd-supply = <&hdmi_vdd_reg>;
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pll-supply = <&hdmi_pll_reg>;
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nvidia,ddc-i2c-bus = <&i2c_ddc>;
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nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
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};
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};
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pinmux {
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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audio_refclk {
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nvidia,pins = "cdev1";
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nvidia,function = "plla_out";
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nvidia,pull = <0>;
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nvidia,tristate = <0>;
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};
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crt {
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nvidia,pins = "crtp";
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nvidia,function = "crt";
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nvidia,pull = <0>;
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nvidia,tristate = <1>;
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};
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dap3 {
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nvidia,pins = "dap3";
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nvidia,function = "dap3";
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nvidia,pull = <0>;
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nvidia,tristate = <0>;
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};
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displaya {
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nvidia,pins = "ld0", "ld1", "ld2", "ld3",
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"ld4", "ld5", "ld6", "ld7", "ld8",
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"ld9", "ld10", "ld11", "ld12", "ld13",
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"ld14", "ld15", "ld16", "ld17",
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"lhs", "lpw0", "lpw2", "lsc0",
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"lsc1", "lsck", "lsda", "lspi", "lvs";
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nvidia,function = "displaya";
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nvidia,tristate = <1>;
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};
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gpio_dte {
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nvidia,pins = "dte";
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nvidia,function = "rsvd1";
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nvidia,pull = <0>;
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nvidia,tristate = <0>;
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};
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gpio_gmi {
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nvidia,pins = "ata", "atc", "atd", "ate",
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"dap1", "dap2", "dap4", "gpu", "irrx",
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"irtx", "spia", "spib", "spic";
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nvidia,function = "gmi";
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nvidia,pull = <0>;
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nvidia,tristate = <0>;
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};
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gpio_pta {
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nvidia,pins = "pta";
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nvidia,function = "rsvd4";
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nvidia,pull = <0>;
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nvidia,tristate = <0>;
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};
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gpio_uac {
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nvidia,pins = "uac";
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nvidia,function = "rsvd2";
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nvidia,pull = <0>;
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nvidia,tristate = <0>;
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};
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hdint {
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nvidia,pins = "hdint";
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nvidia,function = "hdmi";
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nvidia,tristate = <1>;
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};
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i2c1 {
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nvidia,pins = "rm";
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nvidia,function = "i2c1";
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nvidia,pull = <0>;
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nvidia,tristate = <1>;
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};
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i2c3 {
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nvidia,pins = "dtf";
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nvidia,function = "i2c3";
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nvidia,pull = <0>;
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nvidia,tristate = <1>;
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};
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i2cddc {
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nvidia,pins = "ddc";
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nvidia,function = "i2c2";
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nvidia,pull = <2>;
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nvidia,tristate = <1>;
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};
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i2cp {
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nvidia,pins = "i2cp";
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nvidia,function = "i2cp";
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nvidia,pull = <0>;
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nvidia,tristate = <0>;
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};
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irda {
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nvidia,pins = "uad";
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nvidia,function = "irda";
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nvidia,pull = <0>;
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nvidia,tristate = <1>;
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};
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nand {
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nvidia,pins = "kbca", "kbcc", "kbcd",
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"kbce", "kbcf";
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nvidia,function = "nand";
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nvidia,pull = <0>;
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nvidia,tristate = <0>;
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};
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owc {
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nvidia,pins = "owc";
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nvidia,function = "owr";
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nvidia,pull = <0>;
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nvidia,tristate = <1>;
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};
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pmc {
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nvidia,pins = "pmc";
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nvidia,function = "pwr_on";
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nvidia,tristate = <0>;
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};
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pwm {
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nvidia,pins = "sdb", "sdc", "sdd";
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nvidia,function = "pwm";
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nvidia,tristate = <1>;
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};
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sdio4 {
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nvidia,pins = "atb", "gma", "gme";
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nvidia,function = "sdio4";
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nvidia,pull = <0>;
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nvidia,tristate = <1>;
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};
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spi1 {
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nvidia,pins = "spid", "spie", "spif";
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nvidia,function = "spi1";
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nvidia,pull = <0>;
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nvidia,tristate = <1>;
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};
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spi4 {
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nvidia,pins = "slxa", "slxc", "slxd", "slxk";
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nvidia,function = "spi4";
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nvidia,pull = <0>;
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nvidia,tristate = <1>;
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};
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uarta {
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nvidia,pins = "sdio1";
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nvidia,function = "uarta";
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nvidia,pull = <0>;
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nvidia,tristate = <1>;
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};
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uartd {
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nvidia,pins = "gmc";
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nvidia,function = "uartd";
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nvidia,pull = <0>;
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nvidia,tristate = <1>;
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};
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ulpi {
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nvidia,pins = "uaa", "uab", "uda";
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nvidia,function = "ulpi";
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nvidia,pull = <0>;
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nvidia,tristate = <0>;
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};
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ulpi_refclk {
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nvidia,pins = "cdev2";
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nvidia,function = "pllp_out4";
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nvidia,pull = <0>;
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nvidia,tristate = <0>;
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};
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usb_gpio {
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nvidia,pins = "spig", "spih";
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nvidia,function = "spi2_alt";
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nvidia,pull = <0>;
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nvidia,tristate = <0>;
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};
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vi {
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nvidia,pins = "dta", "dtb", "dtc", "dtd";
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nvidia,function = "vi";
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nvidia,pull = <0>;
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nvidia,tristate = <1>;
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};
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vi_sc {
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nvidia,pins = "csus";
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nvidia,function = "vi_sensor_clk";
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nvidia,pull = <0>;
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nvidia,tristate = <1>;
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};
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};
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};
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i2c@7000c000 {
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clock-frequency = <400000>;
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};
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i2c_ddc: i2c@7000c400 {
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clock-frequency = <100000>;
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};
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i2c@7000c500 {
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clock-frequency = <400000>;
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};
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i2c@7000d000 {
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status = "okay";
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clock-frequency = <400000>;
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pmic: tps6586x@34 {
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compatible = "ti,tps6586x";
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reg = <0x34>;
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interrupts = <0 86 0x4>;
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ti,system-power-controller;
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#gpio-cells = <2>;
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gpio-controller;
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sys-supply = <&vdd_5v0_reg>;
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vin-sm0-supply = <&sys_reg>;
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vin-sm1-supply = <&sys_reg>;
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vin-sm2-supply = <&sys_reg>;
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vinldo01-supply = <&sm2_reg>;
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vinldo23-supply = <&sm2_reg>;
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vinldo4-supply = <&sm2_reg>;
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vinldo678-supply = <&sm2_reg>;
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vinldo9-supply = <&sm2_reg>;
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regulators {
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#address-cells = <1>;
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#size-cells = <0>;
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sys_reg: regulator@0 {
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reg = <0>;
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regulator-compatible = "sys";
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regulator-name = "vdd_sys";
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regulator-always-on;
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||||
};
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||||
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||||
regulator@1 {
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||||
reg = <1>;
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||||
regulator-compatible = "sm0";
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regulator-name = "vdd_sm0,vdd_core";
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||||
regulator-min-microvolt = <1275000>;
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||||
regulator-max-microvolt = <1275000>;
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||||
regulator-always-on;
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||||
};
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||||
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||||
regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "sm1";
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||||
regulator-name = "vdd_sm1,vdd_cpu";
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||||
regulator-min-microvolt = <1100000>;
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||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
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||||
};
|
||||
|
||||
sm2_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "sm2";
|
||||
regulator-name = "vdd_sm2,vin_ldo*";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* LDO0 is not connected to anything */
|
||||
|
||||
regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "ldo1";
|
||||
regulator-name = "vdd_ldo1,avdd_pll*";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-compatible = "ldo2";
|
||||
regulator-name = "vdd_ldo2,vdd_rtc";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
/* LDO3 is not connected to anything */
|
||||
|
||||
regulator@8 {
|
||||
reg = <8>;
|
||||
regulator-compatible = "ldo4";
|
||||
regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5_reg: regulator@9 {
|
||||
reg = <9>;
|
||||
regulator-compatible = "ldo5";
|
||||
regulator-name = "vdd_ldo5,vdd_fuse";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@10 {
|
||||
reg = <10>;
|
||||
regulator-compatible = "ldo6";
|
||||
regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
hdmi_vdd_reg: regulator@11 {
|
||||
reg = <11>;
|
||||
regulator-compatible = "ldo7";
|
||||
regulator-name = "vdd_ldo7,avdd_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
hdmi_pll_reg: regulator@12 {
|
||||
reg = <12>;
|
||||
regulator-compatible = "ldo8";
|
||||
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@13 {
|
||||
reg = <13>;
|
||||
regulator-compatible = "ldo9";
|
||||
regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@14 {
|
||||
reg = <14>;
|
||||
regulator-compatible = "ldo_rtc";
|
||||
regulator-name = "vdd_rtc_out,vdd_cell";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
temperature-sensor@4c {
|
||||
compatible = "national,lm95245";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
|
||||
memory-controller@7000f400 {
|
||||
emc-table@83250 {
|
||||
reg = <83250>;
|
||||
compatible = "nvidia,tegra20-emc-table";
|
||||
clock-frequency = <83250>;
|
||||
nvidia,emc-registers = <0x00000005 0x00000011
|
||||
0x00000004 0x00000002 0x00000004 0x00000004
|
||||
0x00000001 0x0000000a 0x00000002 0x00000002
|
||||
0x00000001 0x00000001 0x00000003 0x00000004
|
||||
0x00000003 0x00000009 0x0000000c 0x0000025f
|
||||
0x00000000 0x00000003 0x00000003 0x00000002
|
||||
0x00000002 0x00000001 0x00000008 0x000000c8
|
||||
0x00000003 0x00000005 0x00000003 0x0000000c
|
||||
0x00000002 0x00000000 0x00000000 0x00000002
|
||||
0x00000000 0x00000000 0x00000083 0x00520006
|
||||
0x00000010 0x00000008 0x00000000 0x00000000
|
||||
0x00000000 0x00000000 0x00000000 0x00000000>;
|
||||
};
|
||||
emc-table@133200 {
|
||||
reg = <133200>;
|
||||
compatible = "nvidia,tegra20-emc-table";
|
||||
clock-frequency = <133200>;
|
||||
nvidia,emc-registers = <0x00000008 0x00000019
|
||||
0x00000006 0x00000002 0x00000004 0x00000004
|
||||
0x00000001 0x0000000a 0x00000002 0x00000002
|
||||
0x00000002 0x00000001 0x00000003 0x00000004
|
||||
0x00000003 0x00000009 0x0000000c 0x0000039f
|
||||
0x00000000 0x00000003 0x00000003 0x00000002
|
||||
0x00000002 0x00000001 0x00000008 0x000000c8
|
||||
0x00000003 0x00000007 0x00000003 0x0000000c
|
||||
0x00000002 0x00000000 0x00000000 0x00000002
|
||||
0x00000000 0x00000000 0x00000083 0x00510006
|
||||
0x00000010 0x00000008 0x00000000 0x00000000
|
||||
0x00000000 0x00000000 0x00000000 0x00000000>;
|
||||
};
|
||||
emc-table@166500 {
|
||||
reg = <166500>;
|
||||
compatible = "nvidia,tegra20-emc-table";
|
||||
clock-frequency = <166500>;
|
||||
nvidia,emc-registers = <0x0000000a 0x00000021
|
||||
0x00000008 0x00000003 0x00000004 0x00000004
|
||||
0x00000002 0x0000000a 0x00000003 0x00000003
|
||||
0x00000002 0x00000001 0x00000003 0x00000004
|
||||
0x00000003 0x00000009 0x0000000c 0x000004df
|
||||
0x00000000 0x00000003 0x00000003 0x00000003
|
||||
0x00000003 0x00000001 0x00000009 0x000000c8
|
||||
0x00000003 0x00000009 0x00000004 0x0000000c
|
||||
0x00000002 0x00000000 0x00000000 0x00000002
|
||||
0x00000000 0x00000000 0x00000083 0x004f0006
|
||||
0x00000010 0x00000008 0x00000000 0x00000000
|
||||
0x00000000 0x00000000 0x00000000 0x00000000>;
|
||||
};
|
||||
emc-table@333000 {
|
||||
reg = <333000>;
|
||||
compatible = "nvidia,tegra20-emc-table";
|
||||
clock-frequency = <333000>;
|
||||
nvidia,emc-registers = <0x00000014 0x00000041
|
||||
0x0000000f 0x00000005 0x00000004 0x00000005
|
||||
0x00000003 0x0000000a 0x00000005 0x00000005
|
||||
0x00000004 0x00000001 0x00000003 0x00000004
|
||||
0x00000003 0x00000009 0x0000000c 0x000009ff
|
||||
0x00000000 0x00000003 0x00000003 0x00000005
|
||||
0x00000005 0x00000001 0x0000000e 0x000000c8
|
||||
0x00000003 0x00000011 0x00000006 0x0000000c
|
||||
0x00000002 0x00000000 0x00000000 0x00000002
|
||||
0x00000000 0x00000000 0x00000083 0x00380006
|
||||
0x00000010 0x00000008 0x00000000 0x00000000
|
||||
0x00000000 0x00000000 0x00000000 0x00000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ac97: ac97 {
|
||||
status = "okay";
|
||||
nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
|
||||
nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
|
||||
};
|
||||
|
||||
usb@c5004000 {
|
||||
status = "okay";
|
||||
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
|
||||
};
|
||||
|
||||
sdhci@c8000600 {
|
||||
cd-gpios = <&gpio 23 0>; /* gpio PC7 */
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
|
||||
"nvidia,tegra-audio-wm9712";
|
||||
nvidia,model = "Colibri T20 AC97 Audio";
|
||||
|
||||
nvidia,audio-routing =
|
||||
"Headphone", "HPOUTL",
|
||||
"Headphone", "HPOUTR",
|
||||
"LineIn", "LINEINL",
|
||||
"LineIn", "LINEINR",
|
||||
"Mic", "MIC1";
|
||||
|
||||
nvidia,ac97-controller = <&ac97>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vdd_5v0_reg: regulator@100 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <100>;
|
||||
regulator-name = "vdd_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@101 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <101>;
|
||||
regulator-name = "internal_usb";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
gpio = <&gpio 217 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -3,7 +3,7 @@
|
||||
/include/ "tegra20.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NVIDIA Tegra2 Harmony evaluation board";
|
||||
model = "NVIDIA Tegra20 Harmony evaluation board";
|
||||
compatible = "nvidia,harmony", "nvidia,tegra20";
|
||||
|
||||
memory {
|
||||
@ -252,7 +252,6 @@
|
||||
|
||||
serial@70006300 {
|
||||
status = "okay";
|
||||
clock-frequency = <216000000>;
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
@ -452,6 +451,123 @@
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
kbc {
|
||||
status = "okay";
|
||||
nvidia,debounce-delay-ms = <2>;
|
||||
nvidia,repeat-delay-ms = <160>;
|
||||
nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
|
||||
nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
|
||||
linux,keymap = <0x00020011 /* KEY_W */
|
||||
0x0003001F /* KEY_S */
|
||||
0x0004001E /* KEY_A */
|
||||
0x0005002C /* KEY_Z */
|
||||
0x000701D0 /* KEY_FN */
|
||||
0x0107008B /* KEY_MENU */
|
||||
0x02060038 /* KEY_LEFTALT */
|
||||
0x02070064 /* KEY_RIGHTALT */
|
||||
0x03000006 /* KEY_5 */
|
||||
0x03010005 /* KEY_4 */
|
||||
0x03020013 /* KEY_R */
|
||||
0x03030012 /* KEY_E */
|
||||
0x03040021 /* KEY_F */
|
||||
0x03050020 /* KEY_D */
|
||||
0x0306002D /* KEY_X */
|
||||
0x04000008 /* KEY_7 */
|
||||
0x04010007 /* KEY_6 */
|
||||
0x04020014 /* KEY_T */
|
||||
0x04030023 /* KEY_H */
|
||||
0x04040022 /* KEY_G */
|
||||
0x0405002F /* KEY_V */
|
||||
0x0406002E /* KEY_C */
|
||||
0x04070039 /* KEY_SPACE */
|
||||
0x0500000A /* KEY_9 */
|
||||
0x05010009 /* KEY_8 */
|
||||
0x05020016 /* KEY_U */
|
||||
0x05030015 /* KEY_Y */
|
||||
0x05040024 /* KEY_J */
|
||||
0x05050031 /* KEY_N */
|
||||
0x05060030 /* KEY_B */
|
||||
0x0507002B /* KEY_BACKSLASH */
|
||||
0x0600000C /* KEY_MINUS */
|
||||
0x0601000B /* KEY_0 */
|
||||
0x06020018 /* KEY_O */
|
||||
0x06030017 /* KEY_I */
|
||||
0x06040026 /* KEY_L */
|
||||
0x06050025 /* KEY_K */
|
||||
0x06060033 /* KEY_COMMA */
|
||||
0x06070032 /* KEY_M */
|
||||
0x0701000D /* KEY_EQUAL */
|
||||
0x0702001B /* KEY_RIGHTBRACE */
|
||||
0x0703001C /* KEY_ENTER */
|
||||
0x0707008B /* KEY_MENU */
|
||||
0x0804002A /* KEY_LEFTSHIFT */
|
||||
0x08050036 /* KEY_RIGHTSHIFT */
|
||||
0x0905001D /* KEY_LEFTCTRL */
|
||||
0x09070061 /* KEY_RIGHTCTRL */
|
||||
0x0B00001A /* KEY_LEFTBRACE */
|
||||
0x0B010019 /* KEY_P */
|
||||
0x0B020028 /* KEY_APOSTROPHE */
|
||||
0x0B030027 /* KEY_SEMICOLON */
|
||||
0x0B040035 /* KEY_SLASH */
|
||||
0x0B050034 /* KEY_DOT */
|
||||
0x0C000044 /* KEY_F10 */
|
||||
0x0C010043 /* KEY_F9 */
|
||||
0x0C02000E /* KEY_BACKSPACE */
|
||||
0x0C030004 /* KEY_3 */
|
||||
0x0C040003 /* KEY_2 */
|
||||
0x0C050067 /* KEY_UP */
|
||||
0x0C0600D2 /* KEY_PRINT */
|
||||
0x0C070077 /* KEY_PAUSE */
|
||||
0x0D00006E /* KEY_INSERT */
|
||||
0x0D01006F /* KEY_DELETE */
|
||||
0x0D030068 /* KEY_PAGEUP */
|
||||
0x0D04006D /* KEY_PAGEDOWN */
|
||||
0x0D05006A /* KEY_RIGHT */
|
||||
0x0D06006C /* KEY_DOWN */
|
||||
0x0D070069 /* KEY_LEFT */
|
||||
0x0E000057 /* KEY_F11 */
|
||||
0x0E010058 /* KEY_F12 */
|
||||
0x0E020042 /* KEY_F8 */
|
||||
0x0E030010 /* KEY_Q */
|
||||
0x0E04003E /* KEY_F4 */
|
||||
0x0E05003D /* KEY_F3 */
|
||||
0x0E060002 /* KEY_1 */
|
||||
0x0E070041 /* KEY_F7 */
|
||||
0x0F000001 /* KEY_ESC */
|
||||
0x0F010029 /* KEY_GRAVE */
|
||||
0x0F02003F /* KEY_F5 */
|
||||
0x0F03000F /* KEY_TAB */
|
||||
0x0F04003B /* KEY_F1 */
|
||||
0x0F05003C /* KEY_F2 */
|
||||
0x0F06003A /* KEY_CAPSLOCK */
|
||||
0x0F070040 /* KEY_F6 */
|
||||
0x14000047 /* KEY_KP7 */
|
||||
0x15000049 /* KEY_KP9 */
|
||||
0x15010048 /* KEY_KP8 */
|
||||
0x1502004B /* KEY_KP4 */
|
||||
0x1504004F /* KEY_KP1 */
|
||||
0x1601004E /* KEY_KPSLASH */
|
||||
0x1602004D /* KEY_KP6 */
|
||||
0x1603004C /* KEY_KP5 */
|
||||
0x16040051 /* KEY_KP3 */
|
||||
0x16050050 /* KEY_KP2 */
|
||||
0x16070052 /* KEY_KP0 */
|
||||
0x1B010037 /* KEY_KPASTERISK */
|
||||
0x1B03004A /* KEY_KPMINUS */
|
||||
0x1B04004E /* KEY_KPPLUS */
|
||||
0x1B050053 /* KEY_KPDOT */
|
||||
0x1C050073 /* KEY_VOLUMEUP */
|
||||
0x1D030066 /* KEY_HOME */
|
||||
0x1D04006B /* KEY_END */
|
||||
0x1D0500E1 /* KEY_BRIGHTNESSUP */
|
||||
0x1D060072 /* KEY_VOLUMEDOWN */
|
||||
0x1D0700E0 /* KEY_BRIGHTNESSDOWN */
|
||||
0x1E000045 /* KEY_NUMLOCK */
|
||||
0x1E010046 /* KEY_SCROLLLOCK */
|
||||
0x1E020071 /* KEY_MUTE */
|
||||
0x1F0400D6>; /* KEY_QUESTION */
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
||||
89
arch/arm/boot/dts/tegra20-iris-512.dts
Normal file
89
arch/arm/boot/dts/tegra20-iris-512.dts
Normal file
@ -0,0 +1,89 @@
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "tegra20-colibri-512.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri T20 512MB on Iris";
|
||||
compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
state_default: pinmux {
|
||||
hdint {
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
|
||||
i2cddc {
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
|
||||
sdio4 {
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
|
||||
uarta {
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
|
||||
uartd {
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb@c5000000 {
|
||||
status = "okay";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
|
||||
usb@c5008000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@70006000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@70006300 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c_ddc: i2c@7000c400 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdhci@c8000600 {
|
||||
status = "okay";
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&vcc_sd_reg>;
|
||||
vqmmc-supply = <&vcc_sd_reg>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "usb_host_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
gpio = <&gpio 178 0>;
|
||||
};
|
||||
|
||||
vcc_sd_reg: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -10,6 +10,18 @@
|
||||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&hdmi_vdd_reg>;
|
||||
pll-supply = <&hdmi_pll_reg>;
|
||||
|
||||
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
|
||||
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
|
||||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
@ -232,12 +244,10 @@
|
||||
|
||||
serial@70006000 {
|
||||
status = "okay";
|
||||
clock-frequency = <216000000>;
|
||||
};
|
||||
|
||||
serial@70006200 {
|
||||
status = "okay";
|
||||
clock-frequency = <216000000>;
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
@ -252,9 +262,9 @@
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c400 {
|
||||
hdmi_ddc: i2c@7000c400 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
nvec {
|
||||
@ -369,13 +379,13 @@
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ldo7 {
|
||||
hdmi_vdd_reg: ldo7 {
|
||||
regulator-name = "+3.3vs_ldo7,avdd_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
ldo8 {
|
||||
hdmi_pll_reg: ldo8 {
|
||||
regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
@ -10,6 +10,18 @@
|
||||
reg = <0x00000000 0x40000000>;
|
||||
};
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&hdmi_vdd_reg>;
|
||||
pll-supply = <&hdmi_pll_reg>;
|
||||
|
||||
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
|
||||
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
|
||||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
@ -291,7 +303,6 @@
|
||||
|
||||
serial@70006300 {
|
||||
status = "okay";
|
||||
clock-frequency = <216000000>;
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
@ -345,7 +356,7 @@
|
||||
pinctrl-1 = <&state_i2cmux_pta>;
|
||||
pinctrl-2 = <&state_i2cmux_idle>;
|
||||
|
||||
i2c@0 {
|
||||
hdmi_ddc: i2c@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -463,13 +474,13 @@
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ldo7 {
|
||||
hdmi_vdd_reg: ldo7 {
|
||||
regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
ldo8 {
|
||||
hdmi_pll_reg: ldo8 {
|
||||
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
@ -604,6 +615,145 @@
|
||||
};
|
||||
};
|
||||
|
||||
kbc {
|
||||
status = "okay";
|
||||
nvidia,debounce-delay-ms = <32>;
|
||||
nvidia,repeat-delay-ms = <160>;
|
||||
nvidia,ghost-filter;
|
||||
nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
|
||||
nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
|
||||
linux,keymap = <0x00020011 /* KEY_W */
|
||||
0x0003001F /* KEY_S */
|
||||
0x0004001E /* KEY_A */
|
||||
0x0005002C /* KEY_Z */
|
||||
0x000701d0 /* KEY_FN */
|
||||
|
||||
0x0107007D /* KEY_LEFTMETA */
|
||||
0x02060064 /* KEY_RIGHTALT */
|
||||
0x02070038 /* KEY_LEFTALT */
|
||||
|
||||
0x03000006 /* KEY_5 */
|
||||
0x03010005 /* KEY_4 */
|
||||
0x03020013 /* KEY_R */
|
||||
0x03030012 /* KEY_E */
|
||||
0x03040021 /* KEY_F */
|
||||
0x03050020 /* KEY_D */
|
||||
0x0306002D /* KEY_X */
|
||||
|
||||
0x04000008 /* KEY_7 */
|
||||
0x04010007 /* KEY_6 */
|
||||
0x04020014 /* KEY_T */
|
||||
0x04030023 /* KEY_H */
|
||||
0x04040022 /* KEY_G */
|
||||
0x0405002F /* KEY_V */
|
||||
0x0406002E /* KEY_C */
|
||||
0x04070039 /* KEY_SPACE */
|
||||
|
||||
0x0500000A /* KEY_9 */
|
||||
0x05010009 /* KEY_8 */
|
||||
0x05020016 /* KEY_U */
|
||||
0x05030015 /* KEY_Y */
|
||||
0x05040024 /* KEY_J */
|
||||
0x05050031 /* KEY_N */
|
||||
0x05060030 /* KEY_B */
|
||||
0x0507002B /* KEY_BACKSLASH */
|
||||
|
||||
0x0600000C /* KEY_MINUS */
|
||||
0x0601000B /* KEY_0 */
|
||||
0x06020018 /* KEY_O */
|
||||
0x06030017 /* KEY_I */
|
||||
0x06040026 /* KEY_L */
|
||||
0x06050025 /* KEY_K */
|
||||
0x06060033 /* KEY_COMMA */
|
||||
0x06070032 /* KEY_M */
|
||||
|
||||
0x0701000D /* KEY_EQUAL */
|
||||
0x0702001B /* KEY_RIGHTBRACE */
|
||||
0x0703001C /* KEY_ENTER */
|
||||
0x0707008B /* KEY_MENU */
|
||||
|
||||
0x08040036 /* KEY_RIGHTSHIFT */
|
||||
0x0805002A /* KEY_LEFTSHIFT */
|
||||
|
||||
0x09050061 /* KEY_RIGHTCTRL */
|
||||
0x0907001D /* KEY_LEFTCTRL */
|
||||
|
||||
0x0B00001A /* KEY_LEFTBRACE */
|
||||
0x0B010019 /* KEY_P */
|
||||
0x0B020028 /* KEY_APOSTROPHE */
|
||||
0x0B030027 /* KEY_SEMICOLON */
|
||||
0x0B040035 /* KEY_SLASH */
|
||||
0x0B050034 /* KEY_DOT */
|
||||
|
||||
0x0C000044 /* KEY_F10 */
|
||||
0x0C010043 /* KEY_F9 */
|
||||
0x0C02000E /* KEY_BACKSPACE */
|
||||
0x0C030004 /* KEY_3 */
|
||||
0x0C040003 /* KEY_2 */
|
||||
0x0C050067 /* KEY_UP */
|
||||
0x0C0600D2 /* KEY_PRINT */
|
||||
0x0C070077 /* KEY_PAUSE */
|
||||
|
||||
0x0D00006E /* KEY_INSERT */
|
||||
0x0D01006F /* KEY_DELETE */
|
||||
0x0D030068 /* KEY_PAGEUP */
|
||||
0x0D04006D /* KEY_PAGEDOWN */
|
||||
0x0D05006A /* KEY_RIGHT */
|
||||
0x0D06006C /* KEY_DOWN */
|
||||
0x0D070069 /* KEY_LEFT */
|
||||
|
||||
0x0E000057 /* KEY_F11 */
|
||||
0x0E010058 /* KEY_F12 */
|
||||
0x0E020042 /* KEY_F8 */
|
||||
0x0E030010 /* KEY_Q */
|
||||
0x0E04003E /* KEY_F4 */
|
||||
0x0E05003D /* KEY_F3 */
|
||||
0x0E060002 /* KEY_1 */
|
||||
0x0E070041 /* KEY_F7 */
|
||||
|
||||
0x0F000001 /* KEY_ESC */
|
||||
0x0F010029 /* KEY_GRAVE */
|
||||
0x0F02003F /* KEY_F5 */
|
||||
0x0F03000F /* KEY_TAB */
|
||||
0x0F04003B /* KEY_F1 */
|
||||
0x0F05003C /* KEY_F2 */
|
||||
0x0F06003A /* KEY_CAPSLOCK */
|
||||
0x0F070040 /* KEY_F6 */
|
||||
|
||||
/* Software Handled Function Keys */
|
||||
0x14000047 /* KEY_KP7 */
|
||||
|
||||
0x15000049 /* KEY_KP9 */
|
||||
0x15010048 /* KEY_KP8 */
|
||||
0x1502004B /* KEY_KP4 */
|
||||
0x1504004F /* KEY_KP1 */
|
||||
|
||||
0x1601004E /* KEY_KPSLASH */
|
||||
0x1602004D /* KEY_KP6 */
|
||||
0x1603004C /* KEY_KP5 */
|
||||
0x16040051 /* KEY_KP3 */
|
||||
0x16050050 /* KEY_KP2 */
|
||||
0x16070052 /* KEY_KP0 */
|
||||
|
||||
0x1B010037 /* KEY_KPASTERISK */
|
||||
0x1B03004A /* KEY_KPMINUS */
|
||||
0x1B04004E /* KEY_KPPLUS */
|
||||
0x1B050053 /* KEY_KPDOT */
|
||||
|
||||
0x1C050073 /* KEY_VOLUMEUP */
|
||||
|
||||
0x1D030066 /* KEY_HOME */
|
||||
0x1D04006B /* KEY_END */
|
||||
0x1D0500E0 /* KEY_BRIGHTNESSDOWN */
|
||||
0x1D060072 /* KEY_VOLUMEDOWN */
|
||||
0x1D0700E1 /* KEY_BRIGHTNESSUP */
|
||||
|
||||
0x1E000045 /* KEY_NUMLOCK */
|
||||
0x1E010046 /* KEY_SCROLLLOCK */
|
||||
0x1E020071 /* KEY_MUTE */
|
||||
|
||||
0x1F04008A>; /* KEY_HELP */
|
||||
};
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
||||
@ -276,7 +276,6 @@
|
||||
};
|
||||
|
||||
serial@70006300 {
|
||||
clock-frequency = <216000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@ -249,6 +249,11 @@
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
};
|
||||
conf_spif {
|
||||
nvidia,pins = "spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -258,7 +263,6 @@
|
||||
|
||||
serial@70006000 {
|
||||
status = "okay";
|
||||
clock-frequency = <216000000>;
|
||||
};
|
||||
|
||||
dvi_ddc: i2c@7000c000 {
|
||||
@ -326,6 +330,11 @@
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
poweroff {
|
||||
compatible = "gpio-poweroff";
|
||||
gpios = <&gpio 191 1>; /* gpio PX7, active low */
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
||||
@ -3,13 +3,25 @@
|
||||
/include/ "tegra20.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NVIDIA Tegra2 Ventana evaluation board";
|
||||
model = "NVIDIA Tegra20 Ventana evaluation board";
|
||||
compatible = "nvidia,ventana", "nvidia,tegra20";
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x40000000>;
|
||||
};
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&hdmi_vdd_reg>;
|
||||
pll-supply = <&hdmi_pll_reg>;
|
||||
|
||||
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
|
||||
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
|
||||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
@ -288,7 +300,6 @@
|
||||
|
||||
serial@70006300 {
|
||||
status = "okay";
|
||||
clock-frequency = <216000000>;
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
@ -320,7 +331,7 @@
|
||||
|
||||
i2c@7000c400 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2cmux {
|
||||
@ -335,7 +346,7 @@
|
||||
pinctrl-1 = <&state_i2cmux_pta>;
|
||||
pinctrl-2 = <&state_i2cmux_idle>;
|
||||
|
||||
i2c@0 {
|
||||
hdmi_ddc: i2c@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -446,13 +457,13 @@
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ldo7 {
|
||||
hdmi_vdd_reg: ldo7 {
|
||||
regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
ldo8 {
|
||||
hdmi_pll_reg: ldo8 {
|
||||
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
/include/ "tegra20.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NVIDIA Tegra2 Whistler evaluation board";
|
||||
model = "NVIDIA Tegra20 Whistler evaluation board";
|
||||
compatible = "nvidia,whistler", "nvidia,tegra20";
|
||||
|
||||
memory {
|
||||
@ -255,7 +255,6 @@
|
||||
|
||||
serial@70006000 {
|
||||
status = "okay";
|
||||
clock-frequency = <216000000>;
|
||||
};
|
||||
|
||||
hdmi_ddc: i2c@7000c400 {
|
||||
@ -520,6 +519,18 @@
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
kbc {
|
||||
status = "okay";
|
||||
nvidia,debounce-delay-ms = <20>;
|
||||
nvidia,repeat-delay-ms = <160>;
|
||||
nvidia,kbc-row-pins = <0 1 2>;
|
||||
nvidia,kbc-col-pins = <16 17>;
|
||||
linux,keymap = <0x00000074 /* KEY_POWER */
|
||||
0x01000066 /* KEY_HOME */
|
||||
0x0101009E /* KEY_BACK */
|
||||
0x0201008B>; /* KEY_MENU */
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
||||
@ -4,6 +4,14 @@
|
||||
compatible = "nvidia,tegra20";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartb;
|
||||
serial2 = &uartc;
|
||||
serial3 = &uartd;
|
||||
serial4 = &uarte;
|
||||
};
|
||||
|
||||
host1x {
|
||||
compatible = "nvidia,tegra20-host1x", "simple-bus";
|
||||
reg = <0x50000000 0x00024000>;
|
||||
@ -112,15 +120,6 @@
|
||||
interrupts = <1 13 0x304>;
|
||||
};
|
||||
|
||||
cache-controller@50043000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x50043000 0x1000>;
|
||||
arm,data-latency = <5 5 2>;
|
||||
arm,tag-latency = <4 4 2>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
reg = <0x50041000 0x1000
|
||||
@ -129,6 +128,15 @@
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
|
||||
cache-controller {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x50043000 0x1000>;
|
||||
arm,data-latency = <5 5 2>;
|
||||
arm,tag-latency = <4 4 2>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
timer@60005000 {
|
||||
compatible = "nvidia,tegra20-timer";
|
||||
reg = <0x60005000 0x60>;
|
||||
@ -199,6 +207,15 @@
|
||||
compatible = "nvidia,tegra20-das";
|
||||
reg = <0x70000c00 0x80>;
|
||||
};
|
||||
|
||||
tegra_ac97: ac97 {
|
||||
compatible = "nvidia,tegra20-ac97";
|
||||
reg = <0x70002000 0x200>;
|
||||
interrupts = <0 81 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 12>;
|
||||
clocks = <&tegra_car 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tegra_i2s1: i2s@70002800 {
|
||||
compatible = "nvidia,tegra20-i2s";
|
||||
@ -218,47 +235,64 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@70006000 {
|
||||
/*
|
||||
* There are two serial driver i.e. 8250 based simple serial
|
||||
* driver and APB DMA based serial driver for higher baudrate
|
||||
* and performace. To enable the 8250 based driver, the compatible
|
||||
* is "nvidia,tegra20-uart" and to enable the APB DMA based serial
|
||||
* driver, the comptible is "nvidia,tegra20-hsuart".
|
||||
*/
|
||||
uarta: serial@70006000 {
|
||||
compatible = "nvidia,tegra20-uart";
|
||||
reg = <0x70006000 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <0 36 0x04>;
|
||||
clock-frequency = <216000000>;
|
||||
nvidia,dma-request-selector = <&apbdma 8>;
|
||||
clocks = <&tegra_car 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@70006040 {
|
||||
uartb: serial@70006040 {
|
||||
compatible = "nvidia,tegra20-uart";
|
||||
reg = <0x70006040 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <0 37 0x04>;
|
||||
clock-frequency = <216000000>;
|
||||
nvidia,dma-request-selector = <&apbdma 9>;
|
||||
clocks = <&tegra_car 96>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@70006200 {
|
||||
uartc: serial@70006200 {
|
||||
compatible = "nvidia,tegra20-uart";
|
||||
reg = <0x70006200 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <0 46 0x04>;
|
||||
clock-frequency = <216000000>;
|
||||
nvidia,dma-request-selector = <&apbdma 10>;
|
||||
clocks = <&tegra_car 55>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@70006300 {
|
||||
uartd: serial@70006300 {
|
||||
compatible = "nvidia,tegra20-uart";
|
||||
reg = <0x70006300 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <0 90 0x04>;
|
||||
clock-frequency = <216000000>;
|
||||
nvidia,dma-request-selector = <&apbdma 19>;
|
||||
clocks = <&tegra_car 65>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@70006400 {
|
||||
uarte: serial@70006400 {
|
||||
compatible = "nvidia,tegra20-uart";
|
||||
reg = <0x70006400 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <0 91 0x04>;
|
||||
clock-frequency = <216000000>;
|
||||
nvidia,dma-request-selector = <&apbdma 20>;
|
||||
clocks = <&tegra_car 66>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -375,6 +409,14 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
kbc {
|
||||
compatible = "nvidia,tegra20-kbc";
|
||||
reg = <0x7000e200 0x100>;
|
||||
interrupts = <0 85 0x04>;
|
||||
clocks = <&tegra_car 36>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pmc {
|
||||
compatible = "nvidia,tegra20-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
@ -387,7 +429,7 @@
|
||||
interrupts = <0 77 0x04>;
|
||||
};
|
||||
|
||||
gart {
|
||||
iommu {
|
||||
compatible = "nvidia,tegra20-gart";
|
||||
reg = <0x7000f024 0x00000018 /* controller registers */
|
||||
0x58000000 0x02000000>; /* GART aperture */
|
||||
|
||||
373
arch/arm/boot/dts/tegra30-beaver.dts
Normal file
373
arch/arm/boot/dts/tegra30-beaver.dts
Normal file
@ -0,0 +1,373 @@
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "tegra30.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NVIDIA Tegra30 Beaver evaluation board";
|
||||
compatible = "nvidia,beaver", "nvidia,tegra30";
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x80000000>;
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
sdmmc1_clk_pz0 {
|
||||
nvidia,pins = "sdmmc1_clk_pz0";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc1_cmd_pz1 {
|
||||
nvidia,pins = "sdmmc1_cmd_pz1",
|
||||
"sdmmc1_dat0_py7",
|
||||
"sdmmc1_dat1_py6",
|
||||
"sdmmc1_dat2_py5",
|
||||
"sdmmc1_dat3_py4";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc3_clk_pa6 {
|
||||
nvidia,pins = "sdmmc3_clk_pa6";
|
||||
nvidia,function = "sdmmc3";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc3_cmd_pa7 {
|
||||
nvidia,pins = "sdmmc3_cmd_pa7",
|
||||
"sdmmc3_dat0_pb7",
|
||||
"sdmmc3_dat1_pb6",
|
||||
"sdmmc3_dat2_pb5",
|
||||
"sdmmc3_dat3_pb4";
|
||||
nvidia,function = "sdmmc3";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4",
|
||||
"sdmmc4_rst_n_pcc3";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc4_dat0_paa0 {
|
||||
nvidia,pins = "sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
dap2_fs_pa2 {
|
||||
nvidia,pins = "dap2_fs_pa2",
|
||||
"dap2_sclk_pa3",
|
||||
"dap2_din_pa4",
|
||||
"dap2_dout_pa5";
|
||||
nvidia,function = "i2s1";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdio3 {
|
||||
nvidia,pins = "drive_sdio3";
|
||||
nvidia,high-speed-mode = <0>;
|
||||
nvidia,schmitt = <0>;
|
||||
nvidia,pull-down-strength = <46>;
|
||||
nvidia,pull-up-strength = <42>;
|
||||
nvidia,slew-rate-rising = <1>;
|
||||
nvidia,slew-rate-falling = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial@70006000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@7000c400 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@7000c500 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@7000c700 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@7000d000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
tps62361 {
|
||||
compatible = "ti,tps62361";
|
||||
reg = <0x60>;
|
||||
|
||||
regulator-name = "tps62361-vout";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
ti,vsel0-state-high;
|
||||
ti,vsel1-state-high;
|
||||
};
|
||||
|
||||
pmic: tps65911@2d {
|
||||
compatible = "ti,tps65911";
|
||||
reg = <0x2d>;
|
||||
|
||||
interrupts = <0 86 0x4>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
||||
ti,system-power-controller;
|
||||
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
|
||||
vcc1-supply = <&vdd_5v_in_reg>;
|
||||
vcc2-supply = <&vdd_5v_in_reg>;
|
||||
vcc3-supply = <&vio_reg>;
|
||||
vcc4-supply = <&vdd_5v_in_reg>;
|
||||
vcc5-supply = <&vdd_5v_in_reg>;
|
||||
vcc6-supply = <&vdd2_reg>;
|
||||
vcc7-supply = <&vdd_5v_in_reg>;
|
||||
vccio-supply = <&vdd_5v_in_reg>;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vdd1_reg: vdd1 {
|
||||
regulator-name = "vddio_ddr_1v2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd2_reg: vdd2 {
|
||||
regulator-name = "vdd_1v5_gen";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vddctrl_reg: vddctrl {
|
||||
regulator-name = "vdd_cpu,vdd_sys";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vio_reg: vio {
|
||||
regulator-name = "vdd_1v8_gen";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: ldo1 {
|
||||
regulator-name = "vdd_pexa,vdd_pexb";
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
};
|
||||
|
||||
ldo2_reg: ldo2 {
|
||||
regulator-name = "vdd_sata,avdd_plle";
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
};
|
||||
|
||||
/* LDO3 is not connected to anything */
|
||||
|
||||
ldo4_reg: ldo4 {
|
||||
regulator-name = "vdd_rtc";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5_reg: ldo5 {
|
||||
regulator-name = "vddio_sdmmc,avdd_vdac";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo6_reg: ldo6 {
|
||||
regulator-name = "avdd_dsi_csi,pwrdet_mipi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
ldo7_reg: ldo7 {
|
||||
regulator-name = "vdd_pllm,x,u,a_p_c_s";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo8_reg: ldo8 {
|
||||
regulator-name = "vdd_ddr_hs";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi@7000da00 {
|
||||
status = "okay";
|
||||
spi-max-frequency = <25000000>;
|
||||
spi-flash@1 {
|
||||
compatible = "winbond,w25q32";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahub {
|
||||
i2s@70080400 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
status = "okay";
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
sdhci@78000000 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
power-gpios = <&gpio 31 0>; /* gpio PD7 */
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
sdhci@78000600 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vdd_5v_in_reg: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "vdd_5v_in";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
chargepump_5v_reg: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "chargepump_5v";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
enable-active-high;
|
||||
gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
|
||||
};
|
||||
|
||||
ddr_reg: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "vdd_ddr";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */
|
||||
vin-supply = <&vdd_5v_in_reg>;
|
||||
};
|
||||
|
||||
vdd_5v_sata_reg: regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <3>;
|
||||
regulator-name = "vdd_5v_sata";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 30 0>; /* gpio PD6 */
|
||||
vin-supply = <&vdd_5v_in_reg>;
|
||||
};
|
||||
|
||||
usb1_vbus_reg: regulator@4 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <4>;
|
||||
regulator-name = "usb1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 68 0>; /* GPIO PI4 */
|
||||
gpio-open-drain;
|
||||
vin-supply = <&vdd_5v_in_reg>;
|
||||
};
|
||||
|
||||
usb3_vbus_reg: regulator@5 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <5>;
|
||||
regulator-name = "usb3_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 63 0>; /* GPIO PH7 */
|
||||
gpio-open-drain;
|
||||
vin-supply = <&vdd_5v_in_reg>;
|
||||
};
|
||||
|
||||
sys_3v3_reg: regulator@6 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <6>;
|
||||
regulator-name = "sys_3v3,vdd_3v3_alw";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */
|
||||
vin-supply = <&vdd_5v_in_reg>;
|
||||
};
|
||||
|
||||
sys_3v3_pexs_reg: regulator@7 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <7>;
|
||||
regulator-name = "sys_3v3_pexs";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 95 0>; /* gpio PL7 */
|
||||
vin-supply = <&sys_3v3_reg>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -106,12 +106,25 @@
|
||||
nvidia,slew-rate-rising = <1>;
|
||||
nvidia,slew-rate-falling = <1>;
|
||||
};
|
||||
uart3_txd_pw6 {
|
||||
nvidia,pins = "uart3_txd_pw6",
|
||||
"uart3_cts_n_pa1",
|
||||
"uart3_rts_n_pc0",
|
||||
"uart3_rxd_pw7";
|
||||
nvidia,function = "uartc";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial@70006000 {
|
||||
status = "okay";
|
||||
clock-frequency = <408000000>;
|
||||
};
|
||||
|
||||
serial@70006200 {
|
||||
compatible = "nvidia,tegra30-hsuart";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
|
||||
@ -4,6 +4,14 @@
|
||||
compatible = "nvidia,tegra30";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartb;
|
||||
serial2 = &uartc;
|
||||
serial3 = &uartd;
|
||||
serial4 = &uarte;
|
||||
};
|
||||
|
||||
host1x {
|
||||
compatible = "nvidia,tegra30-host1x", "simple-bus";
|
||||
reg = <0x50000000 0x00024000>;
|
||||
@ -113,15 +121,6 @@
|
||||
interrupts = <1 13 0xf04>;
|
||||
};
|
||||
|
||||
cache-controller@50043000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x50043000 0x1000>;
|
||||
arm,data-latency = <6 6 2>;
|
||||
arm,tag-latency = <5 5 2>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
reg = <0x50041000 0x1000
|
||||
@ -130,6 +129,15 @@
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
|
||||
cache-controller {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x50043000 0x1000>;
|
||||
arm,data-latency = <6 6 2>;
|
||||
arm,tag-latency = <5 5 2>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
timer@60005000 {
|
||||
compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
|
||||
reg = <0x60005000 0x400>;
|
||||
@ -191,7 +199,7 @@
|
||||
};
|
||||
|
||||
gpio: gpio {
|
||||
compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
|
||||
compatible = "nvidia,tegra30-gpio";
|
||||
reg = <0x6000d000 0x1000>;
|
||||
interrupts = <0 32 0x04
|
||||
0 33 0x04
|
||||
@ -213,47 +221,65 @@
|
||||
0x70003000 0x3e4>; /* Mux registers */
|
||||
};
|
||||
|
||||
serial@70006000 {
|
||||
/*
|
||||
* There are two serial driver i.e. 8250 based simple serial
|
||||
* driver and APB DMA based serial driver for higher baudrate
|
||||
* and performace. To enable the 8250 based driver, the compatible
|
||||
* is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
|
||||
* the APB DMA based serial driver, the comptible is
|
||||
* "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
|
||||
*/
|
||||
uarta: serial@70006000 {
|
||||
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006000 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <0 36 0x04>;
|
||||
clock-frequency = <408000000>;
|
||||
nvidia,dma-request-selector = <&apbdma 8>;
|
||||
clocks = <&tegra_car 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@70006040 {
|
||||
uartb: serial@70006040 {
|
||||
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006040 0x40>;
|
||||
reg-shift = <2>;
|
||||
clock-frequency = <408000000>;
|
||||
interrupts = <0 37 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 9>;
|
||||
clocks = <&tegra_car 160>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@70006200 {
|
||||
uartc: serial@70006200 {
|
||||
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006200 0x100>;
|
||||
reg-shift = <2>;
|
||||
clock-frequency = <408000000>;
|
||||
interrupts = <0 46 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 10>;
|
||||
clocks = <&tegra_car 55>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@70006300 {
|
||||
uartd: serial@70006300 {
|
||||
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006300 0x100>;
|
||||
reg-shift = <2>;
|
||||
clock-frequency = <408000000>;
|
||||
interrupts = <0 90 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 19>;
|
||||
clocks = <&tegra_car 65>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@70006400 {
|
||||
uarte: serial@70006400 {
|
||||
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006400 0x100>;
|
||||
reg-shift = <2>;
|
||||
clock-frequency = <408000000>;
|
||||
interrupts = <0 91 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 20>;
|
||||
clocks = <&tegra_car 66>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -392,6 +418,14 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
kbc {
|
||||
compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
|
||||
reg = <0x7000e200 0x100>;
|
||||
interrupts = <0 85 0x04>;
|
||||
clocks = <&tegra_car 36>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pmc {
|
||||
compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
@ -406,7 +440,7 @@
|
||||
interrupts = <0 77 0x04>;
|
||||
};
|
||||
|
||||
smmu {
|
||||
iommu {
|
||||
compatible = "nvidia,tegra30-smmu";
|
||||
reg = <0x7000f010 0x02c
|
||||
0x7000f1f0 0x010
|
||||
|
||||
Loading…
Reference in New Issue
Block a user