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6c452cff79
.get_state() might fail in some cases. To make it possible that a driver signals such a failure change the prototype of .get_state() to return an error code. This patch was created using coccinelle and the following semantic patch: @p1@ identifier getstatefunc; identifier driver; @@ struct pwm_ops driver = { ..., .get_state = getstatefunc ,... }; @p2@ identifier p1.getstatefunc; identifier chip, pwm, state; @@ -void +int getstatefunc(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_state *state) { ... - return; + return 0; ... } plus the actual change of the prototype in include/linux/pwm.h (plus some manual fixing of indentions and empty lines). So for now all drivers return success unconditionally. They are adapted in the following patches to make the changes easier reviewable. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com> Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Acked-by: Douglas Anderson <dianders@chromium.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Pavel Machek <pavel@ucw.cz> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20221130152148.2769768-2-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
324 lines
9.8 KiB
C
324 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021 Sean Anderson <sean.anderson@seco.com>
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*
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* Limitations:
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* - When changing both duty cycle and period, we may end up with one cycle
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* with the old duty cycle and the new period. This is because the counters
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* may only be reloaded by first stopping them, or by letting them be
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* automatically reloaded at the end of a cycle. If this automatic reload
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* happens after we set TLR0 but before we set TLR1 then we will have a
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* bad cycle. This could probably be fixed by reading TCR0 just before
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* reprogramming, but I think it would add complexity for little gain.
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* - Cannot produce 100% duty cycle by configuring the TLRs. This might be
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* possible by stopping the counters at an appropriate point in the cycle,
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* but this is not (yet) implemented.
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* - Only produces "normal" output.
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* - Always produces low output if disabled.
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*/
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#include <clocksource/timer-xilinx.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/regmap.h>
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/*
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* The following functions are "common" to drivers for this device, and may be
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* exported at a future date.
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*/
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u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr,
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u64 cycles)
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{
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WARN_ON(cycles < 2 || cycles - 2 > priv->max);
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if (tcsr & TCSR_UDT)
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return cycles - 2;
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return priv->max - cycles + 2;
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}
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unsigned int xilinx_timer_get_period(struct xilinx_timer_priv *priv,
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u32 tlr, u32 tcsr)
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{
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u64 cycles;
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if (tcsr & TCSR_UDT)
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cycles = tlr + 2;
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else
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cycles = (u64)priv->max - tlr + 2;
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/* cycles has a max of 2^32 + 2, so we can't overflow */
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return DIV64_U64_ROUND_UP(cycles * NSEC_PER_SEC,
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clk_get_rate(priv->clk));
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}
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/*
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* The idea here is to capture whether the PWM is actually running (e.g.
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* because we or the bootloader set it up) and we need to be careful to ensure
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* we don't cause a glitch. According to the data sheet, to enable the PWM we
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* need to
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*
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* - Set both timers to generate mode (MDT=1)
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* - Set both timers to PWM mode (PWMA=1)
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* - Enable the generate out signals (GENT=1)
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*
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* In addition,
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*
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* - The timer must be running (ENT=1)
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* - The timer must auto-reload TLR into TCR (ARHT=1)
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* - We must not be in the process of loading TLR into TCR (LOAD=0)
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* - Cascade mode must be disabled (CASC=0)
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*
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* If any of these differ from usual, then the PWM is either disabled, or is
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* running in a mode that this driver does not support.
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*/
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#define TCSR_PWM_SET (TCSR_GENT | TCSR_ARHT | TCSR_ENT | TCSR_PWMA)
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#define TCSR_PWM_CLEAR (TCSR_MDT | TCSR_LOAD)
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#define TCSR_PWM_MASK (TCSR_PWM_SET | TCSR_PWM_CLEAR)
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struct xilinx_pwm_device {
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struct pwm_chip chip;
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struct xilinx_timer_priv priv;
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};
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static inline struct xilinx_timer_priv
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*xilinx_pwm_chip_to_priv(struct pwm_chip *chip)
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{
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return &container_of(chip, struct xilinx_pwm_device, chip)->priv;
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}
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static bool xilinx_timer_pwm_enabled(u32 tcsr0, u32 tcsr1)
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{
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return ((TCSR_PWM_MASK | TCSR_CASC) & tcsr0) == TCSR_PWM_SET &&
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(TCSR_PWM_MASK & tcsr1) == TCSR_PWM_SET;
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}
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static int xilinx_pwm_apply(struct pwm_chip *chip, struct pwm_device *unused,
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const struct pwm_state *state)
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{
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struct xilinx_timer_priv *priv = xilinx_pwm_chip_to_priv(chip);
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u32 tlr0, tlr1, tcsr0, tcsr1;
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u64 period_cycles, duty_cycles;
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unsigned long rate;
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if (state->polarity != PWM_POLARITY_NORMAL)
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return -EINVAL;
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/*
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* To be representable by TLR, cycles must be between 2 and
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* priv->max + 2. To enforce this we can reduce the cycles, but we may
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* not increase them. Caveat emptor: while this does result in more
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* predictable rounding, it may also result in a completely different
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* duty cycle (% high time) than what was requested.
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*/
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rate = clk_get_rate(priv->clk);
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/* Avoid overflow */
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period_cycles = min_t(u64, state->period, U32_MAX * NSEC_PER_SEC);
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period_cycles = mul_u64_u32_div(period_cycles, rate, NSEC_PER_SEC);
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period_cycles = min_t(u64, period_cycles, priv->max + 2);
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if (period_cycles < 2)
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return -ERANGE;
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/* Same thing for duty cycles */
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duty_cycles = min_t(u64, state->duty_cycle, U32_MAX * NSEC_PER_SEC);
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duty_cycles = mul_u64_u32_div(duty_cycles, rate, NSEC_PER_SEC);
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duty_cycles = min_t(u64, duty_cycles, priv->max + 2);
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/*
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* If we specify 100% duty cycle, we will get 0% instead, so decrease
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* the duty cycle count by one.
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*/
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if (duty_cycles >= period_cycles)
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duty_cycles = period_cycles - 1;
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/* Round down to 0% duty cycle for unrepresentable duty cycles */
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if (duty_cycles < 2)
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duty_cycles = period_cycles;
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regmap_read(priv->map, TCSR0, &tcsr0);
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regmap_read(priv->map, TCSR1, &tcsr1);
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tlr0 = xilinx_timer_tlr_cycles(priv, tcsr0, period_cycles);
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tlr1 = xilinx_timer_tlr_cycles(priv, tcsr1, duty_cycles);
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regmap_write(priv->map, TLR0, tlr0);
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regmap_write(priv->map, TLR1, tlr1);
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if (state->enabled) {
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/*
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* If the PWM is already running, then the counters will be
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* reloaded at the end of the current cycle.
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*/
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if (!xilinx_timer_pwm_enabled(tcsr0, tcsr1)) {
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/* Load TLR into TCR */
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regmap_write(priv->map, TCSR0, tcsr0 | TCSR_LOAD);
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regmap_write(priv->map, TCSR1, tcsr1 | TCSR_LOAD);
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/* Enable timers all at once with ENALL */
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tcsr0 = (TCSR_PWM_SET & ~TCSR_ENT) | (tcsr0 & TCSR_UDT);
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tcsr1 = TCSR_PWM_SET | TCSR_ENALL | (tcsr1 & TCSR_UDT);
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regmap_write(priv->map, TCSR0, tcsr0);
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regmap_write(priv->map, TCSR1, tcsr1);
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}
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} else {
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regmap_write(priv->map, TCSR0, 0);
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regmap_write(priv->map, TCSR1, 0);
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}
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return 0;
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}
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static int xilinx_pwm_get_state(struct pwm_chip *chip,
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struct pwm_device *unused,
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struct pwm_state *state)
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{
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struct xilinx_timer_priv *priv = xilinx_pwm_chip_to_priv(chip);
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u32 tlr0, tlr1, tcsr0, tcsr1;
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regmap_read(priv->map, TLR0, &tlr0);
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regmap_read(priv->map, TLR1, &tlr1);
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regmap_read(priv->map, TCSR0, &tcsr0);
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regmap_read(priv->map, TCSR1, &tcsr1);
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state->period = xilinx_timer_get_period(priv, tlr0, tcsr0);
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state->duty_cycle = xilinx_timer_get_period(priv, tlr1, tcsr1);
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state->enabled = xilinx_timer_pwm_enabled(tcsr0, tcsr1);
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state->polarity = PWM_POLARITY_NORMAL;
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/*
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* 100% duty cycle results in constant low output. This may be (very)
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* wrong if rate > 1 GHz, so fix this if you have such hardware :)
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*/
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if (state->period == state->duty_cycle)
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state->duty_cycle = 0;
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return 0;
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}
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static const struct pwm_ops xilinx_pwm_ops = {
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.apply = xilinx_pwm_apply,
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.get_state = xilinx_pwm_get_state,
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.owner = THIS_MODULE,
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};
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static const struct regmap_config xilinx_pwm_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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.max_register = TCR1,
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};
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static int xilinx_pwm_probe(struct platform_device *pdev)
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{
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int ret;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct xilinx_timer_priv *priv;
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struct xilinx_pwm_device *xilinx_pwm;
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u32 pwm_cells, one_timer, width;
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void __iomem *regs;
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/* If there are no PWM cells, this binding is for a timer */
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ret = of_property_read_u32(np, "#pwm-cells", &pwm_cells);
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if (ret == -EINVAL)
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return -ENODEV;
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if (ret)
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return dev_err_probe(dev, ret, "could not read #pwm-cells\n");
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xilinx_pwm = devm_kzalloc(dev, sizeof(*xilinx_pwm), GFP_KERNEL);
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if (!xilinx_pwm)
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return -ENOMEM;
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platform_set_drvdata(pdev, xilinx_pwm);
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priv = &xilinx_pwm->priv;
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regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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priv->map = devm_regmap_init_mmio(dev, regs,
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&xilinx_pwm_regmap_config);
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if (IS_ERR(priv->map))
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return dev_err_probe(dev, PTR_ERR(priv->map),
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"Could not create regmap\n");
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ret = of_property_read_u32(np, "xlnx,one-timer-only", &one_timer);
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if (ret)
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return dev_err_probe(dev, ret,
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"Could not read xlnx,one-timer-only\n");
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if (one_timer)
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return dev_err_probe(dev, -EINVAL,
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"Two timers required for PWM mode\n");
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ret = of_property_read_u32(np, "xlnx,count-width", &width);
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if (ret == -EINVAL)
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width = 32;
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else if (ret)
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return dev_err_probe(dev, ret,
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"Could not read xlnx,count-width\n");
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if (width != 8 && width != 16 && width != 32)
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return dev_err_probe(dev, -EINVAL,
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"Invalid counter width %d\n", width);
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priv->max = BIT_ULL(width) - 1;
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/*
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* The polarity of the Generate Out signals must be active high for PWM
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* mode to work. We could determine this from the device tree, but
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* alas, such properties are not allowed to be used.
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*/
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priv->clk = devm_clk_get(dev, "s_axi_aclk");
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if (IS_ERR(priv->clk))
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return dev_err_probe(dev, PTR_ERR(priv->clk),
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"Could not get clock\n");
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ret = clk_prepare_enable(priv->clk);
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if (ret)
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return dev_err_probe(dev, ret, "Clock enable failed\n");
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clk_rate_exclusive_get(priv->clk);
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xilinx_pwm->chip.dev = dev;
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xilinx_pwm->chip.ops = &xilinx_pwm_ops;
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xilinx_pwm->chip.npwm = 1;
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ret = pwmchip_add(&xilinx_pwm->chip);
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if (ret) {
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clk_rate_exclusive_put(priv->clk);
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clk_disable_unprepare(priv->clk);
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return dev_err_probe(dev, ret, "Could not register PWM chip\n");
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}
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return 0;
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}
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static int xilinx_pwm_remove(struct platform_device *pdev)
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{
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struct xilinx_pwm_device *xilinx_pwm = platform_get_drvdata(pdev);
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pwmchip_remove(&xilinx_pwm->chip);
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clk_rate_exclusive_put(xilinx_pwm->priv.clk);
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clk_disable_unprepare(xilinx_pwm->priv.clk);
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return 0;
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}
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static const struct of_device_id xilinx_pwm_of_match[] = {
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{ .compatible = "xlnx,xps-timer-1.00.a", },
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{},
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};
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MODULE_DEVICE_TABLE(of, xilinx_pwm_of_match);
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static struct platform_driver xilinx_pwm_driver = {
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.probe = xilinx_pwm_probe,
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.remove = xilinx_pwm_remove,
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.driver = {
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.name = "xilinx-pwm",
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.of_match_table = of_match_ptr(xilinx_pwm_of_match),
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},
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};
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module_platform_driver(xilinx_pwm_driver);
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MODULE_ALIAS("platform:xilinx-pwm");
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MODULE_DESCRIPTION("PWM driver for Xilinx LogiCORE IP AXI Timer");
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MODULE_LICENSE("GPL");
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