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7a8d1ec16d
Since the default DMA ops for arm64 are non-coherent, mark the X-Gene controller explicitly as dma-coherent to avoid additional cache maintenance. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Loc Ho <lho@apm.com>
80 lines
2.3 KiB
Plaintext
80 lines
2.3 KiB
Plaintext
* APM X-Gene 6.0 Gb/s SATA host controller nodes
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SATA host controller nodes are defined to describe on-chip Serial ATA
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controllers. Each SATA controller (pair of ports) have its own node.
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Required properties:
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- compatible : Shall contain:
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* "apm,xgene-ahci"
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- reg : First memory resource shall be the AHCI memory
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resource.
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Second memory resource shall be the host controller
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core memory resource.
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Third memory resource shall be the host controller
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diagnostic memory resource.
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4th memory resource shall be the host controller
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AXI memory resource.
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5th optional memory resource shall be the host
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controller MUX memory resource if required.
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- interrupts : Interrupt-specifier for SATA host controller IRQ.
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- clocks : Reference to the clock entry.
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- phys : A list of phandles + phy-specifiers, one for each
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entry in phy-names.
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- phy-names : Should contain:
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* "sata-phy" for the SATA 6.0Gbps PHY
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Optional properties:
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- dma-coherent : Present if dma operations are coherent
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- status : Shall be "ok" if enabled or "disabled" if disabled.
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Default is "ok".
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Example:
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sataclk: sataclk {
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compatible = "fixed-clock";
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#clock-cells = <1>;
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clock-frequency = <100000000>;
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clock-output-names = "sataclk";
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};
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phy2: phy@1f22a000 {
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compatible = "apm,xgene-phy";
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reg = <0x0 0x1f22a000 0x0 0x100>;
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#phy-cells = <1>;
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};
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phy3: phy@1f23a000 {
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compatible = "apm,xgene-phy";
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reg = <0x0 0x1f23a000 0x0 0x100>;
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#phy-cells = <1>;
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};
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sata2: sata@1a400000 {
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compatible = "apm,xgene-ahci";
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reg = <0x0 0x1a400000 0x0 0x1000>,
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<0x0 0x1f220000 0x0 0x1000>,
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<0x0 0x1f22d000 0x0 0x1000>,
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<0x0 0x1f22e000 0x0 0x1000>,
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<0x0 0x1f227000 0x0 0x1000>;
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interrupts = <0x0 0x87 0x4>;
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dma-coherent;
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status = "ok";
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clocks = <&sataclk 0>;
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phys = <&phy2 0>;
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phy-names = "sata-phy";
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};
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sata3: sata@1a800000 {
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compatible = "apm,xgene-ahci-pcie";
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reg = <0x0 0x1a800000 0x0 0x1000>,
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<0x0 0x1f230000 0x0 0x1000>,
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<0x0 0x1f23d000 0x0 0x1000>,
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<0x0 0x1f23e000 0x0 0x1000>,
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<0x0 0x1f237000 0x0 0x1000>;
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interrupts = <0x0 0x88 0x4>;
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dma-coherent;
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status = "ok";
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clocks = <&sataclk 0>;
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phys = <&phy3 0>;
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phy-names = "sata-phy";
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};
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