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arm64: Mark the Applied Micro X-Gene SATA controller as DMA coherent
Since the default DMA ops for arm64 are non-coherent, mark the X-Gene controller explicitly as dma-coherent to avoid additional cache maintenance. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Loc Ho <lho@apm.com>
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@ -24,6 +24,7 @@ Required properties:
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* "sata-phy" for the SATA 6.0Gbps PHY
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Optional properties:
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- dma-coherent : Present if dma operations are coherent
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- status : Shall be "ok" if enabled or "disabled" if disabled.
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Default is "ok".
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@ -55,6 +56,7 @@ Example:
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<0x0 0x1f22e000 0x0 0x1000>,
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<0x0 0x1f227000 0x0 0x1000>;
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interrupts = <0x0 0x87 0x4>;
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dma-coherent;
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status = "ok";
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clocks = <&sataclk 0>;
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phys = <&phy2 0>;
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@ -69,6 +71,7 @@ Example:
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<0x0 0x1f23e000 0x0 0x1000>,
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<0x0 0x1f237000 0x0 0x1000>;
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interrupts = <0x0 0x88 0x4>;
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dma-coherent;
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status = "ok";
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clocks = <&sataclk 0>;
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phys = <&phy3 0>;
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@ -307,6 +307,7 @@
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<0x0 0x1f21e000 0x0 0x1000>,
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<0x0 0x1f217000 0x0 0x1000>;
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interrupts = <0x0 0x86 0x4>;
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dma-coherent;
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status = "disabled";
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clocks = <&sata01clk 0>;
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phys = <&phy1 0>;
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@ -321,6 +322,7 @@
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<0x0 0x1f22e000 0x0 0x1000>,
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<0x0 0x1f227000 0x0 0x1000>;
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interrupts = <0x0 0x87 0x4>;
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dma-coherent;
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status = "ok";
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clocks = <&sata23clk 0>;
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phys = <&phy2 0>;
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@ -334,6 +336,7 @@
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<0x0 0x1f23d000 0x0 0x1000>,
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<0x0 0x1f23e000 0x0 0x1000>;
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interrupts = <0x0 0x88 0x4>;
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dma-coherent;
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status = "ok";
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clocks = <&sata45clk 0>;
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phys = <&phy3 0>;
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