linux/drivers/gpu/drm/msm
Archit Taneja 621da7d93c drm/msm/mdp5: Add a CAP for Source Split
Some of the newer MDP5 versions support Source Split of SSPPs. It is a
feature that allows us to route the output of a hwpipe to 2 Layer
Mixers. This is required to achieve the following use cases:

- Dual DSI: For high res DSI panels (such as 2560x1600 etc), a single
  DSI interface doesn't have the bandwidth to drive the required pixel
  clock. We use 2 DSI interfaces to drive the left and right halves
  of the panel (i.e, 1280x1600 each). The MDP5 pipeline here would look
  like:

         LM0 -- DSPP0 -- INTF1 -- DSI1
        /
hwpipe--
        \
         LM1 -- DSPP1 -- INTF2 -- DSI2

  A single hwpipe is used to scan out the left and right halves to DSI1
  and DSI2 respectively. In order to do this, we need to configure the
  2 Layer Mixers in Source Split mode.

- HDMI 4K: In order to support resolutions with width higher than the
  max width supported by a hwpipe, we club 2 hwpipes together:

hwpipe1 --- LM0 -- DSPP0
       -   -             \
         -                -- 3D Mux -- INTF0 -- HDMI
       -   -             /
hwpipe2 --- LM1 -- DSPP1

  hwpipe1 is staged on the 'left' Layer Mixer, and hwpipe2 is staged on
  the 'right' Layer Mixer. An additional block called the '3D Mux' is
  used to merge the output of the 2 DSPPs to a single interface.
  In this use case, it is possible that a 4K surface is downscaled and
  placed completely within one of the halves. In order to support such
  scenarios (and keep the programming simple), Layer Mixers with Source
  Split can be assigned 2 hw pipes per stage. While scanning out, the HW
  takes care of fetching the pixels fom the correct pipe.

Add a MDP cap to tell whether the HW supports source split or not.
Add a MDP LM cap that tells whether a LM instance can operate in
source split mode (and generate the 'left' part of the display
output).

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-04-08 06:59:34 -04:00
..
adreno drm/msm: Pass interrupt status to a5xx_rbbm_err_irq() 2017-04-08 06:59:32 -04:00
dsi drm/msm/dsi: Fix bug in dsi_mgr_phy_enable 2017-04-08 06:59:32 -04:00
edp drm: bridge: Link encoder and bridge in core code 2016-12-18 16:31:45 +05:30
hdmi drm/msm/hdmi: redefinitions of macros not required 2017-04-08 06:59:33 -04:00
mdp drm/msm/mdp5: Add a CAP for Source Split 2017-04-08 06:59:34 -04:00
Kconfig drm/msm/dsi: Add PHY/PLL for 8x96 2017-02-06 11:28:45 -05:00
Makefile drm/msm/mdp5: Add structs for hw Layer Mixers 2017-04-08 06:59:33 -04:00
msm_atomic.c drm/msm/mdp5: Add cursor planes 2017-02-06 11:28:44 -05:00
msm_debugfs.c drm/msm/gpu: use pm-runtime 2017-04-08 06:59:31 -04:00
msm_debugfs.h drm/msm: Remove msm_debugfs_cleanup() 2017-03-08 11:24:45 +01:00
msm_drv.c drm/msm: Don't increase priv->num_aspaces until we know that it fits 2017-04-08 06:59:32 -04:00
msm_drv.h drm/msm: add stubs for msm_{perf,rd}_debugfs_cleanup 2017-03-20 15:34:01 +01:00
msm_fb.c drm: Nuke fb->pixel_format 2016-12-15 14:55:34 +02:00
msm_fbdev.c drm/fb-helper: Automatically clean up fb_info 2017-02-07 21:36:28 +01:00
msm_fence.c dma-buf: Rename struct fence to dma_fence 2016-10-25 14:40:39 +02:00
msm_fence.h dma-buf: Rename struct fence to dma_fence 2016-10-25 14:40:39 +02:00
msm_gem_prime.c drm/msm: change gem->vmap() to get/put 2016-07-16 10:09:07 -04:00
msm_gem_shrinker.c Merge branch 'linus' into locking/core, to pick up fixes 2016-11-22 12:37:38 +01:00
msm_gem_submit.c drm/msm: move submit fence wait out of struct_mutex 2017-04-08 06:59:31 -04:00
msm_gem_vma.c drm: Improve drm_mm search (and fix topdown allocation) with rbtrees 2017-02-03 11:10:32 +01:00
msm_gem.c drm/msm: Don't allow zero sized buffer objects 2017-04-08 06:59:32 -04:00
msm_gem.h drm/msm: convert iova to 64b 2016-11-28 15:14:08 -05:00
msm_gpu.c drm/msm/gpu: use pm-runtime 2017-04-08 06:59:31 -04:00
msm_gpu.h drm/msm/gpu: use pm-runtime 2017-04-08 06:59:31 -04:00
msm_iommu.c drm/msm: pm runtime support for iommu 2017-04-08 06:59:31 -04:00
msm_kms.h drm/msm: Remove msm_debugfs_cleanup() 2017-03-08 11:24:45 +01:00
msm_mmu.h drm/msm: let gpu wire up it's own fault handler 2017-02-06 11:28:42 -05:00
msm_perf.c drm/msm: Remove msm_debugfs_cleanup() 2017-03-08 11:24:45 +01:00
msm_rd.c drm/msm: Support 64 bit iova in RD_CMDSTREAM_ADDR 2017-04-08 06:59:32 -04:00
msm_ringbuffer.c drm/msm: Ensure that the hardware write pointer is valid 2016-12-29 15:02:58 -05:00
msm_ringbuffer.h
NOTES