mirror of
https://github.com/torvalds/linux.git
synced 2024-11-27 06:31:52 +00:00
1a5a2cbd21
Zong Li <zong.li@sifive.com> says: Since composable cache may be L3 cache if private L2 cache exists, we should use its original name "composable cache" to prevent confusion. This patchset contains the modification which is related to ccache, such as DT binding and EDAC driver. * b4-shazam-merge: riscv: Add cache information in AUX vector soc: sifive: ccache: define the macro for the register shifts soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes soc: sifive: ccache: reduce printing on init soc: sifive: ccache: determine the cache level from dts soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Link: https://lore.kernel.org/r/20220913061817.22564-1-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
||
|---|---|---|
| .. | ||
| actions | ||
| amlogic | ||
| apple | ||
| aspeed | ||
| atmel | ||
| bcm | ||
| canaan | ||
| dove | ||
| fsl | ||
| fujitsu | ||
| gemini | ||
| imx | ||
| ixp4xx | ||
| lantiq | ||
| litex | ||
| mediatek | ||
| microchip | ||
| pxa | ||
| qcom | ||
| renesas | ||
| rockchip | ||
| samsung | ||
| sifive | ||
| sunxi | ||
| tegra | ||
| ti | ||
| ux500 | ||
| versatile | ||
| xilinx | ||
| Kconfig | ||
| Makefile | ||