Sathya Perla f3eb62d2cc be2net: memory barrier fixes on IBM p7 platform ... The ibm p7 architecure seems to reorder memory accesses more aggressively than previous ppc64 architectures. This requires memory barriers to ensure that rx/tx doorbells are pressed only after memory to be DMAed is written. Signed-off-by: Sathya Perla <sathyap@serverengines.com> Signed-off-by: David S. Miller <davem@davemloft.net>		2010-06-30 13:26:42 -07:00
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be_cmds.c	be2net: memory barrier fixes on IBM p7 platform	2010-06-30 13:26:42 -07:00
be_cmds.h	be2net: Adding PCI SRIOV support	2010-04-01 19:53:14 -07:00
be_ethtool.c	drivers/net: Remove unnecessary returns from void function()s	2010-05-14 00:19:28 -07:00
be_hw.h	be2net: enable ipv6 tso support	2010-06-16 18:13:28 -07:00
be_main.c	be2net: memory barrier fixes on IBM p7 platform	2010-06-30 13:26:42 -07:00
be.h	be2net: Bug fix to avoid disabling bottom half during firmware upgrade.	2010-05-25 16:16:32 -07:00
Kconfig	be2net: remove ASIC generation number from Kconfig	2010-02-12 12:28:00 -08:00
Makefile