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be2net: memory barrier fixes on IBM p7 platform
The ibm p7 architecure seems to reorder memory accesses more aggressively than previous ppc64 architectures. This requires memory barriers to ensure that rx/tx doorbells are pressed only after memory to be DMAed is written. Signed-off-by: Sathya Perla <sathyap@serverengines.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -25,6 +25,8 @@ static void be_mcc_notify(struct be_adapter *adapter)
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val |= mccq->id & DB_MCCQ_RING_ID_MASK;
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val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
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wmb();
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iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
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}
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@ -89,6 +89,8 @@ static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
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u32 val = 0;
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val |= qid & DB_RQ_RING_ID_MASK;
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val |= posted << DB_RQ_NUM_POSTED_SHIFT;
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wmb();
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iowrite32(val, adapter->db + DB_RQ_OFFSET);
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}
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@ -97,6 +99,8 @@ static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
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u32 val = 0;
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val |= qid & DB_TXULP_RING_ID_MASK;
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val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
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wmb();
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iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
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}
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@ -973,6 +977,7 @@ static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
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if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
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return NULL;
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rmb();
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be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
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queue_tail_inc(&adapter->rx_obj.cq);
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@ -1066,6 +1071,7 @@ static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
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if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
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return NULL;
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rmb();
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be_dws_le_to_cpu(txcp, sizeof(*txcp));
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txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
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@ -1113,6 +1119,7 @@ static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
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if (!eqe->evt)
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return NULL;
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rmb();
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eqe->evt = le32_to_cpu(eqe->evt);
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queue_tail_inc(&eq_obj->q);
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return eqe;
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