10717 Commits

Author	SHA1	Message	Date
Uwe Kleine-König	f00b45db02	clk: Switch back to struct platform_driver::remove() ... After commit 0edb555a65 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all clk drivers to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/20240909144026.870565-2-u.kleine-koenig@baylibre.com Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-09-21 14:12:05 -07:00
Stephen Boyd	1b189f71e1	Merge branches 'clk-devm', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into clk-next ... * clk-devm: clk: provide devm_clk_get_optional_enabled_with_rate() clk: fixed-rate: add devm_clk_hw_register_fixed_rate_parent_data() * clk-samsung: clk: samsung: add top clock support for ExynosAuto v920 SoC clk: samsung: clk-pll: Add support for pll_531x dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings clk: samsung: exynos7885: Add USB related clocks to CMU_FSYS clk: samsung: clk-pll: Add support for pll_1418x clk: samsung: exynosautov9: add dpum clock support dt-bindings: clock: exynosautov9: add dpum clock clk: samsung: exynos7885: Add missing MUX clocks from PLLs in CMU_TOP clk: samsung: exynos7885: Update CLKS_NR_FSYS after bindings fix dt-bindings: clock: exynos7885: Add indices for USB clocks dt-bindings: clock: exynos7885: Add CMU_TOP PLL MUX indices dt-bindings: clock: exynos7885: Fix duplicated binding clk: samsung: exynos850: Add TMU clock dt-bindings: clock: exynos850: Add TMU clock * clk-rockchip: dt-bindings: clock, reset: fix top-comment indentation rk3576 headers clk: rockchip: remove unused mclk_pdm0_p/pdm0_p definitions clk: rockchip: fix error for unknown clocks clk: rockchip: rk3588: drop unused code clk: rockchip: Add clock controller for the RK3576 clk: rockchip: Add new pll type pll_rk3588_ddr dt-bindings: clock, reset: Add support for rk3576 dt-bindings: clock: rockchip,rk3588-cru: drop unneeded assigned-clocks clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_p dt-bindings: clock: rockchip: remove CLK_NR_CLKS and CLKPMU_NR_CLKS clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage clk: rockchip: rk3368: Drop CLK_NR_CLKS usage clk: rockchip: rk3328: Drop CLK_NR_CLKS usage clk: rockchip: rk3308: Drop CLK_NR_CLKS usage clk: rockchip: rk3288: Drop CLK_NR_CLKS usage clk: rockchip: rk3228: Drop CLK_NR_CLKS usage clk: rockchip: rk3036: Drop CLK_NR_CLKS usage clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228 * clk-qcom: (47 commits) clk: qcom: videocc-sm8550: Use HW_CTRL_TRIGGER flag for video GDSC's clk: qcom: dispcc-sm8250: use special function for Lucid 5LPE PLL clk: qcom: dispcc-sm8250: use CLK_SET_RATE_PARENT for branch clocks clk: qcom: ipq5332: Use icc-clk for enabling NoC related clocks clk: qcom: ipq5332: Register gcc_qdss_tsctr_clk_src dt-bindings: usb: qcom,dwc3: Update ipq5332 clock details dt-bindings: interconnect: Add Qualcomm IPQ5332 support clk: qcom: gcc-msm8998: Add Q6 BIMC and LPASS core, ADSP SMMU clocks dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions clk: qcom: Fix SM_CAMCC_8150 dependencies clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src clk: qcom: gcc-sc8180x: Fix the sdcc2 and sdcc4 clocks freq table clk: qcom: gcc-sc8180x: Add GPLL9 support dt-bindings: clock: qcom: Add GPLL9 support on gcc-sc8180x clk: qcom: gcc-sc8180x: Register QUPv3 RCGs for DFS on sc8180x clk: qcom: clk-rpmh: Fix overflow in BCM vote dt-bindings: clock: qcom: Drop required-opps in required on SM8650 camcc dt-bindings: clock: qcom: Drop required-opps in required on sm8650 videocc dt-bindings: clock: qcom,qcs404-turingcc: convert to dtschema dt-bindings: clock: Add x1e80100 LPASSCC reset controller ...	2024-09-21 14:11:05 -07:00
Stephen Boyd	6629108252	Merge branches 'clk-amlogic', 'clk-microchip' and 'clk-imx' into clk-next ... * clk-amlogic: clk: meson: introduce symbol namespace for amlogic clocks clk: meson: axg-audio: add sm1 earcrx clocks clk: meson: axg-audio: setup regmap max_register based on the SoC dt-bindings: clock: axg-audio: add earcrx clock ids clk: meson: s4: pll: Constify struct regmap_config clk: meson: s4: peripherals: Constify struct regmap_config clk: meson: c3: pll: Constify struct regmap_config clk: meson: c3: peripherals: Constify struct regmap_config clk: meson: a1: pll: Constify struct regmap_config clk: meson: a1: peripherals: Constify struct regmap_config * clk-microchip: clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs clk: at91: sam9x7: add sam9x7 pmc driver dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT clk: at91: sama7g5: move mux table macros to header file clk: at91: sam9x7: add support for HW PLL freq dividers clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs dt-bindings: clocks: atmel,at91rm9200-pmc: add sam9x7 clock controller dt-bindings: clocks: atmel,at91sam9x5-sckc: add sam9x7 * clk-imx: (27 commits) clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL clk: imx95: enable the clock of NETCMIX block control dt-bindings: clock: add RMII clock selection dt-bindings: clock: add i.MX95 NETCMIX block control clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data clk: imx: composite-7ulp: Use NULL instead of 0 clk: imx: add missing MODULE_DESCRIPTION() macros clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate clk: imx: fracn-gppll: update rate table clk: imx: imx8qxp: Parent should be initialized earlier than the clock clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks clk: imx: imx8qxp: Add LVDS bypass clocks clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one clk: imx: imx8mn: add sai7_ipg_clk clock settings clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D clk: imx: imx8mp: fix clock tree update of TF-A managed clocks clk: imx: fracn-gppll: fix fractional part of PLL getting lost clk: imx: composite-7ulp: Check the PCC present bit ...	2024-09-21 14:10:59 -07:00
Stephen Boyd	c7183ff52f	Merge branches 'clk-assigned-rates', 'clk-renesas' and 'clk-scmi' into clk-next ... * clk-assigned-rates: clk: clk-conf: support assigned-clock-rates-u64 * clk-renesas: (34 commits) clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT clk: renesas: rzv2h: Add support for dynamic switching divider clocks clk: renesas: r9a08g045: Add clocks, resets and power domains for USB dt-bindings: clock: renesas,cpg-clocks: Add top-level constraints clk: renesas: r8a779h0: Add CANFD clock clk: renesas: Add RZ/V2H(P) CPG driver clk: renesas: Add family-specific clock driver for RZ/V2H(P) dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG clk: renesas: r8a779h0: Add PWM clock dt-bindings: clock: renesas,cpg-mssr: Document RZ/G2M v3.0 (r8a774a3) clock clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs clk: renesas: rcar-gen4: Remove unused fixed PLL clock types clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs clk: renesas: r8a779a0: Use defines for PLL control registers clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs clk: renesas: rcar-gen4: Add support for fixed variable PLLs clk: renesas: rcar-gen4: Add support for variable fractional PLLs ... * clk-scmi: clk: scmi: add is_prepared hook	2024-09-21 14:10:53 -07:00
Stephen Boyd	a2b88026f7	Merge branches 'clk-kunit', 'clk-mediatek', 'clk-cleanup' and 'clk-bindings' into clk-next ... - KUnit tests for clk registration and fixed rate basic clk type * clk-kunit: clk: Add KUnit tests for clks registered with struct clk_parent_data clk: Add KUnit tests for clk fixed rate basic type clk: Add test managed clk provider/consumer APIs platform: Add test managed platform_device/driver APIs of: Add a KUnit test for overlays and test managed APIs dt-bindings: vendor-prefixes: Add "test" vendor for KUnit and friends of: Add test managed wrappers for of_overlay_apply()/of_node_put() of/platform: Allow overlays to create platform devices from the root node * clk-mediatek: dt-bindings: clock: mediatek: Convert MediaTek clock syscons to schema dt-bindings: Move Mediatek clock controllers to "clock" directory dt-bindings: clock: mediatek,apmixedsys: Fix "mediatek,mt6779-apmixed" compatible clk: mediatek: reset: Remove unused mtk_register_reset_controller() clk: mediatek: reset: Return regmap's error code * clk-cleanup: clk: starfive: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage clk: ti: dra7-atl: Fix leak of of_nodes clk:davinci: make use of dev_err_cast_probe() clk: bcm: bcm53573: fix OF node leak in init clk: lmk04832: Use devm_clk_get_enabled() helpers clk: visconti: Switch to use kmemdup_array() clk: mmp: Switch to use kmemdup_array() clk: hisilicon: Remove unnecessary local variable clk: use clk_core_unlink_consumer() helper clk: Use of_property_present() clk: at91: Use of_property_count_u32_elems() to get property length da8xx-cfgchip.c: replace of_node_put with __free improves cleanup * clk-bindings: dt-bindings: clock: st,stm32mp1-rcc: add top-level constraints dt-bindings: clock: cirrus,lochnagar: add top-level constraints dt-bindings: clock: baikal,bt1-ccu-div: add top-level constraints dt-bindings: clock: nxp,lpc3220-usb-clk: Convert bindings to dtschema dt-bindings: clock: nxp,lpc3220-clk: Convert bindings to DT schema	2024-09-21 14:10:42 -07:00
Arnd Bergmann	4500f510d9	clk: rockchip: remove unused mclk_pdm0_p/pdm0_p definitions ... When -Wunused-const-variable is enabled (not the default), there is a warning about two definitions in this file: In file included from drivers/clk/rockchip/clk-rk3576.c:14: drivers/clk/rockchip/clk-rk3576.c:334:7: error: 'mclk_pdm0_p' defined but not used [-Werror=unused-const-variable=] 334 | PNAME(mclk_pdm0_p) = { "mclk_pdm0_src_top", "xin24m" }; | ^~~~~~~~~~~ drivers/clk/rockchip/clk.h:564:43: note: in definition of macro 'PNAME' 564 | #define PNAME(x) static const char *const x[] __initconst | ^ drivers/clk/rockchip/clk-rk3576.c:333:7: error: 'pdm0_p' defined but not used [-Werror=unused-const-variable=] 333 | PNAME(pdm0_p) = { "clk_pdm0_src_top", "xin24m" }; | ^~~~~~ drivers/clk/rockchip/clk.h:564:43: note: in definition of macro 'PNAME' 564 | #define PNAME(x) static const char *const x[] __initconst | ^ Remove them for the moment. If they are needed later, they can be added back at that point. Fixes: cc40f5baa9 ("clk: rockchip: Add clock controller for the RK3576") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20240909121116.254036-1-arnd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-09-09 14:10:32 -07:00
Bartosz Golaszewski	9934a1bd45	clk: provide devm_clk_get_optional_enabled_with_rate() ... There are clock users in the kernel that can't use devm_clk_get_optional_enabled() as they need to set rate after getting the clock and before enabling it. Provide a managed helper that wraps these operations in the correct order. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20240805-clk-new-helper-v2-1-e5fdd1e1d729@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-09-05 13:51:46 -07:00
Stephen Boyd	a09e3cf770	Merge branch 'clk-imx-old' into clk-imx ... * clk-imx: (22 commits) clk: imx: composite-7ulp: Use NULL instead of 0 clk: imx: add missing MODULE_DESCRIPTION() macros clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate clk: imx: fracn-gppll: update rate table clk: imx: imx8qxp: Parent should be initialized earlier than the clock clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks clk: imx: imx8qxp: Add LVDS bypass clocks clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one clk: imx: imx8mn: add sai7_ipg_clk clock settings clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D clk: imx: imx8mp: fix clock tree update of TF-A managed clocks clk: imx: fracn-gppll: fix fractional part of PLL getting lost clk: imx: composite-7ulp: Check the PCC present bit clk: imx: composite-93: keep root clock on when mcore enabled clk: imx: composite-8m: Enable gate clk with mcore_booted clk: imx: imx6ul: fix default parent for enet*_ref_sel clk: imx: clk-audiomix: Correct parent clock for earc_phy and audpll clk: imx: clk-audiomix: Add CLK_SET_RATE_PARENT flags for clocks ...	2024-09-05 11:30:59 -07:00
Michel Alex	32c055ef56	clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL ... Commit 4e197ee880 ("clk: imx6ul: add ethernet refclock mux support") sets the internal clock as default ethernet clock. Since IMX6UL_CLK_ENET_REF cannot be parent for IMX6UL_CLK_ENET1_REF_SEL, the call to clk_set_parent() fails. IMX6UL_CLK_ENET1_REF_125M is the correct parent and shall be used instead. Same applies for IMX6UL_CLK_ENET2_REF_SEL, for which IMX6UL_CLK_ENET2_REF_125M is the correct parent. Cc: stable@vger.kernel.org Signed-off-by: Alex Michel <alex.michel@wiedemann-group.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.kernel.org/r/AS1P250MB0608F9CE4009DCE65C61EEDEA9922@AS1P250MB0608.EURP250.PROD.OUTLOOK.COM Signed-off-by: Abel Vesa <abel.vesa@linaro.org>	2024-09-04 12:39:38 +03:00
Lad Prabhakar	3aeccbe081	clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT ... Add clock and reset entries for Generic Timer (GTM), I2C Bus Interface (RIIC), SD/MMC Host Interface (SDHI) and Watchdog Timer (WDT) IP blocks. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828093822.162855-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2024-09-02 10:15:38 +02:00
Lad Prabhakar	bc4d25fdfa	clk: renesas: rzv2h: Add support for dynamic switching divider clocks ... Add support for dynamic switching divider clocks. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828093822.162855-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2024-09-02 10:15:38 +02:00
Claudiu Beznea	f0fe60cae6	clk: renesas: r9a08g045: Add clocks, resets and power domains for USB ... Add clocks, resets and power domains for USB modules available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240822152801.602318-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2024-09-02 10:15:31 +02:00
Sebastian Reichel	12fd64baba	clk: rockchip: fix error for unknown clocks ... There is a clk == NULL check after the switch to check for unsupported clk types. Since clk is re-assigned in a loop, this check is useless right now for anything but the first round. Let's fix this up by assigning clk = NULL in the loop before the switch statement. Fixes: a245fecbb8 ("clk: rockchip: add basic infrastructure for clock branches") Cc: stable@vger.kernel.org Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> [added fixes + stable-cc] Link: https://lore.kernel.org/r/20240325193609.237182-6-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-30 16:59:24 +02:00
Sebastian Reichel	2e7b3daa8c	clk: rockchip: rk3588: drop unused code ... All clocks are registered early using CLK_OF_DECLARE(), which marks the DT node as processed. For the processed DT node the probe routine is never called. Thus this whole code is never executed. This could be "fixed" by using CLK_OF_DECLARE_DRIVER, which avoids marking the DT node as processed. But then the probe routine would re-register all the clocks by calling rk3588_clk_init() again. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240325193609.237182-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-30 16:59:24 +02:00
Elaine Zhang	cc40f5baa9	clk: rockchip: Add clock controller for the RK3576 ... Add the clock and reset tree definitions for the new RK3576 SoC. As opposed to the other rockchip CRU drivers, the GRF node is looked up via compatible instead of a phandle, which simplifies the device tree bindings. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Reviewed-by: Elaine Zhang <zhangqing@rock-chips.com> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/0102019199a7781a-888440f0-a3f7-4a7d-a831-491260cbdfe7-000000@eu-west-1.amazonses.com [dropped additional blank line at EOF in rst-rk3576.c dropped the whole (non-)working as module part] Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-29 11:13:33 +02:00
Elaine Zhang	e781bffc29	clk: rockchip: Add new pll type pll_rk3588_ddr ... That PLL type is similar to the other rk3588 pll types but the actual rate is twice the configured rate. Therefore, the returned calculated rate must be multiplied by two. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Acked-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/0102019199a76ec4-9d5846d4-d76a-4e69-a241-c88c2983d607-000000@eu-west-1.amazonses.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-29 11:13:28 +02:00
Alexander Shiyan	0d02e8d284	clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_p ... The 32kHz input clock is named "xin32k" in the driver, so the name "32k" appears to be a typo in this case. Lets fix this. Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Fixes: f1c506d152 ("clk: rockchip: add clock controller for the RK3588") Link: https://lore.kernel.org/r/20240829052820.3604-1-eagle.alexander923@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-29 10:05:23 +02:00
Wei Fang	42dc425fa8	clk: imx95: enable the clock of NETCMIX block control ... The NETCMIX block control consists of registers for configuration of peripherals in the NETC domain, so enable the clock of NETCMIX to support the configuration. Signed-off-by: Wei Fang <wei.fang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20240829011849.364987-4-wei.fang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>	2024-08-29 10:02:18 +03:00
Shengjiu Wang	35121e9def	clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data ... "acm_aud_clk0_sel" and "acm_aud_clk1_sel" are registered by this ACM driver, but they are the parent clocks for other clocks, in order to use assigned-clock-parents in device tree, the ".fw_name" can't be used, need to assign the clk_hw pointer for the imx8qm_mclk_sels[], imx8qxp_mclk_sels[], imx8dxl_mclk_sels[]. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/1720600860-18866-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>	2024-08-29 10:01:02 +03:00
Yuntao Liu	55c312c1b2	clk: starfive: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage ... We need to call pm_runtime_put_noidle() when pm_runtime_get_sync() fails, so use pm_runtime_resume_and_get() instead. this function will handle this. Fixes: dae5448a32 ("clk: starfive: Add StarFive JH7110 Video-Output clock driver") Signed-off-by: Yuntao Liu <liuyuntao12@huawei.com> Link: https://lore.kernel.org/r/20240815093853.757487-1-liuyuntao12@huawei.com Reviewed-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-08-28 13:20:05 -07:00
David Lechner	9d6e9f10e2	clk: ti: dra7-atl: Fix leak of of_nodes ... This fix leaking the of_node references in of_dra7_atl_clk_probe(). The docs for of_parse_phandle_with_args() say that the caller must call of_node_put() on the returned node. This adds the missing of_node_put() to fix the leak. Fixes: 9ac33b0ce8 ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)") Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://lore.kernel.org/r/20240826-clk-fix-leak-v1-1-f55418a13aa6@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-08-28 13:17:30 -07:00
Yuesong Li	df7e70e38c	clk:davinci: make use of dev_err_cast_probe() ... Using dev_err_cast_probe() to simplify the code. Signed-off-by: Yuesong Li <liyuesong@vivo.com> Link: https://lore.kernel.org/r/20240828073515.950677-1-liyuesong@vivo.com Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-08-28 13:11:21 -07:00
Johan Jonker	1a22986885	clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage ... In order to get rid of CLK_NR_CLKS and CLKPMU_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/45f83b1f-64f8-4ea5-bc93-ebf7507a9709@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-28 21:25:50 +02:00
Johan Jonker	41563197e7	clk: rockchip: rk3368: Drop CLK_NR_CLKS usage ... In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/2a19c3cc-5f4d-4d03-90b2-e0bb13b0502f@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-28 21:25:50 +02:00
Johan Jonker	0758fe99bc	clk: rockchip: rk3328: Drop CLK_NR_CLKS usage ... In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/38ea6be0-3596-49ec-8de9-aef9c7f2bbb6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-28 21:25:50 +02:00
Johan Jonker	31fe149568	clk: rockchip: rk3308: Drop CLK_NR_CLKS usage ... In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/9fbca2d8-f904-4913-ba05-8715e748a454@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-28 21:25:50 +02:00
Johan Jonker	545b1313c5	clk: rockchip: rk3288: Drop CLK_NR_CLKS usage ... In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/af141286-7994-4e3f-93e2-6ee4e718ef8a@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-28 21:25:49 +02:00
Johan Jonker	819b2e19a9	clk: rockchip: rk3228: Drop CLK_NR_CLKS usage ... In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/2ee6f0a5-a1bb-4b62-ae6b-8f3828f8eccc@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-28 21:25:49 +02:00
Johan Jonker	ec4f4261c3	clk: rockchip: rk3036: Drop CLK_NR_CLKS usage ... In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/c8e73847-f472-4473-ac55-068cb28b98f6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-28 21:25:49 +02:00
Johan Jonker	2496910c84	clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage ... In order to get rid of CLK_NR_CLKS and CLKPMU_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/5ad12808-61f5-4e3b-801e-85231375b6a6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-28 21:25:49 +02:00
Krzysztof Kozlowski	f92d67e23b	clk: bcm: bcm53573: fix OF node leak in init ... Driver code is leaking OF node reference from of_get_parent() in bcm53573_ilp_init(). Usage of of_get_parent() is not needed in the first place, because the parent node will not be freed while we are processing given node (triggered by CLK_OF_DECLARE()). Thus fix the leak by accessing parent directly, instead of of_get_parent(). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240826065801.17081-1-krzysztof.kozlowski@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-08-28 11:54:22 -07:00
Huan Yang	f7e41b65bd	clk: lmk04832: Use devm_clk_get_enabled() helpers ... The devm_clk_get_enabled() helpers: - call devm_clk_get() - call clk_prepare_enable() and register what is needed in order to call clk_disable_unprepare() when needed, as a managed resource. This simplifies the code and avoids the calls to clk_disable_unprepare(). Signed-off-by: Huan Yang <link@vivo.com> Link: https://lore.kernel.org/r/20240820102119.130298-1-link@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-08-27 17:25:04 -07:00
Peng Fan	fc953d40bd	clk: scmi: add is_prepared hook ... Some clocks maybe default enabled by hardware. For clocks that don't have users, that will be left in hardware default state, because prepare count and enable count is zero,if there is no is_prepared hook to get the hardware state. So add is_prepared hook to detect the hardware state. Then when disabling the unused clocks, they can be simply turned OFF to save power during kernel boot. Reviewed-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20240806145601.1184337-1-peng.fan@oss.nxp.com Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-08-27 12:11:45 -07:00
Claudiu Beznea	2d6e9ee7cb	clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs ... The maximum number of PLL components on SAMA7G5 is 3 (one fractional part and 2 dividers). Allocate the needed amount of memory for sama7g5_plls 2d array. Previous code used to allocate 7 array entries for each PLL. While at it, replace 3 with PLL_COMPID_MAX in the loop which parses the sama7g5_plls 2d array. Fixes: cb783bbbcf ("clk: at91: sama7g5: add clock support for sama7g5") Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240714141315.19480-1-claudiu.beznea@tuxon.dev Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>	2024-08-24 17:44:11 +03:00
Sunyeal Hong	485e13fe2f	clk: samsung: add top clock support for ExynosAuto v920 SoC ... This adds support for CMU_TOP which generates clocks for all the function blocks such as CORE, HSI0/1/2, PERIC0/1 and so on. For CMU_TOP, PLL_SHARED0,1,2,3,4 and 5 will be the sources of this block and they will generate bus clocks. Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> Link: https://lore.kernel.org/r/20240821232652.1077701-5-sunyeal.hong@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2024-08-23 09:21:35 +02:00
Sunyeal Hong	9224e288f2	clk: samsung: clk-pll: Add support for pll_531x ... pll531x PLL is used in Exynos Auto v920 SoC for shared pll. pll531x: Integer/fractional PLL with mid frequency FVCO (800 to 3120 MHz) PLL531x FOUT = (MDIV x FIN)/(PDIV x 2^SDIV) for integer PLL FOUT = (MDIV + F/2^32-F[31]) x FIN/(PDIV x 2^SDIV) for fractional PLL Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20240821232652.1077701-4-sunyeal.hong@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2024-08-23 09:21:28 +02:00
David Virag	011a9de997	clk: samsung: exynos7885: Add USB related clocks to CMU_FSYS ... Exynos7885 SoC has a DWC3 USB Controller with Exynos USB PHY which in theory supports USB3 SuperSpeed, but is only used as USB2 in all known devices. These clocks are needed for everything related to USB. While at it, also remove the CLK_SET_RATE_PARENT capability of CLK_MOUT_FSYS_USB30DRD_USER, since it's not actually needed. Signed-off-by: David Virag <virag.david003@gmail.com> Link: https://lore.kernel.org/r/20240816175034.769628-3-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2024-08-21 13:20:08 +02:00
David Virag	4e39e5b843	clk: samsung: clk-pll: Add support for pll_1418x ... pll1418x is used in Exynos7885 SoC for USB PHY clock. Operation-wise it is very similar to pll0822x, except that MDIV is only 9 bits wide instead of 10, and we use the CON1 register in the PLL macro's "con" parameter instead of CON3 like this: PLL(pll_1418x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk", PLL_LOCKTIME_PLL_USB, PLL_CON0_PLL_USB, pll_usb_rate_table), Technically the PLL should work fine with pll0822x code if the PLL tables are correct, but it's more "correct" to actually update the mask. Signed-off-by: David Virag <virag.david003@gmail.com> Link: https://lore.kernel.org/r/20240816175034.769628-2-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2024-08-21 13:20:07 +02:00
Vedang Nagar	d628455ab3	clk: qcom: videocc-sm8550: Use HW_CTRL_TRIGGER flag for video GDSC's ... The video driver will be using the newly introduced dev_pm_genpd_set_hwmode() API to switch the video GDSC to HW/SW control modes at runtime. Hence use HW_CTRL_TRIGGER flag instead of HW_CTRL for video GDSC's. Signed-off-by: Vedang Nagar <quic_vnagar@quicinc.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240812134752.28031-1-quic_vnagar@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2024-08-20 17:15:16 -05:00
Cong Dang	120c2833b7	clk: renesas: r8a779h0: Add CANFD clock ... Add the CANFD module clock on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/9bf71bfda338ee5411751174b03b9e870cc818e3.1722519424.git.geert+renesas@glider.be	2024-08-20 09:48:24 +02:00
Lad Prabhakar	36932cbc3e	clk: renesas: Add RZ/V2H(P) CPG driver ... Add RZ/V2H(P) CPG driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240729202645.263525-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2024-08-20 09:48:24 +02:00
Peng Fan	965e063743	clk: clk-conf: support assigned-clock-rates-u64 ... i.MX95 System Management Control Firmware(SCMI) manages the clock function, it exposes PLL VCO which could support up to 5GHz rate that exceeds UINT32_MAX. So add assigned-clock-rates-u64 support to set rate that exceeds UINT32_MAX. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20240804-clk-u64-v4-2-8e55569f39a4@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-08-16 15:21:19 -07:00
Dmitry Baryshkov	362be5cbae	clk: qcom: dispcc-sm8250: use special function for Lucid 5LPE PLL ... According to msm-5.10 the lucid 5lpe PLLs have require slightly different configuration that trion / lucid PLLs, it doesn't set PLL_UPDATE_BYPASS bit. Add corresponding function and use it for the display clock controller on Qualcomm SM8350 platform. Fixes: 205737fe33 ("clk: qcom: add support for SM8350 DISPCC") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-2-1149dd8399fe@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2024-08-15 17:10:13 -05:00
Dmitry Baryshkov	0e93c6320e	clk: qcom: dispcc-sm8250: use CLK_SET_RATE_PARENT for branch clocks ... Add CLK_SET_RATE_PARENT for several branch clocks. Such clocks don't have a way to change the rate, so set the parent rate instead. Fixes: 80a18f4a85 ("clk: qcom: Add display clock controller driver for SM8150 and SM8250") Cc: stable@vger.kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-1-1149dd8399fe@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2024-08-15 17:10:13 -05:00
Varadarajan Narayanan	92d04de255	clk: qcom: ipq5332: Use icc-clk for enabling NoC related clocks ... Use the icc-clk framework to enable few clocks to be able to create paths and use the peripherals connected on those NoCs. Remove CLK_IGNORE_UNUSED from gpll4_main as all consumers have been identified. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20240730054817.1915652-5-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2024-08-15 17:06:11 -05:00
Varadarajan Narayanan	0e1ac23dfa	clk: qcom: ipq5332: Register gcc_qdss_tsctr_clk_src ... gcc_qdss_tsctr_clk_src (enabled in the boot loaders and dependent on gpll4_main) was not registered as one of the ipq5332 clocks. Hence clk_disable_unused() disabled 'gpll4_main' assuming there were no consumers for 'gpll4_main' resulting in system freeze or reboots. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: 3d89d52970 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20240730054817.1915652-4-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2024-08-15 17:06:11 -05:00
AngeloGioacchino Del Regno	7554d532e0	clk: qcom: gcc-msm8998: Add Q6 BIMC and LPASS core, ADSP SMMU clocks ... Add the Q6 BIMC, LPASS core/adsp SMMU clocks to support audio related functionality on MSM8998 and APQ variants. As a final step to entirely enable the required clock tree for the lpass iommu and audio dsp, add the lpass core/adsp GDSCs. As a side note, it was found out that disabling the lpass core GDSC at any time would cause a system lockup (and reboot): disabling this GDSC will leave the lpass iommu completely unclocked, losing its state entirely - including the secure contexts that have been previously set-up from the bootloader/TrustZone. Losing this IOMMU configuration will trigger a hypervisor fault, which will reboot the system; the only workaround for this issue is to declare the lpass core gdsc as always-on. It should also not be forgotten that this is all about firmware and there may be a version of it that doesn't enable this GDSC at all before booting Linux, which is the reason why this specific declaration wasn't simply omitted. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr> Link: https://lore.kernel.org/r/20240814-lpass-v1-2-a5bb8f9dfa8b@freebox.fr Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2024-08-15 16:11:42 -05:00
Satya Priya Kakitapalli	82ceaf6bcd	clk: qcom: Fix SM_CAMCC_8150 dependencies ... SM_CAMCC_8150 depends on SM_GCC_8150, which inturn depends on ARM64. Hence add the dependency to avoid below kernel-bot warning. WARNING: unmet direct dependencies detected for SM_GCC_8150 Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] && (ARM64 || COMPILE_TEST [=n]) Selected by [y]: - SM_CAMCC_8150 [=y] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] Fixes: ea73b7acef ("clk: qcom: Add camera clock controller driver for SM8150") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202408020234.jg9wrvhd-lkp@intel.com/ Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240813085846.941855-1-quic_skakitap@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2024-08-15 14:14:55 -05:00
Satya Priya Kakitapalli	bab0c7a0bc	clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src ... The branch clocks of gcc_cpuss_ahb_clk_src are marked critical and hence these clocks vote on XO blocking the suspend. De-register these clocks and its source as there is no rate setting happening on them. Fixes: 4433594bbe ("clk: qcom: gcc: Add global clock controller driver for SC8180x") Cc: stable@vger.kernel.org Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-5-8b3eaa5fb856@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2024-08-15 14:14:55 -05:00
Satya Priya Kakitapalli	b8acaf2de8	clk: qcom: gcc-sc8180x: Fix the sdcc2 and sdcc4 clocks freq table ... Update the frequency tables of gcc_sdcc2_apps_clk and gcc_sdcc4_apps_clk as per the latest frequency plan. Fixes: 4433594bbe ("clk: qcom: gcc: Add global clock controller driver for SC8180x") Cc: stable@vger.kernel.org Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-4-8b3eaa5fb856@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2024-08-15 14:14:55 -05:00