mirror of
https://github.com/torvalds/linux.git
synced 2024-11-22 04:02:20 +00:00
Merge branches 'clk-devm', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into clk-next
* clk-devm: clk: provide devm_clk_get_optional_enabled_with_rate() clk: fixed-rate: add devm_clk_hw_register_fixed_rate_parent_data() * clk-samsung: clk: samsung: add top clock support for ExynosAuto v920 SoC clk: samsung: clk-pll: Add support for pll_531x dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings clk: samsung: exynos7885: Add USB related clocks to CMU_FSYS clk: samsung: clk-pll: Add support for pll_1418x clk: samsung: exynosautov9: add dpum clock support dt-bindings: clock: exynosautov9: add dpum clock clk: samsung: exynos7885: Add missing MUX clocks from PLLs in CMU_TOP clk: samsung: exynos7885: Update CLKS_NR_FSYS after bindings fix dt-bindings: clock: exynos7885: Add indices for USB clocks dt-bindings: clock: exynos7885: Add CMU_TOP PLL MUX indices dt-bindings: clock: exynos7885: Fix duplicated binding clk: samsung: exynos850: Add TMU clock dt-bindings: clock: exynos850: Add TMU clock * clk-rockchip: dt-bindings: clock, reset: fix top-comment indentation rk3576 headers clk: rockchip: remove unused mclk_pdm0_p/pdm0_p definitions clk: rockchip: fix error for unknown clocks clk: rockchip: rk3588: drop unused code clk: rockchip: Add clock controller for the RK3576 clk: rockchip: Add new pll type pll_rk3588_ddr dt-bindings: clock, reset: Add support for rk3576 dt-bindings: clock: rockchip,rk3588-cru: drop unneeded assigned-clocks clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_p dt-bindings: clock: rockchip: remove CLK_NR_CLKS and CLKPMU_NR_CLKS clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage clk: rockchip: rk3368: Drop CLK_NR_CLKS usage clk: rockchip: rk3328: Drop CLK_NR_CLKS usage clk: rockchip: rk3308: Drop CLK_NR_CLKS usage clk: rockchip: rk3288: Drop CLK_NR_CLKS usage clk: rockchip: rk3228: Drop CLK_NR_CLKS usage clk: rockchip: rk3036: Drop CLK_NR_CLKS usage clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228 * clk-qcom: (47 commits) clk: qcom: videocc-sm8550: Use HW_CTRL_TRIGGER flag for video GDSC's clk: qcom: dispcc-sm8250: use special function for Lucid 5LPE PLL clk: qcom: dispcc-sm8250: use CLK_SET_RATE_PARENT for branch clocks clk: qcom: ipq5332: Use icc-clk for enabling NoC related clocks clk: qcom: ipq5332: Register gcc_qdss_tsctr_clk_src dt-bindings: usb: qcom,dwc3: Update ipq5332 clock details dt-bindings: interconnect: Add Qualcomm IPQ5332 support clk: qcom: gcc-msm8998: Add Q6 BIMC and LPASS core, ADSP SMMU clocks dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions clk: qcom: Fix SM_CAMCC_8150 dependencies clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src clk: qcom: gcc-sc8180x: Fix the sdcc2 and sdcc4 clocks freq table clk: qcom: gcc-sc8180x: Add GPLL9 support dt-bindings: clock: qcom: Add GPLL9 support on gcc-sc8180x clk: qcom: gcc-sc8180x: Register QUPv3 RCGs for DFS on sc8180x clk: qcom: clk-rpmh: Fix overflow in BCM vote dt-bindings: clock: qcom: Drop required-opps in required on SM8650 camcc dt-bindings: clock: qcom: Drop required-opps in required on sm8650 videocc dt-bindings: clock: qcom,qcs404-turingcc: convert to dtschema dt-bindings: clock: Add x1e80100 LPASSCC reset controller ...
This commit is contained in:
Stephen Boyd
commit
1b189f71e1
@ -21,6 +21,7 @@ properties:
|
||||
- qcom,ipq6018-a53pll
|
||||
- qcom,ipq8074-a53pll
|
||||
- qcom,ipq9574-a73pll
|
||||
- qcom,msm8226-a7pll
|
||||
- qcom,msm8916-a53pll
|
||||
- qcom,msm8939-a53pll
|
||||
|
||||
@ -40,6 +41,9 @@ properties:
|
||||
|
||||
operating-points-v2: true
|
||||
|
||||
opp-table:
|
||||
type: object
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@ -31,6 +31,8 @@ properties:
|
||||
- description: USB PCIE wrapper pipe clock source
|
||||
|
||||
'#power-domain-cells': false
|
||||
'#interconnect-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,qcs404-turingcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
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||||
|
||||
title: Qualcomm Turing Clock & Reset Controller on QCS404
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||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
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||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,qcs404-turingcc
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||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
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||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
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||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
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||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
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clock-controller@800000 {
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||||
compatible = "qcom,qcs404-turingcc";
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||||
reg = <0x00800000 0x30000>;
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||||
clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
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||||
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||||
#clock-cells = <1>;
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||||
#reset-cells = <1>;
|
||||
};
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||||
@ -18,9 +18,16 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc8280xp-lpassaudiocc
|
||||
- qcom,sc8280xp-lpasscc
|
||||
oneOf:
|
||||
- enum:
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||||
- qcom,sc8280xp-lpassaudiocc
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||||
- qcom,sc8280xp-lpasscc
|
||||
- items:
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||||
- const: qcom,x1e80100-lpassaudiocc
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||||
- const: qcom,sc8280xp-lpassaudiocc
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||||
- items:
|
||||
- const: qcom,x1e80100-lpasscc
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||||
- const: qcom,sc8280xp-lpasscc
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||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -0,0 +1,63 @@
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||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm4450-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller on SM4450
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||||
|
||||
maintainers:
|
||||
- Ajit Pandey <quic_ajipan@quicinc.com>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module provides the clocks, resets and power
|
||||
domains on SM4450
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h
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||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm4450-camcc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Camera AHB clock source from GCC
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
|
||||
clock-controller@ade0000 {
|
||||
compatible = "qcom,sm4450-camcc";
|
||||
reg = <0x0ade0000 0x20000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_CAMERA_AHB_CLK>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,71 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller on SM4450
|
||||
|
||||
maintainers:
|
||||
- Ajit Pandey <quic_ajipan@quicinc.com>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SM4450
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm4450-dispcc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Display AHB clock source from GCC
|
||||
- description: sleep clock source
|
||||
- description: Byte clock from DSI PHY0
|
||||
- description: Pixel clock from DSI PHY0
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sm4450-dispcc";
|
||||
reg = <0x0af00000 0x20000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&gcc GCC_DISP_AHB_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&dsi0_phy_pll_out_byteclk>,
|
||||
<&dsi0_phy_pll_out_dsiclk>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,77 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm8150-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller on SM8150
|
||||
|
||||
maintainers:
|
||||
- Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module provides the clocks, resets and
|
||||
power domains on SM8150.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm8150-camcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8150-camcc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Camera AHB clock from GCC
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description:
|
||||
A phandle and PM domain specifier for the MMCX power domain.
|
||||
|
||||
required-opps:
|
||||
maxItems: 1
|
||||
description:
|
||||
A phandle to an OPP node describing required MMCX performance point.
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- power-domains
|
||||
- required-opps
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
clock-controller@ad00000 {
|
||||
compatible = "qcom,sm8150-camcc";
|
||||
reg = <0x0ad00000 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_CAMERA_AHB_CLK>;
|
||||
power-domains = <&rpmhpd SM8150_MMCX>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -21,9 +21,6 @@ description: |
|
||||
include/dt-bindings/clock/qcom,sm8650-camcc.h
|
||||
include/dt-bindings/clock/qcom,x1e80100-camcc.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
@ -57,7 +54,21 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
- required-opps
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sc8280xp-camcc
|
||||
- qcom,sm8450-camcc
|
||||
- qcom,sm8550-camcc
|
||||
- qcom,x1e80100-camcc
|
||||
then:
|
||||
required:
|
||||
- required-opps
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
||||
@ -14,6 +14,7 @@ description: |
|
||||
domains on Qualcomm SoCs.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,sm4450-gpucc.h
|
||||
include/dt-bindings/clock/qcom,sm8450-gpucc.h
|
||||
include/dt-bindings/clock/qcom,sm8550-gpucc.h
|
||||
include/dt-bindings/reset/qcom,sm8450-gpucc.h
|
||||
@ -23,6 +24,7 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm4450-gpucc
|
||||
- qcom,sm8450-gpucc
|
||||
- qcom,sm8550-gpucc
|
||||
- qcom,sm8650-gpucc
|
||||
|
||||
@ -44,11 +44,20 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
- required-opps
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sm8450-videocc
|
||||
- qcom,sm8550-videocc
|
||||
then:
|
||||
required:
|
||||
- required-opps
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
||||
@ -1,19 +0,0 @@
|
||||
Qualcomm Turing Clock & Reset Controller Binding
|
||||
------------------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible: shall contain "qcom,qcs404-turingcc".
|
||||
- reg: shall contain base register location and length.
|
||||
- clocks: ahb clock for the TuringCC
|
||||
- #clock-cells: from common clock binding, shall contain 1.
|
||||
- #reset-cells: from common reset binding, shall contain 1.
|
||||
|
||||
Example:
|
||||
turingcc: clock-controller@800000 {
|
||||
compatible = "qcom,qcs404-turingcc";
|
||||
reg = <0x00800000 0x30000>;
|
||||
clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -0,0 +1,56 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3576-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip rk3576 Family Clock and Reset Control Module
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
- Detlev Casanova <detlev.casanova@collabora.com>
|
||||
|
||||
description:
|
||||
The RK3576 clock controller generates the clock and also implements a reset
|
||||
controller for SoC peripherals. For example it provides SCLK_UART2 and
|
||||
PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART
|
||||
module.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: rockchip,rk3576-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xin24m
|
||||
- const: xin32k
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@27200000 {
|
||||
compatible = "rockchip,rk3576-cru";
|
||||
reg = <0xfd7c0000 0x5c000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -42,10 +42,6 @@ properties:
|
||||
- const: xin24m
|
||||
- const: xin32k
|
||||
|
||||
assigned-clocks: true
|
||||
|
||||
assigned-clock-rates: true
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: >
|
||||
|
||||
@ -35,6 +35,7 @@ properties:
|
||||
- samsung,exynosautov9-cmu-top
|
||||
- samsung,exynosautov9-cmu-busmc
|
||||
- samsung,exynosautov9-cmu-core
|
||||
- samsung,exynosautov9-cmu-dpum
|
||||
- samsung,exynosautov9-cmu-fsys0
|
||||
- samsung,exynosautov9-cmu-fsys1
|
||||
- samsung,exynosautov9-cmu-fsys2
|
||||
@ -109,6 +110,24 @@ allOf:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_core_bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-dpum
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: DPU Main bus clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -0,0 +1,162 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynosautov920-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung ExynosAuto v920 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Sunyeal Hong <sunyeal.hong@samsung.com>
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
|
||||
description: |
|
||||
ExynosAuto v920 clock controller is comprised of several CMU units, generating
|
||||
clocks for different domains. Those CMU units are modeled as separate device
|
||||
tree nodes, and might depend on each other. Root clocks in that clock tree are
|
||||
two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
|
||||
The external OSCCLK must be defined as fixed-rate clock in dts.
|
||||
|
||||
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
|
||||
dividers; all other clocks of function blocks (other CMUs) are usually
|
||||
derived from CMU_TOP.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All clocks available for usage
|
||||
in clock consumer nodes are defined as preprocessor macros in
|
||||
'include/dt-bindings/clock/samsung,exynosautov920.h' header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynosautov920-cmu-top
|
||||
- samsung,exynosautov920-cmu-peric0
|
||||
- samsung,exynosautov920-cmu-peric1
|
||||
- samsung,exynosautov920-cmu-misc
|
||||
- samsung,exynosautov920-cmu-hsi0
|
||||
- samsung,exynosautov920-cmu-hsi1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov920-cmu-top
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (38.4 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynosautov920-cmu-peric0
|
||||
- samsung,exynosautov920-cmu-peric1
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (38.4 MHz)
|
||||
- description: CMU_PERICn NOC clock (from CMU_TOP)
|
||||
- description: CMU_PERICn IP clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
- const: ip
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynosautov920-cmu-misc
|
||||
- samsung,exynosautov920-cmu-hsi0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (38.4 MHz)
|
||||
- description: CMU_MISC/CMU_HSI0 NOC clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov920-cmu-hsi1
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (38.4 MHz)
|
||||
- description: CMU_HSI1 NOC clock (from CMU_TOP)
|
||||
- description: CMU_HSI1 USBDRD clock (from CMU_TOP)
|
||||
- description: CMU_HSI1 MMC_CARD clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
- const: usbdrd
|
||||
- const: mmc_card
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock controller node for CMU_PERIC0
|
||||
- |
|
||||
#include <dt-bindings/clock/samsung,exynosautov920.h>
|
||||
|
||||
cmu_peric0: clock-controller@10800000 {
|
||||
compatible = "samsung,exynosautov920-cmu-peric0";
|
||||
reg = <0x10800000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&xtcxo>,
|
||||
<&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
|
||||
<&cmu_top DOUT_CLKCMU_PERIC0_IP>;
|
||||
clock-names = "oscclk",
|
||||
"noc",
|
||||
"ip";
|
||||
};
|
||||
|
||||
...
|
||||
@ -164,6 +164,7 @@ allOf:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,ipq4019-dwc3
|
||||
- qcom,ipq5332-dwc3
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
@ -267,7 +268,6 @@ allOf:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,ipq5018-dwc3
|
||||
- qcom,ipq5332-dwc3
|
||||
- qcom,msm8994-dwc3
|
||||
- qcom,qcs404-dwc3
|
||||
then:
|
||||
|
||||
@ -99,6 +99,34 @@ struct clk *devm_clk_get_optional_enabled(struct device *dev, const char *id)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(devm_clk_get_optional_enabled);
|
||||
|
||||
struct clk *devm_clk_get_optional_enabled_with_rate(struct device *dev,
|
||||
const char *id,
|
||||
unsigned long rate)
|
||||
{
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
clk = __devm_clk_get(dev, id, clk_get_optional, NULL,
|
||||
clk_disable_unprepare);
|
||||
if (IS_ERR(clk))
|
||||
return ERR_CAST(clk);
|
||||
|
||||
ret = clk_set_rate(clk, rate);
|
||||
if (ret)
|
||||
goto out_put_clk;
|
||||
|
||||
ret = clk_prepare_enable(clk);
|
||||
if (ret)
|
||||
goto out_put_clk;
|
||||
|
||||
return clk;
|
||||
|
||||
out_put_clk:
|
||||
devm_clk_put(dev, clk);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(devm_clk_get_optional_enabled_with_rate);
|
||||
|
||||
struct clk_bulk_devres {
|
||||
struct clk_bulk_data *clks;
|
||||
int num_clks;
|
||||
|
||||
@ -810,6 +810,14 @@ config SDX_GCC_75
|
||||
Say Y if you want to use peripheral devices such as UART,
|
||||
SPI, I2C, USB, SD/eMMC, PCIe etc.
|
||||
|
||||
config SM_CAMCC_4450
|
||||
tristate "SM4450 Camera Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SM_GCC_4450
|
||||
help
|
||||
Support for the camera clock controller on SM4450 devices.
|
||||
Say Y if you want to support camera devices and camera functionality.
|
||||
|
||||
config SM_CAMCC_6350
|
||||
tristate "SM6350 Camera Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
@ -826,6 +834,16 @@ config SM_CAMCC_7150
|
||||
Support for the camera clock controller on SM7150 devices.
|
||||
Say Y if you want to support camera devices and camera functionality.
|
||||
|
||||
config SM_CAMCC_8150
|
||||
tristate "SM8150 Camera Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SM_GCC_8150
|
||||
help
|
||||
Support for the camera clock controller on Qualcomm Technologies, Inc
|
||||
SM8150 devices.
|
||||
Say Y if you want to support camera devices and functionality such as
|
||||
capturing pictures.
|
||||
|
||||
config SM_CAMCC_8250
|
||||
tristate "SM8250 Camera Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
@ -858,6 +876,16 @@ config SM_CAMCC_8650
|
||||
Support for the camera clock controller on SM8650 devices.
|
||||
Say Y if you want to support camera devices and camera functionality.
|
||||
|
||||
config SM_DISPCC_4450
|
||||
tristate "SM4450 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
depends on SM_GCC_4450
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
SM4450 devices.
|
||||
Say Y if you want to support display devices and functionality such as
|
||||
splash screen
|
||||
|
||||
config SM_DISPCC_6115
|
||||
tristate "SM6115 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
@ -931,20 +959,10 @@ config SM_DISPCC_8450
|
||||
config SM_DISPCC_8550
|
||||
tristate "SM8550 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
depends on SM_GCC_8550
|
||||
depends on SM_GCC_8550 || SM_GCC_8650
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
SM8550 devices.
|
||||
Say Y if you want to support display devices and functionality such as
|
||||
splash screen.
|
||||
|
||||
config SM_DISPCC_8650
|
||||
tristate "SM8650 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SM_GCC_8650
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
SM8650 devices.
|
||||
SM8550 or SM8650 devices.
|
||||
Say Y if you want to support display devices and functionality such as
|
||||
splash screen.
|
||||
|
||||
@ -1054,6 +1072,15 @@ config SM_GCC_8650
|
||||
Say Y if you want to use peripheral devices such as UART,
|
||||
SPI, I2C, USB, SD/UFS, PCIe etc.
|
||||
|
||||
config SM_GPUCC_4450
|
||||
tristate "SM4450 Graphics Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SM_GCC_4450
|
||||
help
|
||||
Support for the graphics clock controller on SM4450 devices.
|
||||
Say Y if you want to support graphics controller devices and
|
||||
functionality such as 3D graphics.
|
||||
|
||||
config SM_GPUCC_6115
|
||||
tristate "SM6115 Graphics Clock Controller"
|
||||
select SM_GCC_6115
|
||||
|
||||
@ -107,12 +107,15 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
|
||||
obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
|
||||
obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o
|
||||
obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o
|
||||
obj-$(CONFIG_SM_CAMCC_4450) += camcc-sm4450.o
|
||||
obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
|
||||
obj-$(CONFIG_SM_CAMCC_7150) += camcc-sm7150.o
|
||||
obj-$(CONFIG_SM_CAMCC_8150) += camcc-sm8150.o
|
||||
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
|
||||
obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
|
||||
obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o
|
||||
obj-$(CONFIG_SM_CAMCC_8650) += camcc-sm8650.o
|
||||
obj-$(CONFIG_SM_DISPCC_4450) += dispcc-sm4450.o
|
||||
obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
|
||||
obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
|
||||
obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
|
||||
@ -121,7 +124,6 @@ obj-$(CONFIG_SM_DISPCC_7150) += dispcc-sm7150.o
|
||||
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
|
||||
obj-$(CONFIG_SM_DISPCC_8450) += dispcc-sm8450.o
|
||||
obj-$(CONFIG_SM_DISPCC_8550) += dispcc-sm8550.o
|
||||
obj-$(CONFIG_SM_DISPCC_8650) += dispcc-sm8650.o
|
||||
obj-$(CONFIG_SM_GCC_4450) += gcc-sm4450.o
|
||||
obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o
|
||||
obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o
|
||||
@ -134,6 +136,7 @@ obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
|
||||
obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
|
||||
obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o
|
||||
obj-$(CONFIG_SM_GCC_8650) += gcc-sm8650.o
|
||||
obj-$(CONFIG_SM_GPUCC_4450) += gpucc-sm4450.o
|
||||
obj-$(CONFIG_SM_GPUCC_6115) += gpucc-sm6115.o
|
||||
obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o
|
||||
obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o
|
||||
|
||||
@ -151,6 +151,7 @@ static int qcom_a53pll_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
static const struct of_device_id qcom_a53pll_match_table[] = {
|
||||
{ .compatible = "qcom,msm8226-a7pll" },
|
||||
{ .compatible = "qcom,msm8916-a53pll" },
|
||||
{ .compatible = "qcom,msm8939-a53pll" },
|
||||
{ }
|
||||
|
||||
1688
drivers/clk/qcom/camcc-sm4450.c
Normal file
1688
drivers/clk/qcom/camcc-sm4450.c
Normal file
File diff suppressed because it is too large
Load Diff
2159
drivers/clk/qcom/camcc-sm8150.c
Normal file
2159
drivers/clk/qcom/camcc-sm8150.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,7 +1,7 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
* Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
@ -1712,7 +1712,7 @@ static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
|
||||
regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l);
|
||||
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
|
||||
|
||||
/* Latch the PLL input */
|
||||
@ -1831,6 +1831,58 @@ const struct clk_ops clk_alpha_pll_agera_ops = {
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
|
||||
|
||||
/**
|
||||
* clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll
|
||||
*
|
||||
* @pll: clk alpha pll
|
||||
* @regmap: register map
|
||||
* @config: configuration to apply for pll
|
||||
*/
|
||||
void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config)
|
||||
{
|
||||
/*
|
||||
* If the bootloader left the PLL enabled it's likely that there are
|
||||
* RCGs that will lock up if we disable the PLL below.
|
||||
*/
|
||||
if (trion_pll_is_enabled(pll, regmap)) {
|
||||
pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n");
|
||||
return;
|
||||
}
|
||||
|
||||
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
|
||||
regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
|
||||
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
|
||||
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
|
||||
config->config_ctl_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
|
||||
config->config_ctl_hi_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
|
||||
config->config_ctl_hi1_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
|
||||
config->user_ctl_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
|
||||
config->user_ctl_hi_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
|
||||
config->user_ctl_hi1_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
|
||||
config->test_ctl_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
|
||||
config->test_ctl_hi_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
|
||||
config->test_ctl_hi1_val);
|
||||
|
||||
/* Disable PLL output */
|
||||
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
|
||||
|
||||
/* Set operation mode to OFF */
|
||||
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
|
||||
|
||||
/* Place the PLL in STANDBY mode */
|
||||
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_lucid_5lpe_pll_configure);
|
||||
|
||||
static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
@ -2657,3 +2709,33 @@ const struct clk_ops clk_alpha_pll_stromer_plus_ops = {
|
||||
.set_rate = clk_alpha_pll_stromer_plus_set_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops);
|
||||
|
||||
void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config)
|
||||
{
|
||||
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
|
||||
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
|
||||
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
|
||||
|
||||
/* Set operation mode to STANDBY */
|
||||
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_regera_pll_configure);
|
||||
|
||||
const struct clk_ops clk_alpha_pll_regera_ops = {
|
||||
.enable = clk_zonda_pll_enable,
|
||||
.disable = clk_zonda_pll_disable,
|
||||
.is_enabled = clk_alpha_pll_is_enabled,
|
||||
.recalc_rate = clk_trion_pll_recalc_rate,
|
||||
.round_rate = clk_alpha_pll_round_rate,
|
||||
.set_rate = clk_zonda_pll_set_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops);
|
||||
|
||||
@ -23,6 +23,7 @@ enum {
|
||||
CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
|
||||
CLK_ALPHA_PLL_TYPE_AGERA,
|
||||
CLK_ALPHA_PLL_TYPE_ZONDA,
|
||||
CLK_ALPHA_PLL_TYPE_REGERA = CLK_ALPHA_PLL_TYPE_ZONDA,
|
||||
CLK_ALPHA_PLL_TYPE_ZONDA_OLE,
|
||||
CLK_ALPHA_PLL_TYPE_LUCID_EVO,
|
||||
CLK_ALPHA_PLL_TYPE_LUCID_OLE,
|
||||
@ -193,6 +194,8 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
|
||||
extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
|
||||
#define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
|
||||
|
||||
extern const struct clk_ops clk_alpha_pll_regera_ops;
|
||||
|
||||
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
@ -208,6 +211,8 @@ void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
|
||||
void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
@ -216,5 +221,7 @@ void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regm
|
||||
const struct alpha_pll_config *config);
|
||||
void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
|
||||
#endif
|
||||
|
||||
@ -263,6 +263,8 @@ static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable)
|
||||
cmd_state = 0;
|
||||
}
|
||||
|
||||
cmd_state = min(cmd_state, BCM_TCS_CMD_VOTE_MASK);
|
||||
|
||||
if (c->last_sent_aggr_state != cmd_state) {
|
||||
cmd.addr = c->res_addr;
|
||||
cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state);
|
||||
|
||||
770
drivers/clk/qcom/dispcc-sm4450.c
Normal file
770
drivers/clk/qcom/dispcc-sm4450.c
Normal file
@ -0,0 +1,770 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,sm4450-dispcc.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-pll.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "common.h"
|
||||
#include "gdsc.h"
|
||||
#include "reset.h"
|
||||
|
||||
enum {
|
||||
DT_BI_TCXO,
|
||||
DT_BI_TCXO_AO,
|
||||
DT_AHB_CLK,
|
||||
DT_SLEEP_CLK,
|
||||
|
||||
DT_DSI0_PHY_PLL_OUT_BYTECLK,
|
||||
DT_DSI0_PHY_PLL_OUT_DSICLK,
|
||||
};
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_DISP_CC_PLL0_OUT_MAIN,
|
||||
P_DISP_CC_PLL1_OUT_EVEN,
|
||||
P_DISP_CC_PLL1_OUT_MAIN,
|
||||
P_DSI0_PHY_PLL_OUT_BYTECLK,
|
||||
P_DSI0_PHY_PLL_OUT_DSICLK,
|
||||
P_SLEEP_CLK,
|
||||
};
|
||||
|
||||
static const struct pll_vco lucid_evo_vco[] = {
|
||||
{ 249600000, 2020000000, 0 },
|
||||
};
|
||||
|
||||
/* 600.0 MHz Configuration */
|
||||
static const struct alpha_pll_config disp_cc_pll0_config = {
|
||||
.l = 0x1f,
|
||||
.alpha = 0x4000,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x32aa299c,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000805,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll disp_cc_pll0 = {
|
||||
.offset = 0x0,
|
||||
.vco_table = lucid_evo_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_evo_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_pll0",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.index = DT_BI_TCXO,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_evo_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll disp_cc_pll1 = {
|
||||
.offset = 0x1000,
|
||||
.vco_table = lucid_evo_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_evo_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_pll1",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.index = DT_BI_TCXO,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_evo_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
|
||||
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_0[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
|
||||
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
|
||||
{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
|
||||
{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_1[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .hw = &disp_cc_pll0.clkr.hw },
|
||||
{ .hw = &disp_cc_pll1.clkr.hw },
|
||||
{ .hw = &disp_cc_pll1.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_2[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_2[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_2_ao[] = {
|
||||
{ .index = DT_BI_TCXO_AO },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_3[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
|
||||
{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_3[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .hw = &disp_cc_pll1.clkr.hw },
|
||||
{ .hw = &disp_cc_pll1.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_4[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_4[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_5[] = {
|
||||
{ P_SLEEP_CLK, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_5[] = {
|
||||
{ .index = DT_SLEEP_CLK },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
|
||||
F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
|
||||
.cmd_rcgr = 0x82a4,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_3,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_ahb_clk_src",
|
||||
.parent_data = disp_cc_parent_data_3,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
|
||||
.cmd_rcgr = 0x80f8,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_byte0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_byte2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
|
||||
.cmd_rcgr = 0x8114,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_4,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_esc0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_4,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
|
||||
F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(380000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(506000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(608000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
|
||||
.cmd_rcgr = 0x80b0,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_mdp_clk_src",
|
||||
.parent_data = disp_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
|
||||
.cmd_rcgr = 0x8098,
|
||||
.mnd_width = 8,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_pclk0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_pixel_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
|
||||
F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
|
||||
F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
|
||||
.cmd_rcgr = 0x80c8,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_rot_clk_src",
|
||||
.parent_data = disp_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
|
||||
.cmd_rcgr = 0x80e0,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_2,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_vsync_clk_src",
|
||||
.parent_data = disp_cc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
|
||||
F(32000, P_SLEEP_CLK, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_sleep_clk_src = {
|
||||
.cmd_rcgr = 0xe058,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_5,
|
||||
.freq_tbl = ftbl_disp_cc_sleep_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_sleep_clk_src",
|
||||
.parent_data = disp_cc_parent_data_5,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_xo_clk_src = {
|
||||
.cmd_rcgr = 0xe03c,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_2,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_xo_clk_src",
|
||||
.parent_data = disp_cc_parent_data_2_ao,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2_ao),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
|
||||
.reg = 0x8110,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_byte0_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_byte0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_ahb1_clk = {
|
||||
.halt_reg = 0xa020,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0xa020,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_ahb1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_ahb_clk = {
|
||||
.halt_reg = 0x8094,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8094,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_byte0_clk = {
|
||||
.halt_reg = 0x8024,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8024,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_byte0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_byte0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
|
||||
.halt_reg = 0x8028,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8028,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_byte0_intf_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_esc0_clk = {
|
||||
.halt_reg = 0x802c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x802c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_esc0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_esc0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_mdp1_clk = {
|
||||
.halt_reg = 0xa004,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0xa004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_mdp1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_mdp_clk = {
|
||||
.halt_reg = 0x8008,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8008,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_mdp_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {
|
||||
.halt_reg = 0xa014,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0xa014,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_mdp_lut1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
|
||||
.halt_reg = 0x8018,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8018,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_mdp_lut_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
|
||||
.halt_reg = 0xc004,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0xc004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_pclk0_clk = {
|
||||
.halt_reg = 0x8004,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_pclk0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_rot1_clk = {
|
||||
.halt_reg = 0xa00c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0xa00c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_rot1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_rot_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_rot_clk = {
|
||||
.halt_reg = 0x8010,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8010,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_rot_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_rot_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
|
||||
.halt_reg = 0xc00c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0xc00c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_rscc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
|
||||
.halt_reg = 0xc008,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0xc008,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_rscc_vsync_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_vsync1_clk = {
|
||||
.halt_reg = 0xa01c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0xa01c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_vsync1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_vsync_clk = {
|
||||
.halt_reg = 0x8020,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8020,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_vsync_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc disp_cc_mdss_core_gdsc = {
|
||||
.gdscr = 0x9000,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0xf,
|
||||
.pd = {
|
||||
.name = "disp_cc_mdss_core_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = HW_CTRL | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc disp_cc_mdss_core_int2_gdsc = {
|
||||
.gdscr = 0xb000,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0xf,
|
||||
.pd = {
|
||||
.name = "disp_cc_mdss_core_int2_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = HW_CTRL | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct clk_regmap *disp_cc_sm4450_clocks[] = {
|
||||
[DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr,
|
||||
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
|
||||
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
|
||||
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
|
||||
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
|
||||
[DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr,
|
||||
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
|
||||
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
|
||||
[DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr,
|
||||
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
|
||||
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
|
||||
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
|
||||
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
|
||||
[DISP_CC_MDSS_ROT1_CLK] = &disp_cc_mdss_rot1_clk.clkr,
|
||||
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
|
||||
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
|
||||
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
|
||||
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
|
||||
[DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr,
|
||||
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
|
||||
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
|
||||
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
|
||||
[DISP_CC_PLL1] = &disp_cc_pll1.clkr,
|
||||
[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
|
||||
[DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,
|
||||
};
|
||||
|
||||
static struct gdsc *disp_cc_sm4450_gdscs[] = {
|
||||
[DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc,
|
||||
[DISP_CC_MDSS_CORE_INT2_GDSC] = &disp_cc_mdss_core_int2_gdsc,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map disp_cc_sm4450_resets[] = {
|
||||
[DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
|
||||
[DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
|
||||
[DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
|
||||
};
|
||||
|
||||
static const struct regmap_config disp_cc_sm4450_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x11008,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static struct qcom_cc_desc disp_cc_sm4450_desc = {
|
||||
.config = &disp_cc_sm4450_regmap_config,
|
||||
.clks = disp_cc_sm4450_clocks,
|
||||
.num_clks = ARRAY_SIZE(disp_cc_sm4450_clocks),
|
||||
.resets = disp_cc_sm4450_resets,
|
||||
.num_resets = ARRAY_SIZE(disp_cc_sm4450_resets),
|
||||
.gdscs = disp_cc_sm4450_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(disp_cc_sm4450_gdscs),
|
||||
};
|
||||
|
||||
static const struct of_device_id disp_cc_sm4450_match_table[] = {
|
||||
{ .compatible = "qcom,sm4450-dispcc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, disp_cc_sm4450_match_table);
|
||||
|
||||
static int disp_cc_sm4450_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &disp_cc_sm4450_desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
||||
clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll0_config);
|
||||
|
||||
/* Keep some clocks always enabled */
|
||||
qcom_branch_set_clk_en(regmap, 0xe070); /* DISP_CC_SLEEP_CLK */
|
||||
qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */
|
||||
|
||||
return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm4450_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver disp_cc_sm4450_driver = {
|
||||
.probe = disp_cc_sm4450_probe,
|
||||
.driver = {
|
||||
.name = "dispcc-sm4450",
|
||||
.of_match_table = disp_cc_sm4450_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(disp_cc_sm4450_driver);
|
||||
|
||||
MODULE_DESCRIPTION("QTI DISPCC SM4450 Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
@ -849,6 +849,7 @@ static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = {
|
||||
&disp_cc_mdss_dp_link1_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
@ -884,6 +885,7 @@ static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
|
||||
&disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
@ -1009,6 +1011,7 @@ static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
|
||||
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
@ -1357,8 +1360,13 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
|
||||
disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = NULL;
|
||||
}
|
||||
|
||||
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
||||
clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
|
||||
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
|
||||
clk_lucid_5lpe_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
||||
clk_lucid_5lpe_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
|
||||
} else {
|
||||
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
||||
clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
|
||||
}
|
||||
|
||||
/* Enable clock gating for MDP clocks */
|
||||
regmap_update_bits(regmap, 0x8000, 0x10, 0x10);
|
||||
|
||||
@ -71,7 +71,7 @@ enum {
|
||||
P_SLEEP_CLK,
|
||||
};
|
||||
|
||||
static const struct pll_vco lucid_ole_vco[] = {
|
||||
static struct pll_vco lucid_ole_vco[] = {
|
||||
{ 249600000, 2000000000, 0 },
|
||||
};
|
||||
|
||||
@ -95,7 +95,7 @@ static struct clk_alpha_pll disp_cc_pll0 = {
|
||||
.num_vco = ARRAY_SIZE(lucid_ole_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_pll0",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.index = DT_BI_TCXO,
|
||||
@ -126,7 +126,7 @@ static struct clk_alpha_pll disp_cc_pll1 = {
|
||||
.num_vco = ARRAY_SIZE(lucid_ole_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_pll1",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.index = DT_BI_TCXO,
|
||||
@ -196,7 +196,7 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = {
|
||||
static const struct parent_map disp_cc_parent_map_4[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DP0_PHY_PLL_LINK_CLK, 1 },
|
||||
{ P_DP1_PHY_PLL_VCO_DIV_CLK, 2 },
|
||||
{ P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
|
||||
{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
|
||||
{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
|
||||
{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
|
||||
@ -213,7 +213,7 @@ static const struct clk_parent_data disp_cc_parent_data_4[] = {
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_5[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 4 },
|
||||
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
|
||||
{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
|
||||
};
|
||||
|
||||
@ -286,7 +286,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_6,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_ahb_clk_src",
|
||||
.parent_data = disp_cc_parent_data_6,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
|
||||
@ -306,7 +306,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_2,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_byte0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
||||
@ -321,7 +321,7 @@ static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_2,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_byte1_clk_src",
|
||||
.parent_data = disp_cc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
||||
@ -336,7 +336,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx0_aux_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
@ -350,7 +350,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_7,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx0_link_clk_src",
|
||||
.parent_data = disp_cc_parent_data_7,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
|
||||
@ -365,7 +365,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_4,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx0_pixel0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_4,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
|
||||
@ -380,7 +380,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_4,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx0_pixel1_clk_src",
|
||||
.parent_data = disp_cc_parent_data_4,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
|
||||
@ -395,12 +395,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx1_aux_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_dp_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -409,7 +409,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_3,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx1_link_clk_src",
|
||||
.parent_data = disp_cc_parent_data_3,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
|
||||
@ -424,7 +424,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx1_pixel0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
||||
@ -439,7 +439,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx1_pixel1_clk_src",
|
||||
.parent_data = disp_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
||||
@ -454,7 +454,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx2_aux_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
@ -468,7 +468,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_3,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx2_link_clk_src",
|
||||
.parent_data = disp_cc_parent_data_3,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
|
||||
@ -483,7 +483,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx2_pixel0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
||||
@ -498,7 +498,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx2_pixel1_clk_src",
|
||||
.parent_data = disp_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
||||
@ -513,7 +513,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx3_aux_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
@ -527,7 +527,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_3,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx3_link_clk_src",
|
||||
.parent_data = disp_cc_parent_data_3,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
|
||||
@ -542,7 +542,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx3_pixel0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
||||
@ -557,12 +557,12 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_5,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_esc0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_5,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -572,12 +572,12 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_5,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_esc1_clk_src",
|
||||
.parent_data = disp_cc_parent_data_5,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -594,13 +594,25 @@ static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sm8650[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(402000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
|
||||
.cmd_rcgr = 0x80d8,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_8,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_mdp_clk_src",
|
||||
.parent_data = disp_cc_parent_data_8,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_8),
|
||||
@ -615,7 +627,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_2,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_pclk0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
||||
@ -630,7 +642,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_2,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_pclk1_clk_src",
|
||||
.parent_data = disp_cc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
||||
@ -645,7 +657,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_vsync_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
@ -665,7 +677,7 @@ static struct clk_rcg2 disp_cc_sleep_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_9,
|
||||
.freq_tbl = ftbl_disp_cc_sleep_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_sleep_clk_src",
|
||||
.parent_data = disp_cc_parent_data_9,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_9),
|
||||
@ -680,7 +692,7 @@ static struct clk_rcg2 disp_cc_xo_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_xo_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0_ao,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao),
|
||||
@ -693,7 +705,7 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
|
||||
.reg = 0x8120,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_byte0_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_byte0_clk_src.clkr.hw,
|
||||
@ -707,7 +719,7 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
|
||||
.reg = 0x813c,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_byte1_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_byte1_clk_src.clkr.hw,
|
||||
@ -721,7 +733,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {
|
||||
.reg = 0x8188,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx0_link_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
|
||||
@ -736,7 +748,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {
|
||||
.reg = 0x821c,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx1_link_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
|
||||
@ -751,7 +763,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {
|
||||
.reg = 0x8250,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx2_link_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
|
||||
@ -766,7 +778,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {
|
||||
.reg = 0x82cc,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx3_link_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
|
||||
@ -783,7 +795,7 @@ static struct clk_branch disp_cc_mdss_accu_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0xe058,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_accu_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_xo_clk_src.clkr.hw,
|
||||
@ -801,7 +813,7 @@ static struct clk_branch disp_cc_mdss_ahb1_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0xa020,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_ahb1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
@ -819,7 +831,7 @@ static struct clk_branch disp_cc_mdss_ahb_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x80a4,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
@ -837,7 +849,7 @@ static struct clk_branch disp_cc_mdss_byte0_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8028,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_byte0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_byte0_clk_src.clkr.hw,
|
||||
@ -855,7 +867,7 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x802c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_byte0_intf_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
|
||||
@ -873,7 +885,7 @@ static struct clk_branch disp_cc_mdss_byte1_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8030,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_byte1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_byte1_clk_src.clkr.hw,
|
||||
@ -891,7 +903,7 @@ static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8034,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_byte1_intf_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_byte1_div_clk_src.clkr.hw,
|
||||
@ -909,7 +921,7 @@ static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8058,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx0_aux_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
|
||||
@ -927,7 +939,7 @@ static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x804c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx0_crypto_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
|
||||
@ -945,7 +957,7 @@ static struct clk_branch disp_cc_mdss_dptx0_link_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8040,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx0_link_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
|
||||
@ -963,7 +975,7 @@ static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8048,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx0_link_intf_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
|
||||
@ -981,7 +993,7 @@ static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8050,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx0_pixel0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
|
||||
@ -999,7 +1011,7 @@ static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8054,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx0_pixel1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
|
||||
@ -1017,7 +1029,7 @@ static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8044,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
|
||||
@ -1035,7 +1047,7 @@ static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8074,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx1_aux_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
|
||||
@ -1053,7 +1065,7 @@ static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8070,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx1_crypto_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
|
||||
@ -1071,7 +1083,7 @@ static struct clk_branch disp_cc_mdss_dptx1_link_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8064,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx1_link_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
|
||||
@ -1089,7 +1101,7 @@ static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x806c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx1_link_intf_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
|
||||
@ -1107,7 +1119,7 @@ static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x805c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx1_pixel0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
|
||||
@ -1125,7 +1137,7 @@ static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8060,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx1_pixel1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
|
||||
@ -1143,7 +1155,7 @@ static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8068,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
|
||||
@ -1161,7 +1173,7 @@ static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x808c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx2_aux_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,
|
||||
@ -1179,7 +1191,7 @@ static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8088,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx2_crypto_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
|
||||
@ -1197,7 +1209,7 @@ static struct clk_branch disp_cc_mdss_dptx2_link_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8080,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx2_link_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
|
||||
@ -1215,7 +1227,7 @@ static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8084,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx2_link_intf_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
|
||||
@ -1233,7 +1245,7 @@ static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8078,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx2_pixel0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
|
||||
@ -1251,7 +1263,7 @@ static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x807c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx2_pixel1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
|
||||
@ -1269,7 +1281,7 @@ static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x809c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx3_aux_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,
|
||||
@ -1287,7 +1299,7 @@ static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x80a0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx3_crypto_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
|
||||
@ -1305,7 +1317,7 @@ static struct clk_branch disp_cc_mdss_dptx3_link_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8094,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx3_link_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
|
||||
@ -1323,7 +1335,7 @@ static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8098,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx3_link_intf_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
|
||||
@ -1341,7 +1353,7 @@ static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8090,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dptx3_pixel0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
|
||||
@ -1359,7 +1371,7 @@ static struct clk_branch disp_cc_mdss_esc0_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8038,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_esc0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_esc0_clk_src.clkr.hw,
|
||||
@ -1377,7 +1389,7 @@ static struct clk_branch disp_cc_mdss_esc1_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x803c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_esc1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_esc1_clk_src.clkr.hw,
|
||||
@ -1395,7 +1407,7 @@ static struct clk_branch disp_cc_mdss_mdp1_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0xa004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_mdp1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
@ -1413,7 +1425,7 @@ static struct clk_branch disp_cc_mdss_mdp_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x800c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_mdp_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
@ -1431,7 +1443,7 @@ static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0xa010,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_mdp_lut1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
@ -1449,7 +1461,7 @@ static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8018,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_mdp_lut_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
@ -1467,7 +1479,7 @@ static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0xc004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
@ -1485,7 +1497,7 @@ static struct clk_branch disp_cc_mdss_pclk0_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_pclk0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
|
||||
@ -1503,7 +1515,7 @@ static struct clk_branch disp_cc_mdss_pclk1_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8008,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_pclk1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_pclk1_clk_src.clkr.hw,
|
||||
@ -1521,7 +1533,7 @@ static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0xc00c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_rscc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
@ -1539,7 +1551,7 @@ static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0xc008,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_rscc_vsync_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
||||
@ -1557,7 +1569,7 @@ static struct clk_branch disp_cc_mdss_vsync1_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0xa01c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_vsync1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
||||
@ -1575,7 +1587,7 @@ static struct clk_branch disp_cc_mdss_vsync_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0x8024,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_vsync_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
||||
@ -1593,7 +1605,7 @@ static struct clk_branch disp_cc_sleep_clk = {
|
||||
.clkr = {
|
||||
.enable_reg = 0xe074,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "disp_cc_sleep_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&disp_cc_sleep_clk_src.clkr.hw,
|
||||
@ -1611,7 +1623,7 @@ static struct gdsc mdss_gdsc = {
|
||||
.name = "mdss_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = HW_CTRL | RETAIN_FF_ENABLE,
|
||||
.flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc mdss_int2_gdsc = {
|
||||
@ -1620,7 +1632,7 @@ static struct gdsc mdss_int2_gdsc = {
|
||||
.name = "mdss_int2_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = HW_CTRL | RETAIN_FF_ENABLE,
|
||||
.flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct clk_regmap *disp_cc_sm8550_clocks[] = {
|
||||
@ -1739,6 +1751,7 @@ static struct qcom_cc_desc disp_cc_sm8550_desc = {
|
||||
|
||||
static const struct of_device_id disp_cc_sm8550_match_table[] = {
|
||||
{ .compatible = "qcom,sm8550-dispcc" },
|
||||
{ .compatible = "qcom,sm8650-dispcc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, disp_cc_sm8550_match_table);
|
||||
@ -1762,6 +1775,13 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev)
|
||||
goto err_put_rpm;
|
||||
}
|
||||
|
||||
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-dispcc")) {
|
||||
lucid_ole_vco[0].max_freq = 2100000000;
|
||||
disp_cc_mdss_mdp_clk_src.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src_sm8650;
|
||||
disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr.hw.init->parent_hws[0] =
|
||||
&disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw;
|
||||
}
|
||||
|
||||
clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
||||
clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
|
||||
|
||||
@ -1795,5 +1815,5 @@ static struct platform_driver disp_cc_sm8550_driver = {
|
||||
|
||||
module_platform_driver(disp_cc_sm8550_driver);
|
||||
|
||||
MODULE_DESCRIPTION("QTI DISPCC SM8550 Driver");
|
||||
MODULE_DESCRIPTION("QTI DISPCC SM8550 / SM8650 Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -4,12 +4,14 @@
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/interconnect-provider.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
|
||||
#include <dt-bindings/interconnect/qcom,ipq5332.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
@ -126,17 +128,6 @@ static struct clk_alpha_pll gpll4_main = {
|
||||
.parent_data = &gcc_parent_data_xo,
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_stromer_ops,
|
||||
/*
|
||||
* There are no consumers for this GPLL in kernel yet,
|
||||
* (will be added soon), so the clock framework
|
||||
* disables this source. But some of the clocks
|
||||
* initialized by boot loaders uses this source. So we
|
||||
* need to keep this clock ON. Add the
|
||||
* CLK_IGNORE_UNUSED flag so the clock will not be
|
||||
* disabled. Once the consumer in kernel is added, we
|
||||
* can get rid of this flag.
|
||||
*/
|
||||
.flags = CLK_IGNORE_UNUSED,
|
||||
},
|
||||
},
|
||||
};
|
||||
@ -3388,6 +3379,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
|
||||
[GCC_QDSS_DAP_DIV_CLK_SRC] = &gcc_qdss_dap_div_clk_src.clkr,
|
||||
[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
|
||||
[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
|
||||
[GCC_QDSS_TSCTR_CLK_SRC] = &gcc_qdss_tsctr_clk_src.clkr,
|
||||
[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
|
||||
[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
|
||||
[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
|
||||
@ -3628,6 +3620,24 @@ static const struct qcom_reset_map gcc_ipq5332_resets[] = {
|
||||
[GCC_UNIPHY1_XPCS_ARES] = { 0x16060 },
|
||||
};
|
||||
|
||||
#define IPQ_APPS_ID 5332 /* some unique value */
|
||||
|
||||
static struct qcom_icc_hws_data icc_ipq5332_hws[] = {
|
||||
{ MASTER_SNOC_PCIE3_1_M, SLAVE_SNOC_PCIE3_1_M, GCC_SNOC_PCIE3_1LANE_M_CLK },
|
||||
{ MASTER_ANOC_PCIE3_1_S, SLAVE_ANOC_PCIE3_1_S, GCC_SNOC_PCIE3_1LANE_S_CLK },
|
||||
{ MASTER_SNOC_PCIE3_2_M, SLAVE_SNOC_PCIE3_2_M, GCC_SNOC_PCIE3_2LANE_M_CLK },
|
||||
{ MASTER_ANOC_PCIE3_2_S, SLAVE_ANOC_PCIE3_2_S, GCC_SNOC_PCIE3_2LANE_S_CLK },
|
||||
{ MASTER_SNOC_USB, SLAVE_SNOC_USB, GCC_SNOC_USB_CLK },
|
||||
{ MASTER_NSSNOC_NSSCC, SLAVE_NSSNOC_NSSCC, GCC_NSSNOC_NSSCC_CLK },
|
||||
{ MASTER_NSSNOC_SNOC_0, SLAVE_NSSNOC_SNOC_0, GCC_NSSNOC_SNOC_CLK },
|
||||
{ MASTER_NSSNOC_SNOC_1, SLAVE_NSSNOC_SNOC_1, GCC_NSSNOC_SNOC_1_CLK },
|
||||
{ MASTER_NSSNOC_ATB, SLAVE_NSSNOC_ATB, GCC_NSSNOC_ATB_CLK },
|
||||
{ MASTER_NSSNOC_PCNOC_1, SLAVE_NSSNOC_PCNOC_1, GCC_NSSNOC_PCNOC_1_CLK },
|
||||
{ MASTER_NSSNOC_QOSGEN_REF, SLAVE_NSSNOC_QOSGEN_REF, GCC_NSSNOC_QOSGEN_REF_CLK },
|
||||
{ MASTER_NSSNOC_TIMEOUT_REF, SLAVE_NSSNOC_TIMEOUT_REF, GCC_NSSNOC_TIMEOUT_REF_CLK },
|
||||
{ MASTER_NSSNOC_XO_DCD, SLAVE_NSSNOC_XO_DCD, GCC_NSSNOC_XO_DCD_CLK },
|
||||
};
|
||||
|
||||
static const struct regmap_config gcc_ipq5332_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
@ -3656,6 +3666,9 @@ static const struct qcom_cc_desc gcc_ipq5332_desc = {
|
||||
.num_resets = ARRAY_SIZE(gcc_ipq5332_resets),
|
||||
.clk_hws = gcc_ipq5332_hws,
|
||||
.num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws),
|
||||
.icc_hws = icc_ipq5332_hws,
|
||||
.num_icc_hws = ARRAY_SIZE(icc_ipq5332_hws),
|
||||
.icc_first_node_id = IPQ_APPS_ID,
|
||||
};
|
||||
|
||||
static int gcc_ipq5332_probe(struct platform_device *pdev)
|
||||
@ -3674,6 +3687,7 @@ static struct platform_driver gcc_ipq5332_driver = {
|
||||
.driver = {
|
||||
.name = "gcc-ipq5332",
|
||||
.of_match_table = gcc_ipq5332_match_table,
|
||||
.sync_state = icc_sync_state,
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
@ -2684,7 +2684,7 @@ static struct clk_rcg2 lpass_q6_axim_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_rbcpr_wcss_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_rbcpr_wcss_clk_src[] = {
|
||||
F(24000000, P_XO, 1, 0, 0),
|
||||
F(50000000, P_GPLL0, 16, 0, 0),
|
||||
{ }
|
||||
|
||||
@ -390,7 +390,7 @@ static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
|
||||
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_gsbi_uart[] = {
|
||||
static const struct freq_tbl clk_tbl_gsbi_uart[] = {
|
||||
{ 1843200, P_PLL8, 2, 6, 625 },
|
||||
{ 3686400, P_PLL8, 2, 12, 625 },
|
||||
{ 7372800, P_PLL8, 2, 24, 625 },
|
||||
@ -714,7 +714,7 @@ static struct clk_branch gsbi7_uart_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_gsbi_qup[] = {
|
||||
static const struct freq_tbl clk_tbl_gsbi_qup[] = {
|
||||
{ 1100000, P_PXO, 1, 2, 49 },
|
||||
{ 5400000, P_PXO, 1, 1, 5 },
|
||||
{ 10800000, P_PXO, 1, 2, 5 },
|
||||
|
||||
@ -1947,7 +1947,7 @@ static struct clk_regmap_div nss_port6_tx_div_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_crypto_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_crypto_clk_src[] = {
|
||||
F(40000000, P_GPLL0_DIV2, 10, 0, 0),
|
||||
F(80000000, P_GPLL0, 10, 0, 0),
|
||||
F(100000000, P_GPLL0, 8, 0, 0),
|
||||
@ -1968,7 +1968,7 @@ static struct clk_rcg2 crypto_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_gp_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_gp_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
@ -164,7 +164,7 @@ static const struct clk_parent_data gcc_cxo_pll14[] = {
|
||||
{ .hw = &pll14_vote.hw },
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_gsbi_uart[] = {
|
||||
static const struct freq_tbl clk_tbl_gsbi_uart[] = {
|
||||
{ 1843200, P_PLL8, 2, 6, 625 },
|
||||
{ 3686400, P_PLL8, 2, 12, 625 },
|
||||
{ 7372800, P_PLL8, 2, 24, 625 },
|
||||
@ -437,7 +437,7 @@ static struct clk_branch gsbi5_uart_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_gsbi_qup[] = {
|
||||
static const struct freq_tbl clk_tbl_gsbi_qup[] = {
|
||||
{ 960000, P_CXO, 4, 1, 5 },
|
||||
{ 4800000, P_CXO, 4, 0, 1 },
|
||||
{ 9600000, P_CXO, 2, 0, 1 },
|
||||
|
||||
@ -82,7 +82,7 @@ static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
|
||||
{ .fw_name = "cxo", .name = "cxo_board" },
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_gsbi_uart[] = {
|
||||
static const struct freq_tbl clk_tbl_gsbi_uart[] = {
|
||||
{ 1843200, P_PLL8, 2, 6, 625 },
|
||||
{ 3686400, P_PLL8, 2, 12, 625 },
|
||||
{ 7372800, P_PLL8, 2, 24, 625 },
|
||||
@ -712,7 +712,7 @@ static struct clk_branch gsbi12_uart_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_gsbi_qup[] = {
|
||||
static const struct freq_tbl clk_tbl_gsbi_qup[] = {
|
||||
{ 1100000, P_PXO, 1, 2, 49 },
|
||||
{ 5400000, P_PXO, 1, 1, 5 },
|
||||
{ 10800000, P_PXO, 1, 2, 5 },
|
||||
|
||||
@ -328,7 +328,7 @@ static const struct clk_parent_data gcc_pxo_pll8_pll3[] = {
|
||||
{ .hw = &pll3.clkr.hw },
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_gsbi_uart[] = {
|
||||
static const struct freq_tbl clk_tbl_gsbi_uart[] = {
|
||||
{ 1843200, P_PLL8, 2, 6, 625 },
|
||||
{ 3686400, P_PLL8, 2, 12, 625 },
|
||||
{ 7372800, P_PLL8, 2, 24, 625 },
|
||||
@ -958,7 +958,7 @@ static struct clk_branch gsbi12_uart_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_gsbi_qup[] = {
|
||||
static const struct freq_tbl clk_tbl_gsbi_qup[] = {
|
||||
{ 1100000, P_PXO, 1, 2, 49 },
|
||||
{ 5400000, P_PXO, 1, 1, 5 },
|
||||
{ 10800000, P_PXO, 1, 2, 5 },
|
||||
@ -2940,7 +2940,7 @@ static struct clk_branch adm0_pbus_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_ce3[] = {
|
||||
static const struct freq_tbl clk_tbl_ce3[] = {
|
||||
{ 48000000, P_PLL8, 8 },
|
||||
{ 100000000, P_PLL3, 12 },
|
||||
{ 120000000, P_PLL3, 10 },
|
||||
|
||||
@ -112,7 +112,7 @@ static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
|
||||
{ .hw = &gpll4.clkr.hw },
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
|
||||
F(50000000, P_GPLL0, 12, 0, 0),
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
F(150000000, P_GPLL0, 4, 0, 0),
|
||||
@ -136,7 +136,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_usb30_master_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(125000000, P_GPLL0, 1, 5, 24),
|
||||
{ }
|
||||
@ -156,7 +156,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(50000000, P_GPLL0, 12, 0, 0),
|
||||
{ }
|
||||
@ -175,7 +175,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
|
||||
F(960000, P_XO, 10, 1, 2),
|
||||
F(4800000, P_XO, 4, 0, 0),
|
||||
F(9600000, P_XO, 2, 0, 0),
|
||||
@ -188,7 +188,7 @@ static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = {
|
||||
static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = {
|
||||
F(960000, P_XO, 10, 1, 2),
|
||||
F(4800000, P_XO, 4, 0, 0),
|
||||
F(9600000, P_XO, 2, 0, 0),
|
||||
@ -226,7 +226,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
|
||||
F(960000, P_XO, 10, 1, 2),
|
||||
F(4800000, P_XO, 4, 0, 0),
|
||||
F(9600000, P_XO, 2, 0, 0),
|
||||
@ -266,7 +266,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = {
|
||||
F(960000, P_XO, 10, 1, 2),
|
||||
F(4800000, P_XO, 4, 0, 0),
|
||||
F(9600000, P_XO, 2, 0, 0),
|
||||
@ -333,7 +333,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = {
|
||||
F(960000, P_XO, 10, 1, 2),
|
||||
F(4800000, P_XO, 4, 0, 0),
|
||||
F(9600000, P_XO, 2, 0, 0),
|
||||
@ -373,7 +373,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = {
|
||||
F(960000, P_XO, 10, 1, 2),
|
||||
F(4800000, P_XO, 4, 0, 0),
|
||||
F(9600000, P_XO, 2, 0, 0),
|
||||
@ -400,7 +400,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
|
||||
F(3686400, P_GPLL0, 1, 96, 15625),
|
||||
F(7372800, P_GPLL0, 1, 192, 15625),
|
||||
F(14745600, P_GPLL0, 1, 384, 15625),
|
||||
@ -516,7 +516,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = {
|
||||
F(960000, P_XO, 10, 1, 2),
|
||||
F(4800000, P_XO, 4, 0, 0),
|
||||
F(9600000, P_XO, 2, 0, 0),
|
||||
@ -570,7 +570,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = {
|
||||
F(960000, P_XO, 10, 1, 2),
|
||||
F(4800000, P_XO, 4, 0, 0),
|
||||
F(9600000, P_XO, 2, 0, 0),
|
||||
@ -678,7 +678,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = {
|
||||
F(960000, P_XO, 10, 1, 2),
|
||||
F(4800000, P_XO, 4, 0, 0),
|
||||
F(9600000, P_XO, 2, 0, 0),
|
||||
@ -789,7 +789,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_gp1_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_gp1_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
F(200000000, P_GPLL0, 3, 0, 0),
|
||||
@ -810,7 +810,7 @@ static struct clk_rcg2 gp1_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_gp2_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_gp2_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
F(200000000, P_GPLL0, 3, 0, 0),
|
||||
@ -831,7 +831,7 @@ static struct clk_rcg2 gp2_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_gp3_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_gp3_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
F(200000000, P_GPLL0, 3, 0, 0),
|
||||
@ -852,7 +852,7 @@ static struct clk_rcg2 gp3_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
|
||||
F(1011000, P_XO, 1, 1, 19),
|
||||
{ }
|
||||
};
|
||||
@ -872,7 +872,7 @@ static struct clk_rcg2 pcie_0_aux_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
|
||||
F(125000000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -891,7 +891,7 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
|
||||
F(1011000, P_XO, 1, 1, 19),
|
||||
{ }
|
||||
};
|
||||
@ -925,7 +925,7 @@ static struct clk_rcg2 pcie_1_pipe_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_pdm2_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_pdm2_clk_src[] = {
|
||||
F(60000000, P_GPLL0, 10, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -943,7 +943,7 @@ static struct clk_rcg2 pdm2_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
|
||||
F(144000, P_XO, 16, 3, 25),
|
||||
F(400000, P_XO, 12, 1, 4),
|
||||
F(20000000, P_GPLL0, 15, 1, 2),
|
||||
@ -955,7 +955,7 @@ static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = {
|
||||
static const struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = {
|
||||
F(144000, P_XO, 16, 3, 25),
|
||||
F(400000, P_XO, 12, 1, 4),
|
||||
F(20000000, P_GPLL0, 15, 1, 2),
|
||||
@ -981,7 +981,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
|
||||
F(144000, P_XO, 16, 3, 25),
|
||||
F(400000, P_XO, 12, 1, 4),
|
||||
F(20000000, P_GPLL0, 15, 1, 2),
|
||||
@ -1034,7 +1034,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
|
||||
F(105500, P_XO, 1, 1, 182),
|
||||
{ }
|
||||
};
|
||||
@ -1054,7 +1054,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(60000000, P_GPLL0, 10, 0, 0),
|
||||
{ }
|
||||
@ -1073,7 +1073,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
|
||||
F(1200000, P_XO, 16, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -1092,7 +1092,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
|
||||
F(75000000, P_GPLL0, 8, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
@ -359,7 +359,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(150000000, P_GPLL0, 4, 0, 0),
|
||||
F(300000000, P_GPLL0, 2, 0, 0),
|
||||
|
||||
@ -2242,7 +2242,7 @@ static struct clk_branch gcc_hmss_trig_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
|
||||
F( 300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
|
||||
F( 600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
|
||||
{ }
|
||||
@ -2922,6 +2922,43 @@ static struct clk_branch ssc_cnoc_ahbs_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch hlos1_vote_lpass_core_smmu_clk = {
|
||||
.halt_reg = 0x7D010,
|
||||
.clkr = {
|
||||
.enable_reg = 0x7D010,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "hlos1_vote_lpass_core_smmu_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = {
|
||||
.halt_reg = 0x7D014,
|
||||
.clkr = {
|
||||
.enable_reg = 0x7D014,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "hlos1_vote_lpass_adsp_smmu_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
|
||||
.halt_reg = 0x8A040,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8A040,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "gcc_mss_q6_bimc_axi_clk",
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc pcie_0_gdsc = {
|
||||
.gdscr = 0x6b004,
|
||||
.gds_hw_ctrl = 0x0,
|
||||
@ -2953,6 +2990,26 @@ static struct gdsc usb_30_gdsc = {
|
||||
.flags = VOTABLE,
|
||||
};
|
||||
|
||||
static struct gdsc hlos1_vote_lpass_adsp = {
|
||||
.gdscr = 0x7d034,
|
||||
.gds_hw_ctrl = 0x0,
|
||||
.pd = {
|
||||
.name = "lpass_adsp_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = VOTABLE,
|
||||
};
|
||||
|
||||
static struct gdsc hlos1_vote_lpass_core = {
|
||||
.gdscr = 0x7d038,
|
||||
.gds_hw_ctrl = 0x0,
|
||||
.pd = {
|
||||
.name = "lpass_core_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = ALWAYS_ON,
|
||||
};
|
||||
|
||||
static struct clk_regmap *gcc_msm8998_clocks[] = {
|
||||
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
|
||||
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
|
||||
@ -3133,12 +3190,17 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
|
||||
[GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
|
||||
[GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
|
||||
[GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
|
||||
[HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &hlos1_vote_lpass_core_smmu_clk.clkr,
|
||||
[HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &hlos1_vote_lpass_adsp_smmu_clk.clkr,
|
||||
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
|
||||
};
|
||||
|
||||
static struct gdsc *gcc_msm8998_gdscs[] = {
|
||||
[PCIE_0_GDSC] = &pcie_0_gdsc,
|
||||
[UFS_GDSC] = &ufs_gdsc,
|
||||
[USB_30_GDSC] = &usb_30_gdsc,
|
||||
[LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp,
|
||||
[LPASS_CORE_GDSC] = &hlos1_vote_lpass_core,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map gcc_msm8998_resets[] = {
|
||||
|
||||
@ -142,6 +142,23 @@ static struct clk_alpha_pll gpll7 = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpll9 = {
|
||||
.offset = 0x1c000,
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
|
||||
.clkr = {
|
||||
.enable_reg = 0x52000,
|
||||
.enable_mask = BIT(9),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpll9",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.fw_name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_fixed_trion_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPLL0_OUT_MAIN, 1 },
|
||||
@ -241,7 +258,7 @@ static const struct parent_map gcc_parent_map_7[] = {
|
||||
static const struct clk_parent_data gcc_parents_7[] = {
|
||||
{ .fw_name = "bi_tcxo", },
|
||||
{ .hw = &gpll0.clkr.hw },
|
||||
{ .name = "gppl9" },
|
||||
{ .hw = &gpll9.clkr.hw },
|
||||
{ .hw = &gpll4.clkr.hw },
|
||||
{ .hw = &gpll0_out_even.clkr.hw },
|
||||
};
|
||||
@ -260,28 +277,6 @@ static const struct clk_parent_data gcc_parents_8[] = {
|
||||
{ .hw = &gpll0_out_even.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
|
||||
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
|
||||
.cmd_rcgr = 0x48014,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_cpuss_ahb_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
|
||||
@ -609,19 +604,29 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap0_s0_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
|
||||
.cmd_rcgr = 0x17148,
|
||||
.mnd_width = 16,
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap0_s0_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap0_s1_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
|
||||
@ -630,13 +635,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap0_s1_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap0_s2_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
|
||||
@ -645,13 +652,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap0_s2_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap0_s3_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
|
||||
@ -660,13 +669,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap0_s3_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap0_s4_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
|
||||
@ -675,13 +686,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap0_s4_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap0_s5_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
|
||||
@ -690,13 +703,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap0_s5_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap0_s6_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
|
||||
@ -705,13 +720,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap0_s6_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap0_s7_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
|
||||
@ -720,13 +737,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap0_s7_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap1_s0_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
|
||||
@ -735,13 +754,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s0_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap1_s1_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
|
||||
@ -750,13 +771,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s1_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap1_s2_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
|
||||
@ -765,13 +788,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s2_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap1_s3_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
|
||||
@ -780,13 +805,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s3_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap1_s4_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
|
||||
@ -795,13 +822,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s4_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap1_s5_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
|
||||
@ -810,13 +839,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s5_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap2_s0_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
|
||||
@ -825,13 +856,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap2_s0_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap2_s1_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
|
||||
@ -840,28 +873,33 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap2_s1_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap2_s2_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
|
||||
.cmd_rcgr = 0x1e3a8,
|
||||
.mnd_width = 16,
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap2_s2_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap2_s3_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
|
||||
@ -870,13 +908,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap2_s3_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap2_s4_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
|
||||
@ -885,13 +925,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap2_s4_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
|
||||
};
|
||||
|
||||
static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
|
||||
.name = "gcc_qupv3_wrap2_s5_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
|
||||
@ -900,13 +942,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap2_s5_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
|
||||
@ -916,7 +952,7 @@ static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
|
||||
F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
|
||||
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
|
||||
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
|
||||
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
@ -939,9 +975,8 @@ static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
|
||||
F(400000, P_BI_TCXO, 12, 1, 4),
|
||||
F(9600000, P_BI_TCXO, 2, 0, 0),
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
|
||||
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
|
||||
F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
|
||||
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
@ -1599,25 +1634,6 @@ static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
/* For CPUSS functionality the AHB clock needs to be left enabled */
|
||||
static struct clk_branch gcc_cpuss_ahb_clk = {
|
||||
.halt_reg = 0x48000,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x52004,
|
||||
.enable_mask = BIT(21),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_cpuss_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw *[]){
|
||||
&gcc_cpuss_ahb_clk_src.clkr.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_cpuss_rbcpr_clk = {
|
||||
.halt_reg = 0x48008,
|
||||
.halt_check = BRANCH_HALT,
|
||||
@ -3150,25 +3166,6 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
/* For CPUSS functionality the SYS NOC clock needs to be left enabled */
|
||||
static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
|
||||
.halt_reg = 0x4819c,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x52004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_sys_noc_cpuss_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw *[]){
|
||||
&gcc_cpuss_ahb_clk_src.clkr.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_tsif_ahb_clk = {
|
||||
.halt_reg = 0x36004,
|
||||
.halt_check = BRANCH_HALT,
|
||||
@ -4284,8 +4281,6 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = {
|
||||
[GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr,
|
||||
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
|
||||
[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
|
||||
[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
|
||||
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
|
||||
[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
|
||||
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
|
||||
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
|
||||
@ -4422,7 +4417,6 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = {
|
||||
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
|
||||
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
|
||||
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
|
||||
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
|
||||
[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
|
||||
[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
|
||||
[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
|
||||
@ -4511,6 +4505,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = {
|
||||
[GPLL1] = &gpll1.clkr,
|
||||
[GPLL4] = &gpll4.clkr,
|
||||
[GPLL7] = &gpll7.clkr,
|
||||
[GPLL9] = &gpll9.clkr,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map gcc_sc8180x_resets[] = {
|
||||
@ -4546,6 +4541,10 @@ static const struct qcom_reset_map gcc_sc8180x_resets[] = {
|
||||
[GCC_USB3_PHY_SEC_BCR] = { 0x50018 },
|
||||
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c },
|
||||
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 },
|
||||
[GCC_USB3_UNIPHY_MP0_BCR] = { 0x50024 },
|
||||
[GCC_USB3_UNIPHY_MP1_BCR] = { 0x50028 },
|
||||
[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5002c },
|
||||
[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x50030 },
|
||||
[GCC_SDCC2_BCR] = { 0x14000 },
|
||||
[GCC_SDCC4_BCR] = { 0x16000 },
|
||||
[GCC_TSIF_BCR] = { 0x36000 },
|
||||
@ -4561,6 +4560,29 @@ static const struct qcom_reset_map gcc_sc8180x_resets[] = {
|
||||
[GCC_VIDEO_AXI1_CLK_BCR] = { .reg = 0xb028, .bit = 2, .udelay = 150 },
|
||||
};
|
||||
|
||||
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
|
||||
};
|
||||
|
||||
static struct gdsc *gcc_sc8180x_gdscs[] = {
|
||||
[EMAC_GDSC] = &emac_gdsc,
|
||||
[PCIE_0_GDSC] = &pcie_0_gdsc,
|
||||
@ -4602,6 +4624,7 @@ MODULE_DEVICE_TABLE(of, gcc_sc8180x_match_table);
|
||||
static int gcc_sc8180x_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &gcc_sc8180x_desc);
|
||||
if (IS_ERR(regmap))
|
||||
@ -4623,6 +4646,11 @@ static int gcc_sc8180x_probe(struct platform_device *pdev)
|
||||
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
|
||||
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
|
||||
|
||||
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
|
||||
ARRAY_SIZE(gcc_dfs_clocks));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return qcom_cc_really_probe(&pdev->dev, &gcc_sc8180x_desc, regmap);
|
||||
}
|
||||
|
||||
|
||||
@ -3226,7 +3226,7 @@ static struct gdsc pcie_0_gdsc = {
|
||||
.pd = {
|
||||
.name = "pcie_0_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
};
|
||||
|
||||
static struct gdsc pcie_1_gdsc = {
|
||||
@ -3234,7 +3234,7 @@ static struct gdsc pcie_1_gdsc = {
|
||||
.pd = {
|
||||
.name = "pcie_1_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
};
|
||||
|
||||
static struct gdsc pcie_2_gdsc = {
|
||||
@ -3242,7 +3242,7 @@ static struct gdsc pcie_2_gdsc = {
|
||||
.pd = {
|
||||
.name = "pcie_2_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
};
|
||||
|
||||
static struct gdsc ufs_card_gdsc = {
|
||||
|
||||
@ -2974,7 +2974,7 @@ static struct gdsc pcie_0_gdsc = {
|
||||
.pd = {
|
||||
.name = "pcie_0_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
};
|
||||
|
||||
static struct gdsc pcie_1_gdsc = {
|
||||
@ -2982,7 +2982,7 @@ static struct gdsc pcie_1_gdsc = {
|
||||
.pd = {
|
||||
.name = "pcie_1_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
};
|
||||
|
||||
static struct gdsc ufs_phy_gdsc = {
|
||||
|
||||
805
drivers/clk/qcom/gpucc-sm4450.c
Normal file
805
drivers/clk/qcom/gpucc-sm4450.c
Normal file
@ -0,0 +1,805 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,sm4450-gpucc.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-pll.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "common.h"
|
||||
#include "gdsc.h"
|
||||
#include "reset.h"
|
||||
|
||||
enum {
|
||||
DT_BI_TCXO,
|
||||
DT_GPLL0_OUT_MAIN,
|
||||
DT_GPLL0_OUT_MAIN_DIV,
|
||||
};
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_GPLL0_OUT_MAIN,
|
||||
P_GPLL0_OUT_MAIN_DIV,
|
||||
P_GPU_CC_PLL0_OUT_EVEN,
|
||||
P_GPU_CC_PLL0_OUT_MAIN,
|
||||
P_GPU_CC_PLL0_OUT_ODD,
|
||||
P_GPU_CC_PLL1_OUT_EVEN,
|
||||
P_GPU_CC_PLL1_OUT_MAIN,
|
||||
P_GPU_CC_PLL1_OUT_ODD,
|
||||
};
|
||||
|
||||
static const struct pll_vco lucid_evo_vco[] = {
|
||||
{ 249600000, 2020000000, 0 },
|
||||
};
|
||||
|
||||
/* 680.0 MHz Configuration */
|
||||
static const struct alpha_pll_config gpu_cc_pll0_config = {
|
||||
.l = 0x23,
|
||||
.alpha = 0x6aaa,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x32aa299c,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000805,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpu_cc_pll0 = {
|
||||
.offset = 0x0,
|
||||
.vco_table = lucid_evo_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_evo_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_pll0",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.index = DT_BI_TCXO,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_evo_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* 500.0 MHz Configuration */
|
||||
static const struct alpha_pll_config gpu_cc_pll1_config = {
|
||||
.l = 0x1a,
|
||||
.alpha = 0xaaa,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x32aa299c,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000805,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpu_cc_pll1 = {
|
||||
.offset = 0x1000,
|
||||
.vco_table = lucid_evo_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_evo_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_pll1",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.index = DT_BI_TCXO,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_evo_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .index = DT_GPLL0_OUT_MAIN },
|
||||
{ .index = DT_GPLL0_OUT_MAIN_DIV },
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
|
||||
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .hw = &gpu_cc_pll0.clkr.hw },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .index = DT_GPLL0_OUT_MAIN },
|
||||
{ .index = DT_GPLL0_OUT_MAIN_DIV },
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_2[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPU_CC_PLL0_OUT_EVEN, 1 },
|
||||
{ P_GPU_CC_PLL0_OUT_ODD, 2 },
|
||||
{ P_GPU_CC_PLL1_OUT_EVEN, 3 },
|
||||
{ P_GPU_CC_PLL1_OUT_ODD, 4 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .hw = &gpu_cc_pll0.clkr.hw },
|
||||
{ .hw = &gpu_cc_pll0.clkr.hw },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .index = DT_GPLL0_OUT_MAIN },
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_3[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_3[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .index = DT_GPLL0_OUT_MAIN },
|
||||
{ .index = DT_GPLL0_OUT_MAIN_DIV },
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_4[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_4[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
|
||||
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_ff_clk_src = {
|
||||
.cmd_rcgr = 0x9474,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_ff_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
|
||||
.cmd_rcgr = 0x9318,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_gmu_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
|
||||
F(340000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
|
||||
F(500000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
|
||||
F(605000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
|
||||
F(765000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
|
||||
F(850000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
|
||||
F(955000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
|
||||
F(1010000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
|
||||
.cmd_rcgr = 0x9070,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_2,
|
||||
.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_gx_gfx3d_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
|
||||
F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_hub_clk_src = {
|
||||
.cmd_rcgr = 0x93ec,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_3,
|
||||
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_hub_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_3,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_xo_clk_src = {
|
||||
.cmd_rcgr = 0x9010,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_4,
|
||||
.freq_tbl = ftbl_gpu_cc_xo_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_xo_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_4,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_4),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
|
||||
.reg = 0x9054,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_demet_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_xo_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
|
||||
.reg = 0x9430,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_hub_ahb_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
|
||||
.reg = 0x942c,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_hub_cx_int_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div gpu_cc_xo_div_clk_src = {
|
||||
.reg = 0x9050,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_xo_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_xo_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_ahb_clk = {
|
||||
.halt_reg = 0x911c,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x911c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_crc_ahb_clk = {
|
||||
.halt_reg = 0x9120,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9120,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_crc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_ff_clk = {
|
||||
.halt_reg = 0x914c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x914c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_cx_ff_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_ff_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_gfx3d_clk = {
|
||||
.halt_reg = 0x919c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x919c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_cx_gfx3d_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = {
|
||||
.halt_reg = 0x91a0,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x91a0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_cx_gfx3d_slv_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_gmu_clk = {
|
||||
.halt_reg = 0x913c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x913c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_cx_gmu_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_gmu_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
|
||||
.halt_reg = 0x9130,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9130,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_cx_snoc_dvm_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cxo_clk = {
|
||||
.halt_reg = 0x9144,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9144,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_cxo_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_xo_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_freq_measure_clk = {
|
||||
.halt_reg = 0x9008,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9008,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_freq_measure_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_xo_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_cxo_clk = {
|
||||
.halt_reg = 0x90b8,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90b8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_gx_cxo_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_xo_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_ff_clk = {
|
||||
.halt_reg = 0x90c0,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90c0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_gx_ff_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_ff_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
|
||||
.halt_reg = 0x90a8,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90a8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_gx_gfx3d_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = {
|
||||
.halt_reg = 0x90c8,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90c8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_gx_gfx3d_rdvm_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_gmu_clk = {
|
||||
.halt_reg = 0x90bc,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90bc,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_gx_gmu_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_gmu_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_vsense_clk = {
|
||||
.halt_reg = 0x90b0,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90b0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_gx_vsense_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hub_aon_clk = {
|
||||
.halt_reg = 0x93e8,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x93e8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_hub_aon_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hub_cx_int_clk = {
|
||||
.halt_reg = 0x9148,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9148,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_hub_cx_int_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
|
||||
.halt_reg = 0x9150,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9150,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_memnoc_gfx_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
|
||||
.halt_reg = 0x9288,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9288,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_mnd1x_0_gfx3d_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_sleep_clk = {
|
||||
.halt_reg = 0x9134,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9134,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_sleep_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc gpu_cc_cx_gdsc = {
|
||||
.gdscr = 0x9108,
|
||||
.gds_hw_ctrl = 0x953c,
|
||||
.clk_dis_wait_val = 8,
|
||||
.pd = {
|
||||
.name = "gpu_cx_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = VOTABLE | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc gpu_cc_gx_gdsc = {
|
||||
.gdscr = 0x905c,
|
||||
.clamp_io_ctrl = 0x9504,
|
||||
.resets = (unsigned int []){ GPU_CC_GX_BCR,
|
||||
GPU_CC_ACD_BCR,
|
||||
GPU_CC_GX_ACD_IROOT_BCR },
|
||||
.reset_count = 3,
|
||||
.pd = {
|
||||
.name = "gpu_gx_gdsc",
|
||||
.power_on = gdsc_gx_do_nothing_enable,
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
|
||||
};
|
||||
|
||||
static struct clk_regmap *gpu_cc_sm4450_clocks[] = {
|
||||
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
|
||||
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
|
||||
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
|
||||
[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
|
||||
[GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr,
|
||||
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
|
||||
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
|
||||
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
|
||||
[GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
|
||||
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
|
||||
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
|
||||
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
|
||||
[GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,
|
||||
[GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr,
|
||||
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
|
||||
[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
|
||||
[GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr,
|
||||
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
|
||||
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
|
||||
[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
|
||||
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
|
||||
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
|
||||
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
|
||||
[GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
|
||||
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
|
||||
[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
|
||||
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
|
||||
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
|
||||
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
|
||||
[GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
|
||||
[GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,
|
||||
};
|
||||
|
||||
static struct gdsc *gpu_cc_sm4450_gdscs[] = {
|
||||
[GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc,
|
||||
[GPU_CC_GX_GDSC] = &gpu_cc_gx_gdsc,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map gpu_cc_sm4450_resets[] = {
|
||||
[GPU_CC_CB_BCR] = { 0x93a0 },
|
||||
[GPU_CC_CX_BCR] = { 0x9104 },
|
||||
[GPU_CC_GX_BCR] = { 0x9058 },
|
||||
[GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
|
||||
[GPU_CC_ACD_BCR] = { 0x9358 },
|
||||
[GPU_CC_FF_BCR] = { 0x9470 },
|
||||
[GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
|
||||
[GPU_CC_GMU_BCR] = { 0x9314 },
|
||||
[GPU_CC_RBCPR_BCR] = { 0x91e0 },
|
||||
[GPU_CC_XO_BCR] = { 0x9000 },
|
||||
[GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c },
|
||||
};
|
||||
|
||||
static const struct regmap_config gpu_cc_sm4450_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x95c0,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc gpu_cc_sm4450_desc = {
|
||||
.config = &gpu_cc_sm4450_regmap_config,
|
||||
.clks = gpu_cc_sm4450_clocks,
|
||||
.num_clks = ARRAY_SIZE(gpu_cc_sm4450_clocks),
|
||||
.resets = gpu_cc_sm4450_resets,
|
||||
.num_resets = ARRAY_SIZE(gpu_cc_sm4450_resets),
|
||||
.gdscs = gpu_cc_sm4450_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(gpu_cc_sm4450_gdscs),
|
||||
};
|
||||
|
||||
static const struct of_device_id gpu_cc_sm4450_match_table[] = {
|
||||
{ .compatible = "qcom,sm4450-gpucc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, gpu_cc_sm4450_match_table);
|
||||
|
||||
static int gpu_cc_sm4450_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &gpu_cc_sm4450_desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
|
||||
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
|
||||
|
||||
/* Keep some clocks always enabled */
|
||||
qcom_branch_set_clk_en(regmap, 0x93a4); /* GPU_CC_CB_CLK */
|
||||
qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */
|
||||
qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */
|
||||
|
||||
return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm4450_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver gpu_cc_sm4450_driver = {
|
||||
.probe = gpu_cc_sm4450_probe,
|
||||
.driver = {
|
||||
.name = "gpucc-sm4450",
|
||||
.of_match_table = gpu_cc_sm4450_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(gpu_cc_sm4450_driver);
|
||||
|
||||
MODULE_DESCRIPTION("QTI GPUCC SM4450 Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
@ -70,7 +70,7 @@ static const struct clk_parent_data lcc_pxo_pll4[] = {
|
||||
{ .fw_name = "pll4_vote", .name = "pll4_vote" },
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_aif_mi2s[] = {
|
||||
static const struct freq_tbl clk_tbl_aif_mi2s[] = {
|
||||
{ 1024000, P_PLL4, 4, 1, 96 },
|
||||
{ 1411200, P_PLL4, 4, 2, 139 },
|
||||
{ 1536000, P_PLL4, 4, 1, 64 },
|
||||
@ -214,7 +214,7 @@ static struct clk_regmap_mux mi2s_bit_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_pcm[] = {
|
||||
static const struct freq_tbl clk_tbl_pcm[] = {
|
||||
{ 64000, P_PLL4, 4, 1, 1536 },
|
||||
{ 128000, P_PLL4, 4, 1, 768 },
|
||||
{ 256000, P_PLL4, 4, 1, 384 },
|
||||
@ -296,7 +296,7 @@ static struct clk_regmap_mux pcm_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_aif_osr[] = {
|
||||
static const struct freq_tbl clk_tbl_aif_osr[] = {
|
||||
{ 2822400, P_PLL4, 1, 147, 20480 },
|
||||
{ 4096000, P_PLL4, 1, 1, 96 },
|
||||
{ 5644800, P_PLL4, 1, 147, 10240 },
|
||||
@ -360,7 +360,7 @@ static struct clk_branch spdif_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_ahbix[] = {
|
||||
static const struct freq_tbl clk_tbl_ahbix[] = {
|
||||
{ 131072000, P_PLL4, 1, 1, 3 },
|
||||
{ },
|
||||
};
|
||||
|
||||
@ -57,7 +57,7 @@ static struct clk_parent_data lcc_pxo_pll4[] = {
|
||||
{ .fw_name = "pll4_vote", .name = "pll4_vote" },
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_aif_osr_492[] = {
|
||||
static const struct freq_tbl clk_tbl_aif_osr_492[] = {
|
||||
{ 512000, P_PLL4, 4, 1, 240 },
|
||||
{ 768000, P_PLL4, 4, 1, 160 },
|
||||
{ 1024000, P_PLL4, 4, 1, 120 },
|
||||
@ -73,7 +73,7 @@ static struct freq_tbl clk_tbl_aif_osr_492[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_aif_osr_393[] = {
|
||||
static const struct freq_tbl clk_tbl_aif_osr_393[] = {
|
||||
{ 512000, P_PLL4, 4, 1, 192 },
|
||||
{ 768000, P_PLL4, 4, 1, 128 },
|
||||
{ 1024000, P_PLL4, 4, 1, 96 },
|
||||
@ -218,7 +218,7 @@ CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
|
||||
CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74);
|
||||
CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c);
|
||||
|
||||
static struct freq_tbl clk_tbl_pcm_492[] = {
|
||||
static const struct freq_tbl clk_tbl_pcm_492[] = {
|
||||
{ 256000, P_PLL4, 4, 1, 480 },
|
||||
{ 512000, P_PLL4, 4, 1, 240 },
|
||||
{ 768000, P_PLL4, 4, 1, 160 },
|
||||
@ -235,7 +235,7 @@ static struct freq_tbl clk_tbl_pcm_492[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_pcm_393[] = {
|
||||
static const struct freq_tbl clk_tbl_pcm_393[] = {
|
||||
{ 256000, P_PLL4, 4, 1, 384 },
|
||||
{ 512000, P_PLL4, 4, 1, 192 },
|
||||
{ 768000, P_PLL4, 4, 1, 128 },
|
||||
|
||||
@ -338,7 +338,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mmss_axi_clk[] = {
|
||||
static const struct freq_tbl ftbl_mmss_axi_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(37500000, P_GPLL0, 16, 0, 0),
|
||||
F(50000000, P_GPLL0, 12, 0, 0),
|
||||
@ -364,7 +364,7 @@ static struct clk_rcg2 mmss_axi_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_ocmemnoc_clk[] = {
|
||||
static const struct freq_tbl ftbl_ocmemnoc_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(37500000, P_GPLL0, 16, 0, 0),
|
||||
F(50000000, P_GPLL0, 12, 0, 0),
|
||||
@ -389,7 +389,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
|
||||
static const struct freq_tbl ftbl_camss_csi0_3_clk[] = {
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
F(200000000, P_MMPLL0, 4, 0, 0),
|
||||
{ }
|
||||
@ -447,7 +447,7 @@ static struct clk_rcg2 csi3_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
|
||||
static const struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
|
||||
F(37500000, P_GPLL0, 16, 0, 0),
|
||||
F(50000000, P_GPLL0, 12, 0, 0),
|
||||
F(60000000, P_GPLL0, 10, 0, 0),
|
||||
@ -490,7 +490,7 @@ static struct clk_rcg2 vfe1_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_mdp_clk[] = {
|
||||
static const struct freq_tbl ftbl_mdss_mdp_clk[] = {
|
||||
F(37500000, P_GPLL0, 16, 0, 0),
|
||||
F(60000000, P_GPLL0, 10, 0, 0),
|
||||
F(75000000, P_GPLL0, 8, 0, 0),
|
||||
@ -530,7 +530,7 @@ static struct clk_rcg2 gfx3d_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
|
||||
static const struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
|
||||
F(75000000, P_GPLL0, 8, 0, 0),
|
||||
F(133330000, P_GPLL0, 4.5, 0, 0),
|
||||
F(200000000, P_GPLL0, 3, 0, 0),
|
||||
@ -607,7 +607,7 @@ static struct clk_rcg2 pclk1_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
|
||||
static const struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
|
||||
F(50000000, P_GPLL0, 12, 0, 0),
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
F(133330000, P_GPLL0, 4.5, 0, 0),
|
||||
@ -631,7 +631,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_avsync_vp_clk[] = {
|
||||
static const struct freq_tbl ftbl_avsync_vp_clk[] = {
|
||||
F(150000000, P_GPLL0, 4, 0, 0),
|
||||
F(320000000, P_MMPLL0, 2.5, 0, 0),
|
||||
{ }
|
||||
@ -650,7 +650,7 @@ static struct clk_rcg2 vp_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
|
||||
static const struct freq_tbl ftbl_camss_cci_cci_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -669,7 +669,7 @@ static struct clk_rcg2 cci_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
|
||||
static const struct freq_tbl ftbl_camss_gp0_1_clk[] = {
|
||||
F(10000, P_XO, 16, 1, 120),
|
||||
F(24000, P_XO, 16, 1, 50),
|
||||
F(6000000, P_GPLL0, 10, 1, 10),
|
||||
@ -707,7 +707,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
|
||||
static const struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
|
||||
F(4800000, P_XO, 4, 0, 0),
|
||||
F(6000000, P_GPLL0, 10, 1, 10),
|
||||
F(8000000, P_GPLL0, 15, 1, 5),
|
||||
@ -777,7 +777,7 @@ static struct clk_rcg2 mclk3_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
|
||||
static const struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
F(200000000, P_MMPLL0, 4, 0, 0),
|
||||
{ }
|
||||
@ -822,7 +822,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
|
||||
static const struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
|
||||
F(133330000, P_GPLL0, 4.5, 0, 0),
|
||||
F(266670000, P_MMPLL0, 3, 0, 0),
|
||||
F(320000000, P_MMPLL0, 2.5, 0, 0),
|
||||
@ -871,7 +871,7 @@ static struct clk_rcg2 byte1_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
|
||||
static const struct freq_tbl ftbl_mdss_edpaux_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -889,7 +889,7 @@ static struct clk_rcg2 edpaux_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_edplink_clk[] = {
|
||||
static const struct freq_tbl ftbl_mdss_edplink_clk[] = {
|
||||
F(135000000, P_EDPLINK, 2, 0, 0),
|
||||
F(270000000, P_EDPLINK, 11, 0, 0),
|
||||
{ }
|
||||
@ -909,7 +909,7 @@ static struct clk_rcg2 edplink_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl edp_pixel_freq_tbl[] = {
|
||||
static const struct freq_tbl edp_pixel_freq_tbl[] = {
|
||||
{ .src = P_EDPVCO },
|
||||
{ }
|
||||
};
|
||||
@ -928,7 +928,7 @@ static struct clk_rcg2 edppixel_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
|
||||
static const struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -959,7 +959,7 @@ static struct clk_rcg2 esc1_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl extpclk_freq_tbl[] = {
|
||||
static const struct freq_tbl extpclk_freq_tbl[] = {
|
||||
{ .src = P_HDMIPLL },
|
||||
{ }
|
||||
};
|
||||
@ -978,7 +978,7 @@ static struct clk_rcg2 extpclk_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
|
||||
static const struct freq_tbl ftbl_mdss_hdmi_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -996,7 +996,7 @@ static struct clk_rcg2 hdmi_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_vsync_clk[] = {
|
||||
static const struct freq_tbl ftbl_mdss_vsync_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -1014,7 +1014,7 @@ static struct clk_rcg2 vsync_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
|
||||
static const struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
|
||||
F(50000000, P_GPLL0, 12, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -1032,7 +1032,7 @@ static struct clk_rcg2 rbcpr_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
|
||||
static const struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -1050,7 +1050,7 @@ static struct clk_rcg2 rbbmtimer_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_vpu_maple_clk[] = {
|
||||
static const struct freq_tbl ftbl_vpu_maple_clk[] = {
|
||||
F(50000000, P_GPLL0, 12, 0, 0),
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
F(133330000, P_GPLL0, 4.5, 0, 0),
|
||||
@ -1073,7 +1073,7 @@ static struct clk_rcg2 maple_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_vpu_vdp_clk[] = {
|
||||
static const struct freq_tbl ftbl_vpu_vdp_clk[] = {
|
||||
F(50000000, P_GPLL0, 12, 0, 0),
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
F(200000000, P_MMPLL0, 4, 0, 0),
|
||||
@ -1095,7 +1095,7 @@ static struct clk_rcg2 vdp_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_vpu_bus_clk[] = {
|
||||
static const struct freq_tbl ftbl_vpu_bus_clk[] = {
|
||||
F(40000000, P_GPLL0, 15, 0, 0),
|
||||
F(80000000, P_MMPLL0, 10, 0, 0),
|
||||
{ }
|
||||
|
||||
@ -155,7 +155,7 @@ static const struct clk_parent_data mmcc_pxo_dsi1_dsi2_byte[] = {
|
||||
{ .fw_name = "dsi2pllbyte", .name = "dsi2pllbyte" },
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_cam[] = {
|
||||
static const struct freq_tbl clk_tbl_cam[] = {
|
||||
{ 6000000, P_PLL8, 4, 1, 16 },
|
||||
{ 8000000, P_PLL8, 4, 1, 12 },
|
||||
{ 12000000, P_PLL8, 4, 1, 8 },
|
||||
@ -323,7 +323,7 @@ static struct clk_branch camclk2_clk = {
|
||||
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_csi[] = {
|
||||
static const struct freq_tbl clk_tbl_csi[] = {
|
||||
{ 27000000, P_PXO, 1, 0, 0 },
|
||||
{ 85330000, P_PLL8, 1, 2, 9 },
|
||||
{ 177780000, P_PLL2, 1, 2, 9 },
|
||||
@ -715,7 +715,7 @@ static struct clk_pix_rdi csi_rdi2_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_csiphytimer[] = {
|
||||
static const struct freq_tbl clk_tbl_csiphytimer[] = {
|
||||
{ 85330000, P_PLL8, 1, 2, 9 },
|
||||
{ 177780000, P_PLL2, 1, 2, 9 },
|
||||
{ }
|
||||
@ -808,7 +808,7 @@ static struct clk_branch csiphy2_timer_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_gfx2d[] = {
|
||||
static const struct freq_tbl clk_tbl_gfx2d[] = {
|
||||
F_MN( 27000000, P_PXO, 1, 0),
|
||||
F_MN( 48000000, P_PLL8, 1, 8),
|
||||
F_MN( 54857000, P_PLL8, 1, 7),
|
||||
@ -948,7 +948,7 @@ static struct clk_branch gfx2d1_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_gfx3d[] = {
|
||||
static const struct freq_tbl clk_tbl_gfx3d[] = {
|
||||
F_MN( 27000000, P_PXO, 1, 0),
|
||||
F_MN( 48000000, P_PLL8, 1, 8),
|
||||
F_MN( 54857000, P_PLL8, 1, 7),
|
||||
@ -968,7 +968,7 @@ static struct freq_tbl clk_tbl_gfx3d[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_gfx3d_8064[] = {
|
||||
static const struct freq_tbl clk_tbl_gfx3d_8064[] = {
|
||||
F_MN( 27000000, P_PXO, 0, 0),
|
||||
F_MN( 48000000, P_PLL8, 1, 8),
|
||||
F_MN( 54857000, P_PLL8, 1, 7),
|
||||
@ -1058,7 +1058,7 @@ static struct clk_branch gfx3d_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_vcap[] = {
|
||||
static const struct freq_tbl clk_tbl_vcap[] = {
|
||||
F_MN( 27000000, P_PXO, 0, 0),
|
||||
F_MN( 54860000, P_PLL8, 1, 7),
|
||||
F_MN( 64000000, P_PLL8, 1, 6),
|
||||
@ -1149,7 +1149,7 @@ static struct clk_branch vcap_npl_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_ijpeg[] = {
|
||||
static const struct freq_tbl clk_tbl_ijpeg[] = {
|
||||
{ 27000000, P_PXO, 1, 0, 0 },
|
||||
{ 36570000, P_PLL8, 1, 2, 21 },
|
||||
{ 54860000, P_PLL8, 7, 0, 0 },
|
||||
@ -1214,7 +1214,7 @@ static struct clk_branch ijpeg_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_jpegd[] = {
|
||||
static const struct freq_tbl clk_tbl_jpegd[] = {
|
||||
{ 64000000, P_PLL8, 6 },
|
||||
{ 76800000, P_PLL8, 5 },
|
||||
{ 96000000, P_PLL8, 4 },
|
||||
@ -1264,7 +1264,7 @@ static struct clk_branch jpegd_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_mdp[] = {
|
||||
static const struct freq_tbl clk_tbl_mdp[] = {
|
||||
{ 9600000, P_PLL8, 1, 1, 40 },
|
||||
{ 13710000, P_PLL8, 1, 1, 28 },
|
||||
{ 27000000, P_PXO, 1, 0, 0 },
|
||||
@ -1381,7 +1381,7 @@ static struct clk_branch mdp_vsync_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_rot[] = {
|
||||
static const struct freq_tbl clk_tbl_rot[] = {
|
||||
{ 27000000, P_PXO, 1 },
|
||||
{ 29540000, P_PLL8, 13 },
|
||||
{ 32000000, P_PLL8, 12 },
|
||||
@ -1461,7 +1461,7 @@ static const struct clk_parent_data mmcc_pxo_hdmi[] = {
|
||||
{ .fw_name = "hdmipll", .name = "hdmi_pll" },
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_tv[] = {
|
||||
static const struct freq_tbl clk_tbl_tv[] = {
|
||||
{ .src = P_HDMI_PLL, .pre_div = 1 },
|
||||
{ }
|
||||
};
|
||||
@ -1624,7 +1624,7 @@ static struct clk_branch hdmi_app_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_vcodec[] = {
|
||||
static const struct freq_tbl clk_tbl_vcodec[] = {
|
||||
F_MN( 27000000, P_PXO, 1, 0),
|
||||
F_MN( 32000000, P_PLL8, 1, 12),
|
||||
F_MN( 48000000, P_PLL8, 1, 8),
|
||||
@ -1699,7 +1699,7 @@ static struct clk_branch vcodec_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_vpe[] = {
|
||||
static const struct freq_tbl clk_tbl_vpe[] = {
|
||||
{ 27000000, P_PXO, 1 },
|
||||
{ 34909000, P_PLL8, 11 },
|
||||
{ 38400000, P_PLL8, 10 },
|
||||
@ -1752,7 +1752,7 @@ static struct clk_branch vpe_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_vfe[] = {
|
||||
static const struct freq_tbl clk_tbl_vfe[] = {
|
||||
{ 13960000, P_PLL8, 1, 2, 55 },
|
||||
{ 27000000, P_PXO, 1, 0, 0 },
|
||||
{ 36570000, P_PLL8, 1, 2, 21 },
|
||||
|
||||
@ -268,7 +268,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mmss_axi_clk_msm8226[] = {
|
||||
static const struct freq_tbl ftbl_mmss_axi_clk_msm8226[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(37500000, P_GPLL0, 16, 0, 0),
|
||||
F(50000000, P_GPLL0, 12, 0, 0),
|
||||
@ -280,7 +280,7 @@ static struct freq_tbl ftbl_mmss_axi_clk_msm8226[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mmss_axi_clk[] = {
|
||||
static const struct freq_tbl ftbl_mmss_axi_clk[] = {
|
||||
F( 19200000, P_XO, 1, 0, 0),
|
||||
F( 37500000, P_GPLL0, 16, 0, 0),
|
||||
F( 50000000, P_GPLL0, 12, 0, 0),
|
||||
@ -306,7 +306,7 @@ static struct clk_rcg2 mmss_axi_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_ocmemnoc_clk[] = {
|
||||
static const struct freq_tbl ftbl_ocmemnoc_clk[] = {
|
||||
F( 19200000, P_XO, 1, 0, 0),
|
||||
F( 37500000, P_GPLL0, 16, 0, 0),
|
||||
F( 50000000, P_GPLL0, 12, 0, 0),
|
||||
@ -331,7 +331,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
|
||||
static const struct freq_tbl ftbl_camss_csi0_3_clk[] = {
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
F(200000000, P_MMPLL0, 4, 0, 0),
|
||||
{ }
|
||||
@ -389,7 +389,7 @@ static struct clk_rcg2 csi3_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_vfe_vfe0_clk_msm8226[] = {
|
||||
static const struct freq_tbl ftbl_camss_vfe_vfe0_clk_msm8226[] = {
|
||||
F(37500000, P_GPLL0, 16, 0, 0),
|
||||
F(50000000, P_GPLL0, 12, 0, 0),
|
||||
F(60000000, P_GPLL0, 10, 0, 0),
|
||||
@ -406,7 +406,7 @@ static struct freq_tbl ftbl_camss_vfe_vfe0_clk_msm8226[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
|
||||
static const struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
|
||||
F(37500000, P_GPLL0, 16, 0, 0),
|
||||
F(50000000, P_GPLL0, 12, 0, 0),
|
||||
F(60000000, P_GPLL0, 10, 0, 0),
|
||||
@ -449,7 +449,7 @@ static struct clk_rcg2 vfe1_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_mdp_clk_msm8226[] = {
|
||||
static const struct freq_tbl ftbl_mdss_mdp_clk_msm8226[] = {
|
||||
F(37500000, P_GPLL0, 16, 0, 0),
|
||||
F(60000000, P_GPLL0, 10, 0, 0),
|
||||
F(75000000, P_GPLL0, 8, 0, 0),
|
||||
@ -461,7 +461,7 @@ static struct freq_tbl ftbl_mdss_mdp_clk_msm8226[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_mdp_clk[] = {
|
||||
static const struct freq_tbl ftbl_mdss_mdp_clk[] = {
|
||||
F(37500000, P_GPLL0, 16, 0, 0),
|
||||
F(60000000, P_GPLL0, 10, 0, 0),
|
||||
F(75000000, P_GPLL0, 8, 0, 0),
|
||||
@ -490,7 +490,7 @@ static struct clk_rcg2 mdp_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
|
||||
static const struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
|
||||
F(75000000, P_GPLL0, 8, 0, 0),
|
||||
F(133330000, P_GPLL0, 4.5, 0, 0),
|
||||
F(200000000, P_GPLL0, 3, 0, 0),
|
||||
@ -567,7 +567,7 @@ static struct clk_rcg2 pclk1_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_venus0_vcodec0_clk_msm8226[] = {
|
||||
static const struct freq_tbl ftbl_venus0_vcodec0_clk_msm8226[] = {
|
||||
F(66700000, P_GPLL0, 9, 0, 0),
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
F(133330000, P_MMPLL0, 6, 0, 0),
|
||||
@ -575,7 +575,7 @@ static struct freq_tbl ftbl_venus0_vcodec0_clk_msm8226[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
|
||||
static const struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
|
||||
F(50000000, P_GPLL0, 12, 0, 0),
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
F(133330000, P_MMPLL0, 6, 0, 0),
|
||||
@ -599,7 +599,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
|
||||
static const struct freq_tbl ftbl_camss_cci_cci_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -617,7 +617,7 @@ static struct clk_rcg2 cci_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
|
||||
static const struct freq_tbl ftbl_camss_gp0_1_clk[] = {
|
||||
F(10000, P_XO, 16, 1, 120),
|
||||
F(24000, P_XO, 16, 1, 50),
|
||||
F(6000000, P_GPLL0, 10, 1, 10),
|
||||
@ -655,14 +655,14 @@ static struct clk_rcg2 camss_gp1_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_mclk0_3_clk_msm8226[] = {
|
||||
static const struct freq_tbl ftbl_camss_mclk0_3_clk_msm8226[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(24000000, P_GPLL0, 5, 1, 5),
|
||||
F(66670000, P_GPLL0, 9, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
|
||||
static const struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
|
||||
F(4800000, P_XO, 4, 0, 0),
|
||||
F(6000000, P_GPLL0, 10, 1, 10),
|
||||
F(8000000, P_GPLL0, 15, 1, 5),
|
||||
@ -729,7 +729,7 @@ static struct clk_rcg2 mclk3_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
|
||||
static const struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
F(200000000, P_MMPLL0, 4, 0, 0),
|
||||
{ }
|
||||
@ -774,7 +774,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_vfe_cpp_clk_msm8226[] = {
|
||||
static const struct freq_tbl ftbl_camss_vfe_cpp_clk_msm8226[] = {
|
||||
F(133330000, P_GPLL0, 4.5, 0, 0),
|
||||
F(150000000, P_GPLL0, 4, 0, 0),
|
||||
F(266670000, P_MMPLL0, 3, 0, 0),
|
||||
@ -783,7 +783,7 @@ static struct freq_tbl ftbl_camss_vfe_cpp_clk_msm8226[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
|
||||
static const struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
|
||||
F(133330000, P_GPLL0, 4.5, 0, 0),
|
||||
F(266670000, P_MMPLL0, 3, 0, 0),
|
||||
F(320000000, P_MMPLL0, 2.5, 0, 0),
|
||||
@ -805,7 +805,7 @@ static struct clk_rcg2 cpp_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl byte_freq_tbl[] = {
|
||||
static const struct freq_tbl byte_freq_tbl[] = {
|
||||
{ .src = P_DSI0PLL_BYTE },
|
||||
{ }
|
||||
};
|
||||
@ -838,7 +838,7 @@ static struct clk_rcg2 byte1_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
|
||||
static const struct freq_tbl ftbl_mdss_edpaux_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -856,7 +856,7 @@ static struct clk_rcg2 edpaux_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_edplink_clk[] = {
|
||||
static const struct freq_tbl ftbl_mdss_edplink_clk[] = {
|
||||
F(135000000, P_EDPLINK, 2, 0, 0),
|
||||
F(270000000, P_EDPLINK, 11, 0, 0),
|
||||
{ }
|
||||
@ -876,7 +876,7 @@ static struct clk_rcg2 edplink_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl edp_pixel_freq_tbl[] = {
|
||||
static const struct freq_tbl edp_pixel_freq_tbl[] = {
|
||||
{ .src = P_EDPVCO },
|
||||
{ }
|
||||
};
|
||||
@ -895,7 +895,7 @@ static struct clk_rcg2 edppixel_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
|
||||
static const struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -926,7 +926,7 @@ static struct clk_rcg2 esc1_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl extpclk_freq_tbl[] = {
|
||||
static const struct freq_tbl extpclk_freq_tbl[] = {
|
||||
{ .src = P_HDMIPLL },
|
||||
{ }
|
||||
};
|
||||
@ -945,7 +945,7 @@ static struct clk_rcg2 extpclk_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
|
||||
static const struct freq_tbl ftbl_mdss_hdmi_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -963,7 +963,7 @@ static struct clk_rcg2 hdmi_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_vsync_clk[] = {
|
||||
static const struct freq_tbl ftbl_mdss_vsync_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
@ -974,7 +974,7 @@ static struct clk_rcg2 byte1_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
|
||||
static const struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -1005,7 +1005,7 @@ static struct clk_rcg2 esc1_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl extpclk_freq_tbl[] = {
|
||||
static const struct freq_tbl extpclk_freq_tbl[] = {
|
||||
{ .src = P_HDMIPLL },
|
||||
{ }
|
||||
};
|
||||
@ -1024,7 +1024,7 @@ static struct clk_rcg2 extpclk_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_hdmi_clk_src[] = {
|
||||
static const struct freq_tbl ftbl_hdmi_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -1042,7 +1042,7 @@ static struct clk_rcg2 hdmi_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_vsync_clk[] = {
|
||||
static const struct freq_tbl ftbl_mdss_vsync_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
@ -734,7 +734,7 @@ static struct clk_rcg2 mdp_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl extpclk_freq_tbl[] = {
|
||||
static const struct freq_tbl extpclk_freq_tbl[] = {
|
||||
{ .src = P_HDMIPLL },
|
||||
{ }
|
||||
};
|
||||
@ -753,7 +753,7 @@ static struct clk_rcg2 extpclk_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_vsync_clk[] = {
|
||||
static const struct freq_tbl ftbl_mdss_vsync_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -771,7 +771,7 @@ static struct clk_rcg2 vsync_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
|
||||
static const struct freq_tbl ftbl_mdss_hdmi_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
@ -815,7 +815,7 @@ static struct clk_rcg2 byte1_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
|
||||
static const struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
@ -449,7 +449,7 @@ static struct gdsc video_cc_mvs0_gdsc = {
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.parent = &video_cc_mvs0c_gdsc.pd,
|
||||
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
|
||||
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER,
|
||||
};
|
||||
|
||||
static struct gdsc video_cc_mvs1c_gdsc = {
|
||||
@ -474,7 +474,7 @@ static struct gdsc video_cc_mvs1_gdsc = {
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.parent = &video_cc_mvs1c_gdsc.pd,
|
||||
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
|
||||
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER,
|
||||
};
|
||||
|
||||
static struct clk_regmap *video_cc_sm8550_clocks[] = {
|
||||
|
||||
@ -100,6 +100,13 @@ config CLK_RK3568
|
||||
help
|
||||
Build the driver for RK3568 Clock Driver.
|
||||
|
||||
config CLK_RK3576
|
||||
bool "Rockchip RK3576 clock controller support"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3576 Clock Driver.
|
||||
|
||||
config CLK_RK3588
|
||||
bool "Rockchip RK3588 clock controller support"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
|
||||
@ -28,4 +28,5 @@ obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
|
||||
obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
|
||||
obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
|
||||
obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
|
||||
obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o
|
||||
obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o
|
||||
|
||||
@ -914,7 +914,10 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned
|
||||
}
|
||||
rate64 = rate64 >> cur.s;
|
||||
|
||||
return (unsigned long)rate64;
|
||||
if (pll->type == pll_rk3588_ddr)
|
||||
return (unsigned long)rate64 * 2;
|
||||
else
|
||||
return (unsigned long)rate64;
|
||||
}
|
||||
|
||||
static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
|
||||
@ -1167,6 +1170,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
|
||||
break;
|
||||
case pll_rk3588:
|
||||
case pll_rk3588_core:
|
||||
case pll_rk3588_ddr:
|
||||
if (!pll->rate_table)
|
||||
init.ops = &rockchip_rk3588_pll_clk_norate_ops;
|
||||
else
|
||||
|
||||
@ -1002,6 +1002,7 @@ static const char *const px30_cru_critical_clocks[] __initconst = {
|
||||
static void __init px30_clk_init(struct device_node *np)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
unsigned long clk_nr_clks;
|
||||
void __iomem *reg_base;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
@ -1010,7 +1011,9 @@ static void __init px30_clk_init(struct device_node *np)
|
||||
return;
|
||||
}
|
||||
|
||||
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
clk_nr_clks = rockchip_clk_find_max_clk_id(px30_clk_branches,
|
||||
ARRAY_SIZE(px30_clk_branches)) + 1;
|
||||
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
|
||||
if (IS_ERR(ctx)) {
|
||||
pr_err("%s: rockchip clk init failed\n", __func__);
|
||||
iounmap(reg_base);
|
||||
@ -1043,6 +1046,7 @@ CLK_OF_DECLARE(px30_cru, "rockchip,px30-cru", px30_clk_init);
|
||||
static void __init px30_pmu_clk_init(struct device_node *np)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
unsigned long clkpmu_nr_clks;
|
||||
void __iomem *reg_base;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
@ -1051,7 +1055,9 @@ static void __init px30_pmu_clk_init(struct device_node *np)
|
||||
return;
|
||||
}
|
||||
|
||||
ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
|
||||
clkpmu_nr_clks = rockchip_clk_find_max_clk_id(px30_clk_pmu_branches,
|
||||
ARRAY_SIZE(px30_clk_pmu_branches)) + 1;
|
||||
ctx = rockchip_clk_init(np, reg_base, clkpmu_nr_clks);
|
||||
if (IS_ERR(ctx)) {
|
||||
pr_err("%s: rockchip pmu clk init failed\n", __func__);
|
||||
return;
|
||||
|
||||
@ -436,6 +436,7 @@ static const char *const rk3036_critical_clocks[] __initconst = {
|
||||
static void __init rk3036_clk_init(struct device_node *np)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
unsigned long clk_nr_clks;
|
||||
void __iomem *reg_base;
|
||||
struct clk *clk;
|
||||
|
||||
@ -452,7 +453,9 @@ static void __init rk3036_clk_init(struct device_node *np)
|
||||
writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10),
|
||||
reg_base + RK2928_CLKSEL_CON(13));
|
||||
|
||||
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3036_clk_branches,
|
||||
ARRAY_SIZE(rk3036_clk_branches)) + 1;
|
||||
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
|
||||
if (IS_ERR(ctx)) {
|
||||
pr_err("%s: rockchip clk init failed\n", __func__);
|
||||
iounmap(reg_base);
|
||||
|
||||
@ -409,7 +409,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
|
||||
DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
|
||||
RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
|
||||
MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0,
|
||||
MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
|
||||
|
||||
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
|
||||
@ -683,6 +683,7 @@ static const char *const rk3228_critical_clocks[] __initconst = {
|
||||
static void __init rk3228_clk_init(struct device_node *np)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
unsigned long clk_nr_clks;
|
||||
void __iomem *reg_base;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
@ -691,7 +692,9 @@ static void __init rk3228_clk_init(struct device_node *np)
|
||||
return;
|
||||
}
|
||||
|
||||
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3228_clk_branches,
|
||||
ARRAY_SIZE(rk3228_clk_branches)) + 1;
|
||||
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
|
||||
if (IS_ERR(ctx)) {
|
||||
pr_err("%s: rockchip clk init failed\n", __func__);
|
||||
iounmap(reg_base);
|
||||
|
||||
@ -932,6 +932,7 @@ static void __init rk3288_common_init(struct device_node *np,
|
||||
enum rk3288_variant soc)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
unsigned long clk_nr_clks;
|
||||
|
||||
rk3288_cru_base = of_iomap(np, 0);
|
||||
if (!rk3288_cru_base) {
|
||||
@ -939,7 +940,9 @@ static void __init rk3288_common_init(struct device_node *np,
|
||||
return;
|
||||
}
|
||||
|
||||
ctx = rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);
|
||||
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3288_clk_branches,
|
||||
ARRAY_SIZE(rk3288_clk_branches)) + 1;
|
||||
ctx = rockchip_clk_init(np, rk3288_cru_base, clk_nr_clks);
|
||||
if (IS_ERR(ctx)) {
|
||||
pr_err("%s: rockchip clk init failed\n", __func__);
|
||||
iounmap(rk3288_cru_base);
|
||||
|
||||
@ -917,6 +917,7 @@ static const char *const rk3308_critical_clocks[] __initconst = {
|
||||
static void __init rk3308_clk_init(struct device_node *np)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
unsigned long clk_nr_clks;
|
||||
void __iomem *reg_base;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
@ -925,7 +926,9 @@ static void __init rk3308_clk_init(struct device_node *np)
|
||||
return;
|
||||
}
|
||||
|
||||
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3308_clk_branches,
|
||||
ARRAY_SIZE(rk3308_clk_branches)) + 1;
|
||||
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
|
||||
if (IS_ERR(ctx)) {
|
||||
pr_err("%s: rockchip clk init failed\n", __func__);
|
||||
iounmap(reg_base);
|
||||
|
||||
@ -881,6 +881,7 @@ static const char *const rk3328_critical_clocks[] __initconst = {
|
||||
static void __init rk3328_clk_init(struct device_node *np)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
unsigned long clk_nr_clks;
|
||||
void __iomem *reg_base;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
@ -889,7 +890,9 @@ static void __init rk3328_clk_init(struct device_node *np)
|
||||
return;
|
||||
}
|
||||
|
||||
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3328_clk_branches,
|
||||
ARRAY_SIZE(rk3328_clk_branches)) + 1;
|
||||
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
|
||||
if (IS_ERR(ctx)) {
|
||||
pr_err("%s: rockchip clk init failed\n", __func__);
|
||||
iounmap(reg_base);
|
||||
|
||||
@ -866,6 +866,7 @@ static const char *const rk3368_critical_clocks[] __initconst = {
|
||||
static void __init rk3368_clk_init(struct device_node *np)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
unsigned long clk_nr_clks;
|
||||
void __iomem *reg_base;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
@ -874,7 +875,9 @@ static void __init rk3368_clk_init(struct device_node *np)
|
||||
return;
|
||||
}
|
||||
|
||||
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3368_clk_branches,
|
||||
ARRAY_SIZE(rk3368_clk_branches)) + 1;
|
||||
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
|
||||
if (IS_ERR(ctx)) {
|
||||
pr_err("%s: rockchip clk init failed\n", __func__);
|
||||
iounmap(reg_base);
|
||||
|
||||
@ -1531,6 +1531,7 @@ static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
|
||||
static void __init rk3399_clk_init(struct device_node *np)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
unsigned long clk_nr_clks;
|
||||
void __iomem *reg_base;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
@ -1539,7 +1540,9 @@ static void __init rk3399_clk_init(struct device_node *np)
|
||||
return;
|
||||
}
|
||||
|
||||
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3399_clk_branches,
|
||||
ARRAY_SIZE(rk3399_clk_branches)) + 1;
|
||||
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
|
||||
if (IS_ERR(ctx)) {
|
||||
pr_err("%s: rockchip clk init failed\n", __func__);
|
||||
iounmap(reg_base);
|
||||
@ -1577,6 +1580,7 @@ CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
|
||||
static void __init rk3399_pmu_clk_init(struct device_node *np)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
unsigned long clkpmu_nr_clks;
|
||||
void __iomem *reg_base;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
@ -1585,7 +1589,9 @@ static void __init rk3399_pmu_clk_init(struct device_node *np)
|
||||
return;
|
||||
}
|
||||
|
||||
ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
|
||||
clkpmu_nr_clks = rockchip_clk_find_max_clk_id(rk3399_clk_pmu_branches,
|
||||
ARRAY_SIZE(rk3399_clk_pmu_branches)) + 1;
|
||||
ctx = rockchip_clk_init(np, reg_base, clkpmu_nr_clks);
|
||||
if (IS_ERR(ctx)) {
|
||||
pr_err("%s: rockchip pmu clk init failed\n", __func__);
|
||||
iounmap(reg_base);
|
||||
|
||||
1818
drivers/clk/rockchip/clk-rk3576.c
Normal file
1818
drivers/clk/rockchip/clk-rk3576.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -526,7 +526,7 @@ PNAME(pmu_200m_100m_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src" };
|
||||
PNAME(pmu_300m_24m_p) = { "clk_300m_src", "xin24m" };
|
||||
PNAME(pmu_400m_24m_p) = { "clk_400m_src", "xin24m" };
|
||||
PNAME(pmu_100m_50m_24m_src_p) = { "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" };
|
||||
PNAME(pmu_24m_32k_100m_src_p) = { "xin24m", "32k", "clk_pmu1_100m_src" };
|
||||
PNAME(pmu_24m_32k_100m_src_p) = { "xin24m", "xin32k", "clk_pmu1_100m_src" };
|
||||
PNAME(hclk_pmu1_root_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" };
|
||||
PNAME(hclk_pmu_cm0_root_p) = { "clk_pmu1_400m_src", "clk_pmu1_200m_src", "clk_pmu1_100m_src", "xin24m" };
|
||||
PNAME(mclk_pdm0_p) = { "clk_pmu1_300m_src", "clk_pmu1_200m_src" };
|
||||
@ -2502,43 +2502,3 @@ static void __init rk3588_clk_init(struct device_node *np)
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init);
|
||||
|
||||
struct clk_rk3588_inits {
|
||||
void (*inits)(struct device_node *np);
|
||||
};
|
||||
|
||||
static const struct clk_rk3588_inits clk_3588_cru_init = {
|
||||
.inits = rk3588_clk_init,
|
||||
};
|
||||
|
||||
static const struct of_device_id clk_rk3588_match_table[] = {
|
||||
{
|
||||
.compatible = "rockchip,rk3588-cru",
|
||||
.data = &clk_3588_cru_init,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static int __init clk_rk3588_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct clk_rk3588_inits *init_data;
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
init_data = device_get_match_data(dev);
|
||||
if (!init_data)
|
||||
return -EINVAL;
|
||||
|
||||
if (init_data->inits)
|
||||
init_data->inits(dev->of_node);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_rk3588_driver = {
|
||||
.driver = {
|
||||
.name = "clk-rk3588",
|
||||
.of_match_table = clk_rk3588_match_table,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver_probe(clk_rk3588_driver, clk_rk3588_probe);
|
||||
|
||||
@ -450,12 +450,13 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
|
||||
struct rockchip_clk_branch *list,
|
||||
unsigned int nr_clk)
|
||||
{
|
||||
struct clk *clk = NULL;
|
||||
struct clk *clk;
|
||||
unsigned int idx;
|
||||
unsigned long flags;
|
||||
|
||||
for (idx = 0; idx < nr_clk; idx++, list++) {
|
||||
flags = list->flags;
|
||||
clk = NULL;
|
||||
|
||||
/* catch simple muxes */
|
||||
switch (list->branch_type) {
|
||||
|
||||
@ -235,6 +235,58 @@ struct clk;
|
||||
#define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
|
||||
#define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
|
||||
|
||||
#define RK3576_PHP_CRU_BASE 0x8000
|
||||
#define RK3576_SECURE_NS_CRU_BASE 0x10000
|
||||
#define RK3576_PMU_CRU_BASE 0x20000
|
||||
#define RK3576_BIGCORE_CRU_BASE 0x38000
|
||||
#define RK3576_LITCORE_CRU_BASE 0x40000
|
||||
#define RK3576_CCI_CRU_BASE 0x48000
|
||||
|
||||
#define RK3576_PLL_CON(x) RK2928_PLL_CON(x)
|
||||
#define RK3576_MODE_CON0 0x280
|
||||
#define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280)
|
||||
#define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280)
|
||||
#define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280)
|
||||
#define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
|
||||
#define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
|
||||
#define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
|
||||
#define RK3576_GLB_CNT_TH 0xc00
|
||||
#define RK3576_GLB_SRST_FST 0xc08
|
||||
#define RK3576_GLB_SRST_SND 0xc0c
|
||||
#define RK3576_GLB_RST_CON 0xc10
|
||||
#define RK3576_GLB_RST_ST 0xc04
|
||||
#define RK3576_SDIO_CON0 0xC24
|
||||
#define RK3576_SDIO_CON1 0xC28
|
||||
#define RK3576_SDMMC_CON0 0xC30
|
||||
#define RK3576_SDMMC_CON1 0xC34
|
||||
|
||||
#define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300)
|
||||
#define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800)
|
||||
#define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00)
|
||||
|
||||
#define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE)
|
||||
#define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300)
|
||||
#define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800)
|
||||
#define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00)
|
||||
|
||||
#define RK3576_SECURE_NS_CLKSEL_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x300)
|
||||
#define RK3576_SECURE_NS_CLKGATE_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x800)
|
||||
#define RK3576_SECURE_NS_SOFTRST_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0xa00)
|
||||
|
||||
#define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300)
|
||||
#define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800)
|
||||
#define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00)
|
||||
|
||||
#define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE)
|
||||
#define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300)
|
||||
#define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800)
|
||||
#define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00)
|
||||
#define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE)
|
||||
#define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300)
|
||||
#define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800)
|
||||
#define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00)
|
||||
#define RK3576_NON_SECURE_GATING_CON00 0xc48
|
||||
|
||||
#define RK3588_PHP_CRU_BASE 0x8000
|
||||
#define RK3588_PMU_CRU_BASE 0x30000
|
||||
#define RK3588_BIGCORE0_CRU_BASE 0x50000
|
||||
@ -287,6 +339,7 @@ enum rockchip_pll_type {
|
||||
pll_rk3399,
|
||||
pll_rk3588,
|
||||
pll_rk3588_core,
|
||||
pll_rk3588_ddr,
|
||||
};
|
||||
|
||||
#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
|
||||
@ -1025,6 +1078,7 @@ static inline void rockchip_register_softrst(struct device_node *np,
|
||||
return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags);
|
||||
}
|
||||
|
||||
void rk3576_rst_init(struct device_node *np, void __iomem *reg_base);
|
||||
void rk3588_rst_init(struct device_node *np, void __iomem *reg_base);
|
||||
|
||||
#endif
|
||||
|
||||
651
drivers/clk/rockchip/rst-rk3576.c
Normal file
651
drivers/clk/rockchip/rst-rk3576.c
Normal file
@ -0,0 +1,651 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
* Copyright (c) 2024 Collabora Ltd.
|
||||
* Author: Detlev Casanova <detlev.casanova@collabora.com>
|
||||
* Based on Sebastien Reichel's implementation for RK3588
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <dt-bindings/reset/rockchip,rk3576-cru.h>
|
||||
#include "clk.h"
|
||||
|
||||
/* 0x27200000 + 0x0A00 */
|
||||
#define RK3576_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
|
||||
/* 0x27208000 + 0x0A00 */
|
||||
#define RK3576_PHPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit)
|
||||
/* 0x27210000 + 0x0A00 */
|
||||
#define RK3576_SECURENSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit)
|
||||
/* 0x27220000 + 0x0A00 */
|
||||
#define RK3576_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit)
|
||||
|
||||
/* mapping table for reset ID to register offset */
|
||||
static const int rk3576_register_offset[] = {
|
||||
/* SOFTRST_CON01 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_TOP_MID_BIU, 1, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_SECURE_HIGH_BIU, 1, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_TOP_BIU, 1, 14),
|
||||
|
||||
/* SOFTRST_CON02 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_VO0VOP_CHANNEL_BIU, 2, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_VO0VOP_CHANNEL_BIU, 2, 1),
|
||||
|
||||
/* SOFTRST_CON06 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_BISRINTF, 6, 2),
|
||||
|
||||
/* SOFTRST_CON07 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_1, 7, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_0, 7, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_1, 7, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_0, 7, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_1, 7, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_1, 7, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SAI0_8CH, 7, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SAI0_8CH, 7, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX0, 7, 14),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX0, 7, 15),
|
||||
|
||||
/* SOFTRST_CON08 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX1, 8, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX1, 8, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SAI1_8CH, 8, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SAI1_8CH, 8, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SAI2_2CH, 8, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SAI2_2CH, 8, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SAI3_2CH, 8, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SAI3_2CH, 8, 14),
|
||||
|
||||
/* SOFTRST_CON09 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_PDM1, 9, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX0, 9, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX0, 9, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12),
|
||||
|
||||
/* SOFTRST_CON11 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 11, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 11, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_CRU, 11, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_CAN0, 11, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_CAN0, 11, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_CAN1, 11, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2BUS, 11, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_VCCIO_IOC, 11, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 11, 14),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_KEY_SHIFT, 11, 15),
|
||||
|
||||
/* SOFTRST_CON12 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_I2C3, 12, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_I2C4, 12, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_I2C5, 12, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_I2C6, 12, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_I2C7, 12, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_I2C8, 12, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_I2C9, 12, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_WDT_BUSMCU, 12, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_T_WDT_BUSMCU, 12, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_GIC, 12, 11),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_I2C1, 12, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_I2C2, 12, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_I2C3, 12, 14),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_I2C4, 12, 15),
|
||||
|
||||
/* SOFTRST_CON13 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_I2C5, 13, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_I2C6, 13, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_I2C7, 13, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_I2C8, 13, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_I2C9, 13, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_SARADC, 13, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_SARADC, 13, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_TSADC, 13, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_TSADC, 13, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_UART0, 13, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_UART2, 13, 11),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_UART3, 13, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_UART4, 13, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_UART5, 13, 14),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_UART6, 13, 15),
|
||||
|
||||
/* SOFTRST_CON14 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_UART7, 14, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_UART8, 14, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_UART9, 14, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_UART10, 14, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_UART11, 14, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_S_UART0, 14, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_S_UART2, 14, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_S_UART4, 14, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_S_UART5, 14, 15),
|
||||
|
||||
/* SOFTRST_CON15 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_S_UART6, 15, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_S_UART7, 15, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_S_UART8, 15, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_S_UART9, 15, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_S_UART10, 15, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_S_UART11, 15, 11),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_SPI0, 15, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_SPI1, 15, 14),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_SPI2, 15, 15),
|
||||
|
||||
/* SOFTRST_CON16 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_SPI3, 16, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_SPI4, 16, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_SPI0, 16, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_SPI1, 16, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_SPI2, 16, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_SPI3, 16, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_SPI4, 16, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_WDT0, 16, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_T_WDT0, 16, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 16, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_PWM1, 16, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_PWM1, 16, 11),
|
||||
|
||||
/* SOFTRST_CON17 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 17, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 17, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_TIMER0, 17, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_TIMER1, 17, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_TIMER2, 17, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_TIMER3, 17, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_TIMER4, 17, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_TIMER5, 17, 11),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_BUSIOC, 17, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 17, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_GPIO1, 17, 15),
|
||||
|
||||
/* SOFTRST_CON18 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_GPIO1, 18, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_GPIO2, 18, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_GPIO2, 18, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_GPIO3, 18, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_GPIO3, 18, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_GPIO4, 18, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_GPIO4, 18, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DECOM, 18, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_DECOM, 18, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_D_DECOM, 18, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_TIMER6, 18, 11),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_TIMER7, 18, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_TIMER8, 18, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_TIMER9, 18, 14),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_TIMER10, 18, 15),
|
||||
|
||||
/* SOFTRST_CON19 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_TIMER11, 19, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DMAC0, 19, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DMAC1, 19, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DMAC2, 19, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 19, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_BUS, 19, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_I3C0, 19, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_I3C1, 19, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_BUS_CM0_BIU, 19, 11),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_F_BUS_CM0_CORE, 19, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_T_BUS_CM0_JTAG, 19, 13),
|
||||
|
||||
/* SOFTRST_CON20 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2PMU, 20, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2DDR, 20, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_BUS, 20, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_PWM2, 20, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_PWM2, 20, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_FREQ_PWM1, 20, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_COUNTER_PWM1, 20, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_I3C0, 20, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_I3C1, 20, 13),
|
||||
|
||||
/* SOFTRST_CON21 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 21, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 21, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 21, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 21, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 21, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_DFI_CH0, 21, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 21, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH0, 21, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 21, 14),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH1, 21, 15),
|
||||
|
||||
/* SOFTRST_CON22 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 22, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 22, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_DFI_CH1, 22, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 22, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 22, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH0, 22, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH1, 22, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_AHB2APB, 22, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_AHB2APB, 22, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_DDR_BIU, 22, 14),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 22, 15),
|
||||
|
||||
/* SOFTRST_CON23 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 23, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 23, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 23, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 23, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 23, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_WDT, 23, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_TIMER, 23, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 23, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 23, 11),
|
||||
|
||||
/* SOFTRST_CON25 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 25, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH0, 25, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH0, 25, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH0, 25, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH0, 25, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH0, 25, 6),
|
||||
|
||||
/* SOFTRST_CON26 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 26, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH1, 26, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH1, 26, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH1, 26, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH1, 26, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH1, 26, 6),
|
||||
|
||||
/* SOFTRST_CON27 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_DDR, 27, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_DDR, 27, 1),
|
||||
|
||||
/* SOFTRST_CON28 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0, 28, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 28, 11),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_L_RKNN0_BIU, 28, 12),
|
||||
|
||||
/* SOFTRST_CON29 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1, 29, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 29, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_L_RKNN1_BIU, 29, 3),
|
||||
|
||||
/* SOFTRST_CON31 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_NPU_DAP, 31, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_L_NPUSUBSYS_BIU, 31, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 31, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 31, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER0, 31, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER1, 31, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 31, 14),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 31, 15),
|
||||
|
||||
/* SOFTRST_CON32 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_RKNN_CBUF, 32, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_RVCORE0, 32, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 32, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_NPU, 32, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 32, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 32, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 32, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 32, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_RKNNTOP_BIU, 32, 11),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_RKNN_CBUF, 32, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_RKNNTOP_BIU, 32, 13),
|
||||
|
||||
/* SOFTRST_CON33 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 33, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 33, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_S_FSPI, 33, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_FSPI, 33, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_C_EMMC, 33, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_EMMC, 33, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_EMMC, 33, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_B_EMMC, 33, 11),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_T_EMMC, 33, 12),
|
||||
|
||||
/* SOFTRST_CON34 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_GRF, 34, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 34, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 34, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_PCIE0, 34, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 34, 15),
|
||||
|
||||
/* SOFTRST_CON35 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 35, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_MMU0, 35, 11),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU0, 35, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_MMU1, 35, 14),
|
||||
|
||||
/* SOFTRST_CON36 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU1, 36, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_PCIE1, 36, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 36, 9),
|
||||
|
||||
/* SOFTRST_CON37 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_ASIC1, 37, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_ASIC0, 37, 7),
|
||||
|
||||
/* SOFTRST_CON40 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_CSIDPHY1, 40, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_SCAN_CSIDPHY1, 40, 3),
|
||||
|
||||
/* SOFTRST_CON42 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_GRF, 42, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_BIU, 42, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_SDGMAC_BIU, 42, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SDGMAC_BIU, 42, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_GMAC0, 42, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_GMAC1, 42, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_GMAC0, 42, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_GMAC1, 42, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SDIO, 42, 12),
|
||||
|
||||
/* SOFTRST_CON43 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SDMMC0, 43, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_S_FSPI1, 43, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_FSPI1, 43, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DSMC_BIU, 43, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DSMC, 43, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_DSMC, 43, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_HSGPIO, 43, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_HSGPIO, 43, 11),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_HSGPIO, 43, 13),
|
||||
|
||||
/* SOFTRST_CON45 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC, 45, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 45, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 45, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 45, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_CORE, 45, 9),
|
||||
|
||||
/* SOFTRST_CON47 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_USB_BIU, 47, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_BIU, 47, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 47, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_UFS_BIU, 47, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_MMU2, 47, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU2, 47, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_UFS_SYS, 47, 15),
|
||||
|
||||
/* SOFTRST_CON48 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_UFS, 48, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_GRF, 48, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_UFS_GRF, 48, 2),
|
||||
|
||||
/* SOFTRST_CON49 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 49, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 49, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_RGA_BIU, 49, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_VDPP_BIU, 49, 11),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_EBC_BIU, 49, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_0, 49, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_0, 49, 14),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_0, 49, 15),
|
||||
|
||||
/* SOFTRST_CON50 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_JPEG, 50, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_JPEG, 50, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_VDPP, 50, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_VDPP, 50, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_CORE_VDPP, 50, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_1, 50, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_1, 50, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_1, 50, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_EBC, 50, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_EBC, 50, 11),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_D_EBC, 50, 12),
|
||||
|
||||
/* SOFTRST_CON51 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0_BIU, 51, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0_BIU, 51, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0, 51, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0, 51, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_VEPU0_CORE, 51, 6),
|
||||
|
||||
/* SOFTRST_CON53 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_VI_BIU, 53, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_VI_BIU, 53, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_VI_BIU, 53, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_D_VICAP, 53, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_VICAP, 53, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_VICAP, 53, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_ISP0, 53, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 53, 11),
|
||||
|
||||
/* SOFTRST_CON54 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_CORE_VPSS, 54, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 54, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 54, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 54, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 54, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 54, 8),
|
||||
|
||||
/* SOFTRST_CON59 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_CIFIN, 59, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_VICAP_I0CLK, 59, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_VICAP_I1CLK, 59, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_VICAP_I2CLK, 59, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_VICAP_I3CLK, 59, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_VICAP_I4CLK, 59, 5),
|
||||
|
||||
/* SOFTRST_CON61 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 61, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_VOP2_BIU, 61, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 61, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 61, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_VOP, 61, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_VOP, 61, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_D_VP0, 61, 13),
|
||||
|
||||
/* SOFTRST_CON62 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_D_VP1, 62, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_D_VP2, 62, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_VOP2_BIU, 62, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_VOPGRF, 62, 3),
|
||||
|
||||
/* SOFTRST_CON63 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 63, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 63, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 63, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_VO0_GRF, 63, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0, 63, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_HDCP0, 63, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_HDCP0, 63, 14),
|
||||
|
||||
/* SOFTRST_CON64 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 64, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_DSIHOST0, 64, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_HDMITX0, 64, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 64, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_EDP0, 64, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_EDP0_24M, 64, 14),
|
||||
|
||||
/* SOFTRST_CON65 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SAI5_8CH, 65, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SAI5_8CH, 65, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SAI6_8CH, 65, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SAI6_8CH, 65, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX2, 65, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX2, 65, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX2, 65, 14),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX2, 65, 15),
|
||||
|
||||
/* SOFTRST_CON66 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SAI8_8CH, 66, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SAI8_8CH, 66, 2),
|
||||
|
||||
/* SOFTRST_CON67 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_VO1_BIU, 67, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_VO1_BIU, 67, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SAI7_8CH, 67, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SAI7_8CH, 67, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX3, 67, 11),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX4, 67, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX5, 67, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX3, 67, 14),
|
||||
|
||||
/* SOFTRST_CON68 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_DP0, 68, 0),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_VO1_GRF, 68, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 68, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1, 68, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_HDCP1, 68, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_HDCP1, 68, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_SAI9_8CH, 68, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SAI9_8CH, 68, 11),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX4, 68, 12),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX5, 68, 13),
|
||||
|
||||
/* SOFTRST_CON69 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_GPU, 69, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 69, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 69, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 69, 13),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 69, 14),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_GPU, 69, 15),
|
||||
|
||||
/* SOFTRST_CON72 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_CENTER_BIU, 72, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 72, 5),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 72, 6),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 72, 7),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 72, 8),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 72, 9),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 72, 10),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 72, 11),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 72, 12),
|
||||
|
||||
/* SOFTRST_CON75 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 75, 1),
|
||||
|
||||
/* SOFTRST_CON78 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_DP0_PIXELCLK, 78, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_PHY_DP0_TX, 78, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_DP1_PIXELCLK, 78, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_DP2_PIXELCLK, 78, 4),
|
||||
|
||||
/* SOFTRST_CON79 */
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1_BIU, 79, 1),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1_BIU, 79, 2),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1, 79, 3),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1, 79, 4),
|
||||
RK3576_CRU_RESET_OFFSET(SRST_VEPU1_CORE, 79, 5),
|
||||
|
||||
/* PPLL_SOFTRST_CON00 */
|
||||
RK3576_PHPCRU_RESET_OFFSET(SRST_P_PHPPHY_CRU, 0, 1),
|
||||
RK3576_PHPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 3),
|
||||
RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0, 0, 5),
|
||||
RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0_GRF, 0, 6),
|
||||
RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1, 0, 7),
|
||||
RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1_GRF, 0, 8),
|
||||
|
||||
/* PPLL_SOFTRST_CON01 */
|
||||
RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE0_PIPE_PHY, 1, 5),
|
||||
RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE1_PIPE_PHY, 1, 8),
|
||||
|
||||
/* SECURENS_SOFTRST_CON00 */
|
||||
RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_CRYPTO_NS, 0, 3),
|
||||
RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_TRNG_NS, 0, 4),
|
||||
RK3576_SECURENSCRU_RESET_OFFSET(SRST_P_OTPC_NS, 0, 8),
|
||||
RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9),
|
||||
|
||||
/* PMU1_SOFTRST_CON00 */
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_GRF, 0, 0),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_APB, 0, 1),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY, 0, 2),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_DCPHY_GRF, 0, 3),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT0_APB2ASB, 0, 4),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT1_APB2ASB, 0, 5),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_USB2DEBUG, 0, 6),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY_GRF, 0, 7),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY, 0, 8),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_1, 0, 10),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDP_GRF, 0, 11),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDPPHY, 0, 12),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_INIT, 0, 15),
|
||||
|
||||
/* PMU1_SOFTRST_CON01 */
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_CMN, 1, 0),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_LANE, 1, 1),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_PCS, 1, 2),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY, 1, 3),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY, 1, 4),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_SCAN_CSIPHY, 1, 5),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO6_IOC, 1, 6),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_0, 1, 7),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_1, 1, 8),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_CMN, 1, 10),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_LANE, 1, 11),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_HDMITXHDP, 1, 13),
|
||||
|
||||
/* PMU1_SOFTRST_CON02 */
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_MPHY_INIT, 2, 0),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MPHY_GRF, 2, 1),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO7_IOC, 2, 3),
|
||||
|
||||
/* PMU1_SOFTRST_CON03 */
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_NIU, 3, 10),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 3, 11),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_CORE, 3, 12),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_JTAG, 3, 13),
|
||||
|
||||
/* PMU1_SOFTRST_CON04 */
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 4, 1),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 4, 3),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 4, 4),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 4, 5),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 4, 6),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMUTIMER, 4, 7),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER1, 4, 10),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 4, 11),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 4, 12),
|
||||
|
||||
/* PMU1_SOFTRST_CON05 */
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 5, 1),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_I2C0, 5, 2),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_S_UART1, 5, 5),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_UART1, 5, 6),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_PDM0, 5, 13),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 5, 15),
|
||||
|
||||
/* PMU1_SOFTRST_CON06 */
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_M_PDM0, 6, 0),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 6, 1),
|
||||
|
||||
/* PMU1_SOFTRST_CON07 */
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 7, 4),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 7, 5),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 7, 6),
|
||||
RK3576_PMU1CRU_RESET_OFFSET(SRST_DB_GPIO0, 7, 7),
|
||||
};
|
||||
|
||||
void rk3576_rst_init(struct device_node *np, void __iomem *reg_base)
|
||||
{
|
||||
rockchip_register_softrst_lut(np,
|
||||
rk3576_register_offset,
|
||||
ARRAY_SIZE(rk3576_register_offset),
|
||||
reg_base + RK3576_SOFTRST_CON(0),
|
||||
ROCKCHIP_SOFTRST_HIWORD_MASK);
|
||||
}
|
||||
@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o
|
||||
obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o
|
||||
obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o
|
||||
|
||||
@ -17,10 +17,10 @@
|
||||
#include "clk-exynos-arm64.h"
|
||||
|
||||
/* NOTE: Must be equal to the last clock ID increased by one */
|
||||
#define CLKS_NR_TOP (CLK_GOUT_FSYS_USB30DRD + 1)
|
||||
#define CLKS_NR_TOP (CLK_MOUT_SHARED1_PLL + 1)
|
||||
#define CLKS_NR_CORE (CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1)
|
||||
#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
|
||||
#define CLKS_NR_FSYS (CLK_GOUT_MMC_SDIO_SDCLKIN + 1)
|
||||
#define CLKS_NR_FSYS (CLK_FSYS_USB30DRD_REF_CLK + 1)
|
||||
|
||||
/* ---- CMU_TOP ------------------------------------------------------------- */
|
||||
|
||||
@ -162,6 +162,10 @@ static const struct samsung_pll_clock top_pll_clks[] __initconst = {
|
||||
NULL),
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_TOP */
|
||||
PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
|
||||
PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
|
||||
PNAME(mout_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
|
||||
"dout_shared0_div3", "dout_shared0_div3" };
|
||||
@ -189,6 +193,12 @@ PNAME(mout_fsys_mmc_sdio_p) = { "dout_shared0_div2", "dout_shared1_div2" };
|
||||
PNAME(mout_fsys_usb30drd_p) = { "dout_shared0_div4", "dout_shared1_div4" };
|
||||
|
||||
static const struct samsung_mux_clock top_mux_clks[] __initconst = {
|
||||
/* TOP */
|
||||
MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
|
||||
PLL_CON0_PLL_SHARED0, 4, 1),
|
||||
MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
|
||||
PLL_CON0_PLL_SHARED1, 4, 1),
|
||||
|
||||
/* CORE */
|
||||
MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
|
||||
@ -232,17 +242,17 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
|
||||
|
||||
static const struct samsung_div_clock top_div_clks[] __initconst = {
|
||||
/* TOP */
|
||||
DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "fout_shared0_pll",
|
||||
DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
|
||||
CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
|
||||
DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll",
|
||||
DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
|
||||
CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
|
||||
DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
|
||||
CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
|
||||
DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll",
|
||||
DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "mout_shared0_pll",
|
||||
CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
|
||||
DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "fout_shared1_pll",
|
||||
DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
|
||||
DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll",
|
||||
DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
|
||||
DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
|
||||
@ -676,30 +686,56 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
|
||||
/* ---- CMU_FSYS ------------------------------------------------------------ */
|
||||
|
||||
/* Register Offset definitions for CMU_FSYS (0x13400000) */
|
||||
#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100
|
||||
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120
|
||||
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140
|
||||
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160
|
||||
#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180
|
||||
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030
|
||||
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034
|
||||
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038
|
||||
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c
|
||||
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040
|
||||
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044
|
||||
#define PLL_LOCKTIME_PLL_USB 0x0000
|
||||
#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100
|
||||
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120
|
||||
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140
|
||||
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160
|
||||
#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180
|
||||
#define PLL_CON0_PLL_USB 0x01a0
|
||||
#define CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE 0x200c
|
||||
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030
|
||||
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034
|
||||
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038
|
||||
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c
|
||||
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040
|
||||
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044
|
||||
#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL 0x2068
|
||||
#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0 0x206c
|
||||
#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1 0x2070
|
||||
#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY 0x2074
|
||||
#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK 0x2078
|
||||
|
||||
static const unsigned long fsys_clk_regs[] __initconst = {
|
||||
PLL_LOCKTIME_PLL_USB,
|
||||
PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER,
|
||||
PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,
|
||||
PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,
|
||||
PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
|
||||
PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
|
||||
PLL_CON0_PLL_USB,
|
||||
CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE,
|
||||
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK,
|
||||
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,
|
||||
CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK,
|
||||
CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,
|
||||
CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK,
|
||||
CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
|
||||
CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL,
|
||||
CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0,
|
||||
CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1,
|
||||
CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY,
|
||||
CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK,
|
||||
};
|
||||
|
||||
static const struct samsung_pll_rate_table pll_usb_rate_table[] __initconst = {
|
||||
PLL_35XX_RATE(26 * MHZ, 50000000U, 400, 13, 4),
|
||||
};
|
||||
|
||||
static const struct samsung_pll_clock fsys_pll_clks[] __initconst = {
|
||||
PLL(pll_1418x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_USB, PLL_CON0_PLL_USB,
|
||||
pll_usb_rate_table),
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_FSYS */
|
||||
@ -708,6 +744,7 @@ PNAME(mout_fsys_mmc_card_user_p) = { "oscclk", "dout_fsys_mmc_card" };
|
||||
PNAME(mout_fsys_mmc_embd_user_p) = { "oscclk", "dout_fsys_mmc_embd" };
|
||||
PNAME(mout_fsys_mmc_sdio_user_p) = { "oscclk", "dout_fsys_mmc_sdio" };
|
||||
PNAME(mout_fsys_usb30drd_user_p) = { "oscclk", "dout_fsys_usb30drd" };
|
||||
PNAME(mout_usb_pll_p) = { "oscclk", "fout_usb_pll" };
|
||||
|
||||
static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user", mout_fsys_bus_user_p,
|
||||
@ -721,12 +758,16 @@ static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
|
||||
MUX_F(CLK_MOUT_FSYS_MMC_SDIO_USER, "mout_fsys_mmc_sdio_user",
|
||||
mout_fsys_mmc_sdio_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
|
||||
4, 1, CLK_SET_RATE_PARENT, 0),
|
||||
MUX_F(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",
|
||||
MUX(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",
|
||||
mout_fsys_usb30drd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
|
||||
4, 1, CLK_SET_RATE_PARENT, 0),
|
||||
4, 1),
|
||||
nMUX_F(CLK_MOUT_USB_PLL, "mout_usb_pll", mout_usb_pll_p,
|
||||
PLL_CON0_PLL_USB, 4, 1, CLK_SET_RATE_PARENT, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
|
||||
GATE(CLK_FSYS_USB20PHY_CLKCORE, "clk_fsys_usb20phy_clkcore", "mout_usb_pll",
|
||||
CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE, 21, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_fsys_bus_user",
|
||||
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
|
||||
@ -742,9 +783,21 @@ static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
|
||||
GATE(CLK_GOUT_MMC_SDIO_SDCLKIN, "gout_mmc_sdio_sdclkin",
|
||||
"mout_fsys_mmc_sdio_user", CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
|
||||
21, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_FSYS_USB30DRD_ACLK_20PHYCTRL, "clk_fsys_usb30drd_aclk_20phyctrl",
|
||||
"mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL, 21, 0, 0),
|
||||
GATE(CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_0, "clk_fsys_usb30drd_aclk_30phyctrl_0",
|
||||
"mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0, 21, 0, 0),
|
||||
GATE(CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_1, "clk_fsys_usb30drd_aclk_30phyctrl_1",
|
||||
"mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1, 21, 0, 0),
|
||||
GATE(CLK_FSYS_USB30DRD_BUS_CLK_EARLY, "clk_fsys_usb30drd_bus_clk_early",
|
||||
"mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY, 21, 0, 0),
|
||||
GATE(CLK_FSYS_USB30DRD_REF_CLK, "clk_fsys_usb30drd_ref_clk", "mout_fsys_usb30drd_user",
|
||||
CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK, 21, 0, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info fsys_cmu_info __initconst = {
|
||||
.pll_clks = fsys_pll_clks,
|
||||
.nr_pll_clks = ARRAY_SIZE(fsys_pll_clks),
|
||||
.mux_clks = fsys_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
|
||||
.gate_clks = fsys_gate_clks,
|
||||
|
||||
@ -28,7 +28,7 @@
|
||||
#define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
|
||||
#define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
|
||||
#define CLKS_NR_MFCMSCL (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)
|
||||
#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
|
||||
#define CLKS_NR_PERI (CLK_GOUT_BUSIF_TMU_PCLK + 1)
|
||||
#define CLKS_NR_CORE (CLK_GOUT_SPDMA_CORE_ACLK + 1)
|
||||
#define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_PCLK + 1)
|
||||
|
||||
@ -1921,6 +1921,7 @@ static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
|
||||
#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c
|
||||
#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010
|
||||
#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014
|
||||
#define CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK 0x2018
|
||||
#define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020
|
||||
#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024
|
||||
#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028
|
||||
@ -1957,6 +1958,7 @@ static const unsigned long peri_clk_regs[] __initconst = {
|
||||
CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0,
|
||||
CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1,
|
||||
CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2,
|
||||
CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
|
||||
@ -2068,6 +2070,9 @@ static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
|
||||
GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk",
|
||||
"mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_BUSIF_TMU_PCLK, "gout_busif_tmu_pclk",
|
||||
"mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK, 21, 0, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info peri_cmu_info __initconst = {
|
||||
|
||||
@ -20,6 +20,7 @@
|
||||
#define CLKS_NR_TOP (GOUT_CLKCMU_PERIS_BUS + 1)
|
||||
#define CLKS_NR_BUSMC (CLK_GOUT_BUSMC_SPDMA_PCLK + 1)
|
||||
#define CLKS_NR_CORE (CLK_GOUT_CORE_CMU_CORE_PCLK + 1)
|
||||
#define CLKS_NR_DPUM (CLK_GOUT_DPUM_SYSMMU_D3_CLK + 1)
|
||||
#define CLKS_NR_FSYS0 (CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1)
|
||||
#define CLKS_NR_FSYS1 (CLK_GOUT_FSYS1_USB30_1_ACLK + 1)
|
||||
#define CLKS_NR_FSYS2 (CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1)
|
||||
@ -1076,6 +1077,85 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
|
||||
.clk_name = "dout_clkcmu_core_bus",
|
||||
};
|
||||
|
||||
/* ---- CMU_DPUM ---------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_DPUM (0x18c00000) */
|
||||
#define PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER 0x0600
|
||||
#define CLK_CON_DIV_DIV_CLK_DPUM_BUSP 0x1800
|
||||
#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON 0x202c
|
||||
#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA 0x2030
|
||||
#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP 0x2034
|
||||
#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1 0x207c
|
||||
#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1 0x2084
|
||||
#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1 0x208c
|
||||
#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1 0x2094
|
||||
|
||||
static const unsigned long dpum_clk_regs[] __initconst = {
|
||||
PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER,
|
||||
CLK_CON_DIV_DIV_CLK_DPUM_BUSP,
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON,
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA,
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP,
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1,
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1,
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1,
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1,
|
||||
};
|
||||
|
||||
PNAME(mout_dpum_bus_user_p) = { "oscclk", "dout_clkcmu_dpum_bus" };
|
||||
|
||||
static const struct samsung_mux_clock dpum_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_DPUM_BUS_USER, "mout_dpum_bus_user",
|
||||
mout_dpum_bus_user_p, PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER, 4, 1),
|
||||
};
|
||||
|
||||
static const struct samsung_div_clock dpum_div_clks[] __initconst = {
|
||||
DIV(CLK_DOUT_DPUM_BUSP, "dout_dpum_busp", "mout_dpum_bus_user",
|
||||
CLK_CON_DIV_DIV_CLK_DPUM_BUSP, 0, 3),
|
||||
};
|
||||
|
||||
static const struct samsung_gate_clock dpum_gate_clks[] __initconst = {
|
||||
GATE(CLK_GOUT_DPUM_ACLK_DECON, "gout_dpum_decon_aclk",
|
||||
"mout_dpum_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON, 21,
|
||||
0, 0),
|
||||
GATE(CLK_GOUT_DPUM_ACLK_DMA, "gout_dpum_dma_aclk", "mout_dpum_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA, 21,
|
||||
0, 0),
|
||||
GATE(CLK_GOUT_DPUM_ACLK_DPP, "gout_dpum_dpp_aclk", "mout_dpum_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP, 21,
|
||||
0, 0),
|
||||
GATE(CLK_GOUT_DPUM_SYSMMU_D0_CLK, "gout_dpum_sysmmu_d0_clk",
|
||||
"mout_dpum_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1, 21,
|
||||
0, 0),
|
||||
GATE(CLK_GOUT_DPUM_SYSMMU_D1_CLK, "gout_dpum_sysmmu_d1_clk",
|
||||
"mout_dpum_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1, 21,
|
||||
0, 0),
|
||||
GATE(CLK_GOUT_DPUM_SYSMMU_D2_CLK, "gout_dpum_sysmmu_d2_clk",
|
||||
"mout_dpum_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1, 21,
|
||||
0, 0),
|
||||
GATE(CLK_GOUT_DPUM_SYSMMU_D3_CLK, "gout_dpum_sysmmu_d3_clk",
|
||||
"mout_dpum_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1, 21,
|
||||
0, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info dpum_cmu_info __initconst = {
|
||||
.mux_clks = dpum_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(dpum_mux_clks),
|
||||
.div_clks = dpum_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(dpum_div_clks),
|
||||
.gate_clks = dpum_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(dpum_gate_clks),
|
||||
.nr_clk_ids = CLKS_NR_DPUM,
|
||||
.clk_regs = dpum_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(dpum_clk_regs),
|
||||
.clk_name = "bus",
|
||||
};
|
||||
|
||||
/* ---- CMU_FSYS0 ---------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_FSYS2 (0x17700000) */
|
||||
@ -2085,6 +2165,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov9-cmu-core",
|
||||
.data = &core_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov9-cmu-dpum",
|
||||
.data = &dpum_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov9-cmu-fsys0",
|
||||
.data = &fsys0_cmu_info,
|
||||
|
||||
1173
drivers/clk/samsung/clk-exynosautov920.c
Normal file
1173
drivers/clk/samsung/clk-exynosautov920.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -430,6 +430,9 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops = {
|
||||
#define PLL0822X_LOCK_STAT_SHIFT (29)
|
||||
#define PLL0822X_ENABLE_SHIFT (31)
|
||||
|
||||
/* PLL1418x is similar to PLL0822x, except that MDIV is one bit smaller */
|
||||
#define PLL1418X_MDIV_MASK (0x1FF)
|
||||
|
||||
static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
@ -438,7 +441,10 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
|
||||
u64 fvco = parent_rate;
|
||||
|
||||
pll_con3 = readl_relaxed(pll->con_reg);
|
||||
mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;
|
||||
if (pll->type != pll_1418x)
|
||||
mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;
|
||||
else
|
||||
mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL1418X_MDIV_MASK;
|
||||
pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
|
||||
sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
|
||||
|
||||
@ -456,7 +462,12 @@ static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
{
|
||||
const struct samsung_pll_rate_table *rate;
|
||||
struct samsung_clk_pll *pll = to_clk_pll(hw);
|
||||
u32 pll_con3;
|
||||
u32 mdiv_mask, pll_con3;
|
||||
|
||||
if (pll->type != pll_1418x)
|
||||
mdiv_mask = PLL0822X_MDIV_MASK;
|
||||
else
|
||||
mdiv_mask = PLL1418X_MDIV_MASK;
|
||||
|
||||
/* Get required rate settings from table */
|
||||
rate = samsung_get_pll_settings(pll, drate);
|
||||
@ -468,7 +479,7 @@ static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
|
||||
/* Change PLL PMS values */
|
||||
pll_con3 = readl_relaxed(pll->con_reg);
|
||||
pll_con3 &= ~((PLL0822X_MDIV_MASK << PLL0822X_MDIV_SHIFT) |
|
||||
pll_con3 &= ~((mdiv_mask << PLL0822X_MDIV_SHIFT) |
|
||||
(PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) |
|
||||
(PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT));
|
||||
pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) |
|
||||
@ -1261,6 +1272,47 @@ static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
|
||||
.recalc_rate = samsung_pll2650xx_recalc_rate,
|
||||
};
|
||||
|
||||
/*
|
||||
* PLL531X Clock Type
|
||||
*/
|
||||
/* Maximum lock time can be 500 * PDIV cycles */
|
||||
#define PLL531X_LOCK_FACTOR (500)
|
||||
#define PLL531X_MDIV_MASK (0x3FF)
|
||||
#define PLL531X_PDIV_MASK (0x3F)
|
||||
#define PLL531X_SDIV_MASK (0x7)
|
||||
#define PLL531X_FDIV_MASK (0xFFFFFFFF)
|
||||
#define PLL531X_MDIV_SHIFT (16)
|
||||
#define PLL531X_PDIV_SHIFT (8)
|
||||
#define PLL531X_SDIV_SHIFT (0)
|
||||
|
||||
static unsigned long samsung_pll531x_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct samsung_clk_pll *pll = to_clk_pll(hw);
|
||||
u32 pdiv, sdiv, fdiv, pll_con0, pll_con8;
|
||||
u64 mdiv, fout = parent_rate;
|
||||
|
||||
pll_con0 = readl_relaxed(pll->con_reg);
|
||||
pll_con8 = readl_relaxed(pll->con_reg + 20);
|
||||
mdiv = (pll_con0 >> PLL531X_MDIV_SHIFT) & PLL531X_MDIV_MASK;
|
||||
pdiv = (pll_con0 >> PLL531X_PDIV_SHIFT) & PLL531X_PDIV_MASK;
|
||||
sdiv = (pll_con0 >> PLL531X_SDIV_SHIFT) & PLL531X_SDIV_MASK;
|
||||
fdiv = (pll_con8 & PLL531X_FDIV_MASK);
|
||||
|
||||
if (fdiv >> 31)
|
||||
mdiv--;
|
||||
|
||||
fout *= (mdiv << 24) + (fdiv >> 8);
|
||||
do_div(fout, (pdiv << sdiv));
|
||||
fout >>= 24;
|
||||
|
||||
return (unsigned long)fout;
|
||||
}
|
||||
|
||||
static const struct clk_ops samsung_pll531x_clk_ops = {
|
||||
.recalc_rate = samsung_pll531x_recalc_rate,
|
||||
};
|
||||
|
||||
static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
||||
const struct samsung_pll_clock *pll_clk)
|
||||
{
|
||||
@ -1317,6 +1369,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
||||
init.ops = &samsung_pll35xx_clk_ops;
|
||||
break;
|
||||
case pll_1417x:
|
||||
case pll_1418x:
|
||||
case pll_0818x:
|
||||
case pll_0822x:
|
||||
case pll_0516x:
|
||||
@ -1394,6 +1447,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
||||
else
|
||||
init.ops = &samsung_pll2650xx_clk_ops;
|
||||
break;
|
||||
case pll_531x:
|
||||
init.ops = &samsung_pll531x_clk_ops;
|
||||
break;
|
||||
default:
|
||||
pr_warn("%s: Unknown pll type for pll clk %s\n",
|
||||
__func__, pll_clk->name);
|
||||
|
||||
@ -30,6 +30,7 @@ enum samsung_pll_type {
|
||||
pll_2650x,
|
||||
pll_2650xx,
|
||||
pll_1417x,
|
||||
pll_1418x,
|
||||
pll_1450x,
|
||||
pll_1451x,
|
||||
pll_1452x,
|
||||
@ -41,6 +42,7 @@ enum samsung_pll_type {
|
||||
pll_0516x,
|
||||
pll_0517x,
|
||||
pll_0518x,
|
||||
pll_531x,
|
||||
};
|
||||
|
||||
#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
|
||||
|
||||
@ -69,6 +69,8 @@
|
||||
#define CLK_GOUT_FSYS_MMC_EMBD 58
|
||||
#define CLK_GOUT_FSYS_MMC_SDIO 59
|
||||
#define CLK_GOUT_FSYS_USB30DRD 60
|
||||
#define CLK_MOUT_SHARED0_PLL 61
|
||||
#define CLK_MOUT_SHARED1_PLL 62
|
||||
|
||||
/* CMU_CORE */
|
||||
#define CLK_MOUT_CORE_BUS_USER 1
|
||||
@ -132,16 +134,24 @@
|
||||
#define CLK_GOUT_WDT1_PCLK 43
|
||||
|
||||
/* CMU_FSYS */
|
||||
#define CLK_MOUT_FSYS_BUS_USER 1
|
||||
#define CLK_MOUT_FSYS_MMC_CARD_USER 2
|
||||
#define CLK_MOUT_FSYS_MMC_EMBD_USER 3
|
||||
#define CLK_MOUT_FSYS_MMC_SDIO_USER 4
|
||||
#define CLK_MOUT_FSYS_USB30DRD_USER 4
|
||||
#define CLK_GOUT_MMC_CARD_ACLK 5
|
||||
#define CLK_GOUT_MMC_CARD_SDCLKIN 6
|
||||
#define CLK_GOUT_MMC_EMBD_ACLK 7
|
||||
#define CLK_GOUT_MMC_EMBD_SDCLKIN 8
|
||||
#define CLK_GOUT_MMC_SDIO_ACLK 9
|
||||
#define CLK_GOUT_MMC_SDIO_SDCLKIN 10
|
||||
#define CLK_MOUT_FSYS_BUS_USER 1
|
||||
#define CLK_MOUT_FSYS_MMC_CARD_USER 2
|
||||
#define CLK_MOUT_FSYS_MMC_EMBD_USER 3
|
||||
#define CLK_MOUT_FSYS_MMC_SDIO_USER 4
|
||||
#define CLK_GOUT_MMC_CARD_ACLK 5
|
||||
#define CLK_GOUT_MMC_CARD_SDCLKIN 6
|
||||
#define CLK_GOUT_MMC_EMBD_ACLK 7
|
||||
#define CLK_GOUT_MMC_EMBD_SDCLKIN 8
|
||||
#define CLK_GOUT_MMC_SDIO_ACLK 9
|
||||
#define CLK_GOUT_MMC_SDIO_SDCLKIN 10
|
||||
#define CLK_MOUT_FSYS_USB30DRD_USER 11
|
||||
#define CLK_MOUT_USB_PLL 12
|
||||
#define CLK_FOUT_USB_PLL 13
|
||||
#define CLK_FSYS_USB20PHY_CLKCORE 14
|
||||
#define CLK_FSYS_USB30DRD_ACLK_20PHYCTRL 15
|
||||
#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_0 16
|
||||
#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_1 17
|
||||
#define CLK_FSYS_USB30DRD_BUS_CLK_EARLY 18
|
||||
#define CLK_FSYS_USB30DRD_REF_CLK 19
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */
|
||||
|
||||
@ -358,6 +358,7 @@
|
||||
#define CLK_GOUT_UART_PCLK 32
|
||||
#define CLK_GOUT_WDT0_PCLK 33
|
||||
#define CLK_GOUT_WDT1_PCLK 34
|
||||
#define CLK_GOUT_BUSIF_TMU_PCLK 35
|
||||
|
||||
/* CMU_CORE */
|
||||
#define CLK_MOUT_CORE_BUS_USER 1
|
||||
|
||||
@ -175,8 +175,6 @@
|
||||
#define PCLK_CIF 352
|
||||
#define PCLK_OTP_PHY 353
|
||||
|
||||
#define CLK_NR_CLKS (PCLK_OTP_PHY + 1)
|
||||
|
||||
/* pmu-clocks indices */
|
||||
|
||||
#define PLL_GPLL 1
|
||||
@ -195,8 +193,6 @@
|
||||
#define PCLK_GPIO0_PMU 20
|
||||
#define PCLK_UART0_PMU 21
|
||||
|
||||
#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0_PO 0
|
||||
#define SRST_CORE1_PO 1
|
||||
|
||||
@ -193,10 +193,15 @@
|
||||
#define GCC_MMSS_GPLL0_DIV_CLK 184
|
||||
#define GCC_GPU_GPLL0_DIV_CLK 185
|
||||
#define GCC_GPU_GPLL0_CLK 186
|
||||
#define HLOS1_VOTE_LPASS_CORE_SMMU_CLK 187
|
||||
#define HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 188
|
||||
#define GCC_MSS_Q6_BIMC_AXI_CLK 189
|
||||
|
||||
#define PCIE_0_GDSC 0
|
||||
#define UFS_GDSC 1
|
||||
#define USB_30_GDSC 2
|
||||
#define LPASS_ADSP_GDSC 3
|
||||
#define LPASS_CORE_GDSC 4
|
||||
|
||||
#define GCC_BLSP1_QUP1_BCR 0
|
||||
#define GCC_BLSP1_QUP2_BCR 1
|
||||
|
||||
@ -248,6 +248,7 @@
|
||||
#define GCC_USB3_SEC_CLKREF_CLK 238
|
||||
#define GCC_UFS_MEM_CLKREF_EN 239
|
||||
#define GCC_UFS_CARD_CLKREF_EN 240
|
||||
#define GPLL9 241
|
||||
|
||||
#define GCC_EMAC_BCR 0
|
||||
#define GCC_GPU_BCR 1
|
||||
@ -294,6 +295,10 @@
|
||||
#define GCC_VIDEO_AXI0_CLK_BCR 42
|
||||
#define GCC_VIDEO_AXI1_CLK_BCR 43
|
||||
#define GCC_USB3_DP_PHY_SEC_BCR 44
|
||||
#define GCC_USB3_UNIPHY_MP0_BCR 45
|
||||
#define GCC_USB3_UNIPHY_MP1_BCR 46
|
||||
#define GCC_USB3UNIPHY_PHY_MP0_BCR 47
|
||||
#define GCC_USB3UNIPHY_PHY_MP1_BCR 48
|
||||
|
||||
/* GCC GDSCRs */
|
||||
#define EMAC_GDSC 0
|
||||
|
||||
106
include/dt-bindings/clock/qcom,sm4450-camcc.h
Normal file
106
include/dt-bindings/clock/qcom,sm4450-camcc.h
Normal file
@ -0,0 +1,106 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H
|
||||
|
||||
/* CAM_CC clocks */
|
||||
#define CAM_CC_BPS_AHB_CLK 0
|
||||
#define CAM_CC_BPS_AREG_CLK 1
|
||||
#define CAM_CC_BPS_CLK 2
|
||||
#define CAM_CC_BPS_CLK_SRC 3
|
||||
#define CAM_CC_CAMNOC_ATB_CLK 4
|
||||
#define CAM_CC_CAMNOC_AXI_CLK 5
|
||||
#define CAM_CC_CAMNOC_AXI_CLK_SRC 6
|
||||
#define CAM_CC_CAMNOC_AXI_HF_CLK 7
|
||||
#define CAM_CC_CAMNOC_AXI_SF_CLK 8
|
||||
#define CAM_CC_CCI_0_CLK 9
|
||||
#define CAM_CC_CCI_0_CLK_SRC 10
|
||||
#define CAM_CC_CCI_1_CLK 11
|
||||
#define CAM_CC_CCI_1_CLK_SRC 12
|
||||
#define CAM_CC_CORE_AHB_CLK 13
|
||||
#define CAM_CC_CPAS_AHB_CLK 14
|
||||
#define CAM_CC_CPHY_RX_CLK_SRC 15
|
||||
#define CAM_CC_CRE_AHB_CLK 16
|
||||
#define CAM_CC_CRE_CLK 17
|
||||
#define CAM_CC_CRE_CLK_SRC 18
|
||||
#define CAM_CC_CSI0PHYTIMER_CLK 19
|
||||
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 20
|
||||
#define CAM_CC_CSI1PHYTIMER_CLK 21
|
||||
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 22
|
||||
#define CAM_CC_CSI2PHYTIMER_CLK 23
|
||||
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 24
|
||||
#define CAM_CC_CSIPHY0_CLK 25
|
||||
#define CAM_CC_CSIPHY1_CLK 26
|
||||
#define CAM_CC_CSIPHY2_CLK 27
|
||||
#define CAM_CC_FAST_AHB_CLK_SRC 28
|
||||
#define CAM_CC_ICP_ATB_CLK 29
|
||||
#define CAM_CC_ICP_CLK 30
|
||||
#define CAM_CC_ICP_CLK_SRC 31
|
||||
#define CAM_CC_ICP_CTI_CLK 32
|
||||
#define CAM_CC_ICP_TS_CLK 33
|
||||
#define CAM_CC_MCLK0_CLK 34
|
||||
#define CAM_CC_MCLK0_CLK_SRC 35
|
||||
#define CAM_CC_MCLK1_CLK 36
|
||||
#define CAM_CC_MCLK1_CLK_SRC 37
|
||||
#define CAM_CC_MCLK2_CLK 38
|
||||
#define CAM_CC_MCLK2_CLK_SRC 39
|
||||
#define CAM_CC_MCLK3_CLK 40
|
||||
#define CAM_CC_MCLK3_CLK_SRC 41
|
||||
#define CAM_CC_OPE_0_AHB_CLK 42
|
||||
#define CAM_CC_OPE_0_AREG_CLK 43
|
||||
#define CAM_CC_OPE_0_CLK 44
|
||||
#define CAM_CC_OPE_0_CLK_SRC 45
|
||||
#define CAM_CC_PLL0 46
|
||||
#define CAM_CC_PLL0_OUT_EVEN 47
|
||||
#define CAM_CC_PLL0_OUT_ODD 48
|
||||
#define CAM_CC_PLL1 49
|
||||
#define CAM_CC_PLL1_OUT_EVEN 50
|
||||
#define CAM_CC_PLL2 51
|
||||
#define CAM_CC_PLL2_OUT_EVEN 52
|
||||
#define CAM_CC_PLL3 53
|
||||
#define CAM_CC_PLL3_OUT_EVEN 54
|
||||
#define CAM_CC_PLL4 55
|
||||
#define CAM_CC_PLL4_OUT_EVEN 56
|
||||
#define CAM_CC_SLOW_AHB_CLK_SRC 57
|
||||
#define CAM_CC_SOC_AHB_CLK 58
|
||||
#define CAM_CC_SYS_TMR_CLK 59
|
||||
#define CAM_CC_TFE_0_AHB_CLK 60
|
||||
#define CAM_CC_TFE_0_CLK 61
|
||||
#define CAM_CC_TFE_0_CLK_SRC 62
|
||||
#define CAM_CC_TFE_0_CPHY_RX_CLK 63
|
||||
#define CAM_CC_TFE_0_CSID_CLK 64
|
||||
#define CAM_CC_TFE_0_CSID_CLK_SRC 65
|
||||
#define CAM_CC_TFE_1_AHB_CLK 66
|
||||
#define CAM_CC_TFE_1_CLK 67
|
||||
#define CAM_CC_TFE_1_CLK_SRC 68
|
||||
#define CAM_CC_TFE_1_CPHY_RX_CLK 69
|
||||
#define CAM_CC_TFE_1_CSID_CLK 70
|
||||
#define CAM_CC_TFE_1_CSID_CLK_SRC 71
|
||||
|
||||
/* CAM_CC power domains */
|
||||
#define CAM_CC_CAMSS_TOP_GDSC 0
|
||||
|
||||
/* CAM_CC resets */
|
||||
#define CAM_CC_BPS_BCR 0
|
||||
#define CAM_CC_CAMNOC_BCR 1
|
||||
#define CAM_CC_CAMSS_TOP_BCR 2
|
||||
#define CAM_CC_CCI_0_BCR 3
|
||||
#define CAM_CC_CCI_1_BCR 4
|
||||
#define CAM_CC_CPAS_BCR 5
|
||||
#define CAM_CC_CRE_BCR 6
|
||||
#define CAM_CC_CSI0PHY_BCR 7
|
||||
#define CAM_CC_CSI1PHY_BCR 8
|
||||
#define CAM_CC_CSI2PHY_BCR 9
|
||||
#define CAM_CC_ICP_BCR 10
|
||||
#define CAM_CC_MCLK0_BCR 11
|
||||
#define CAM_CC_MCLK1_BCR 12
|
||||
#define CAM_CC_MCLK2_BCR 13
|
||||
#define CAM_CC_MCLK3_BCR 14
|
||||
#define CAM_CC_OPE_0_BCR 15
|
||||
#define CAM_CC_TFE_0_BCR 16
|
||||
#define CAM_CC_TFE_1_BCR 17
|
||||
|
||||
#endif
|
||||
51
include/dt-bindings/clock/qcom,sm4450-dispcc.h
Normal file
51
include/dt-bindings/clock/qcom,sm4450-dispcc.h
Normal file
@ -0,0 +1,51 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
|
||||
|
||||
/* DISP_CC clocks */
|
||||
#define DISP_CC_MDSS_AHB1_CLK 0
|
||||
#define DISP_CC_MDSS_AHB_CLK 1
|
||||
#define DISP_CC_MDSS_AHB_CLK_SRC 2
|
||||
#define DISP_CC_MDSS_BYTE0_CLK 3
|
||||
#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
|
||||
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
|
||||
#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
|
||||
#define DISP_CC_MDSS_ESC0_CLK 7
|
||||
#define DISP_CC_MDSS_ESC0_CLK_SRC 8
|
||||
#define DISP_CC_MDSS_MDP1_CLK 9
|
||||
#define DISP_CC_MDSS_MDP_CLK 10
|
||||
#define DISP_CC_MDSS_MDP_CLK_SRC 11
|
||||
#define DISP_CC_MDSS_MDP_LUT1_CLK 12
|
||||
#define DISP_CC_MDSS_MDP_LUT_CLK 13
|
||||
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 14
|
||||
#define DISP_CC_MDSS_PCLK0_CLK 15
|
||||
#define DISP_CC_MDSS_PCLK0_CLK_SRC 16
|
||||
#define DISP_CC_MDSS_ROT1_CLK 17
|
||||
#define DISP_CC_MDSS_ROT_CLK 18
|
||||
#define DISP_CC_MDSS_ROT_CLK_SRC 19
|
||||
#define DISP_CC_MDSS_RSCC_AHB_CLK 20
|
||||
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 21
|
||||
#define DISP_CC_MDSS_VSYNC1_CLK 22
|
||||
#define DISP_CC_MDSS_VSYNC_CLK 23
|
||||
#define DISP_CC_MDSS_VSYNC_CLK_SRC 24
|
||||
#define DISP_CC_PLL0 25
|
||||
#define DISP_CC_PLL1 26
|
||||
#define DISP_CC_SLEEP_CLK 27
|
||||
#define DISP_CC_SLEEP_CLK_SRC 28
|
||||
#define DISP_CC_XO_CLK 29
|
||||
#define DISP_CC_XO_CLK_SRC 30
|
||||
|
||||
/* DISP_CC power domains */
|
||||
#define DISP_CC_MDSS_CORE_GDSC 0
|
||||
#define DISP_CC_MDSS_CORE_INT2_GDSC 1
|
||||
|
||||
/* DISP_CC resets */
|
||||
#define DISP_CC_MDSS_CORE_BCR 0
|
||||
#define DISP_CC_MDSS_CORE_INT2_BCR 1
|
||||
#define DISP_CC_MDSS_RSCC_BCR 2
|
||||
|
||||
#endif
|
||||
62
include/dt-bindings/clock/qcom,sm4450-gpucc.h
Normal file
62
include/dt-bindings/clock/qcom,sm4450-gpucc.h
Normal file
@ -0,0 +1,62 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H
|
||||
|
||||
/* GPU_CC clocks */
|
||||
#define GPU_CC_AHB_CLK 0
|
||||
#define GPU_CC_CB_CLK 1
|
||||
#define GPU_CC_CRC_AHB_CLK 2
|
||||
#define GPU_CC_CX_FF_CLK 3
|
||||
#define GPU_CC_CX_GFX3D_CLK 4
|
||||
#define GPU_CC_CX_GFX3D_SLV_CLK 5
|
||||
#define GPU_CC_CX_GMU_CLK 6
|
||||
#define GPU_CC_CX_SNOC_DVM_CLK 7
|
||||
#define GPU_CC_CXO_AON_CLK 8
|
||||
#define GPU_CC_CXO_CLK 9
|
||||
#define GPU_CC_DEMET_CLK 10
|
||||
#define GPU_CC_DEMET_DIV_CLK_SRC 11
|
||||
#define GPU_CC_FF_CLK_SRC 12
|
||||
#define GPU_CC_FREQ_MEASURE_CLK 13
|
||||
#define GPU_CC_GMU_CLK_SRC 14
|
||||
#define GPU_CC_GX_CXO_CLK 15
|
||||
#define GPU_CC_GX_FF_CLK 16
|
||||
#define GPU_CC_GX_GFX3D_CLK 17
|
||||
#define GPU_CC_GX_GFX3D_CLK_SRC 18
|
||||
#define GPU_CC_GX_GFX3D_RDVM_CLK 19
|
||||
#define GPU_CC_GX_GMU_CLK 20
|
||||
#define GPU_CC_GX_VSENSE_CLK 21
|
||||
#define GPU_CC_HUB_AHB_DIV_CLK_SRC 22
|
||||
#define GPU_CC_HUB_AON_CLK 23
|
||||
#define GPU_CC_HUB_CLK_SRC 24
|
||||
#define GPU_CC_HUB_CX_INT_CLK 25
|
||||
#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 26
|
||||
#define GPU_CC_MEMNOC_GFX_CLK 27
|
||||
#define GPU_CC_MND1X_0_GFX3D_CLK 28
|
||||
#define GPU_CC_PLL0 29
|
||||
#define GPU_CC_PLL1 30
|
||||
#define GPU_CC_SLEEP_CLK 31
|
||||
#define GPU_CC_XO_CLK_SRC 32
|
||||
#define GPU_CC_XO_DIV_CLK_SRC 33
|
||||
|
||||
/* GPU_CC power domains */
|
||||
#define GPU_CC_CX_GDSC 0
|
||||
#define GPU_CC_GX_GDSC 1
|
||||
|
||||
/* GPU_CC resets */
|
||||
#define GPU_CC_ACD_BCR 0
|
||||
#define GPU_CC_CB_BCR 1
|
||||
#define GPU_CC_CX_BCR 2
|
||||
#define GPU_CC_FAST_HUB_BCR 3
|
||||
#define GPU_CC_FF_BCR 4
|
||||
#define GPU_CC_GFX3D_AON_BCR 5
|
||||
#define GPU_CC_GMU_BCR 6
|
||||
#define GPU_CC_GX_BCR 7
|
||||
#define GPU_CC_XO_BCR 8
|
||||
#define GPU_CC_GX_ACD_IROOT_BCR 9
|
||||
#define GPU_CC_RBCPR_BCR 10
|
||||
|
||||
#endif
|
||||
135
include/dt-bindings/clock/qcom,sm8150-camcc.h
Normal file
135
include/dt-bindings/clock/qcom,sm8150-camcc.h
Normal file
@ -0,0 +1,135 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8150_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8150_H
|
||||
|
||||
/* CAM_CC clocks */
|
||||
#define CAM_CC_PLL0 0
|
||||
#define CAM_CC_PLL0_OUT_EVEN 1
|
||||
#define CAM_CC_PLL0_OUT_ODD 2
|
||||
#define CAM_CC_PLL1 3
|
||||
#define CAM_CC_PLL1_OUT_EVEN 4
|
||||
#define CAM_CC_PLL2 5
|
||||
#define CAM_CC_PLL2_OUT_MAIN 6
|
||||
#define CAM_CC_PLL3 7
|
||||
#define CAM_CC_PLL3_OUT_EVEN 8
|
||||
#define CAM_CC_PLL4 9
|
||||
#define CAM_CC_PLL4_OUT_EVEN 10
|
||||
#define CAM_CC_BPS_AHB_CLK 11
|
||||
#define CAM_CC_BPS_AREG_CLK 12
|
||||
#define CAM_CC_BPS_AXI_CLK 13
|
||||
#define CAM_CC_BPS_CLK 14
|
||||
#define CAM_CC_BPS_CLK_SRC 15
|
||||
#define CAM_CC_CAMNOC_AXI_CLK 16
|
||||
#define CAM_CC_CAMNOC_AXI_CLK_SRC 17
|
||||
#define CAM_CC_CAMNOC_DCD_XO_CLK 18
|
||||
#define CAM_CC_CCI_0_CLK 19
|
||||
#define CAM_CC_CCI_0_CLK_SRC 20
|
||||
#define CAM_CC_CCI_1_CLK 21
|
||||
#define CAM_CC_CCI_1_CLK_SRC 22
|
||||
#define CAM_CC_CORE_AHB_CLK 23
|
||||
#define CAM_CC_CPAS_AHB_CLK 24
|
||||
#define CAM_CC_CPHY_RX_CLK_SRC 25
|
||||
#define CAM_CC_CSI0PHYTIMER_CLK 26
|
||||
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 27
|
||||
#define CAM_CC_CSI1PHYTIMER_CLK 28
|
||||
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 29
|
||||
#define CAM_CC_CSI2PHYTIMER_CLK 30
|
||||
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 31
|
||||
#define CAM_CC_CSI3PHYTIMER_CLK 32
|
||||
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 33
|
||||
#define CAM_CC_CSIPHY0_CLK 34
|
||||
#define CAM_CC_CSIPHY1_CLK 35
|
||||
#define CAM_CC_CSIPHY2_CLK 36
|
||||
#define CAM_CC_CSIPHY3_CLK 37
|
||||
#define CAM_CC_FAST_AHB_CLK_SRC 38
|
||||
#define CAM_CC_FD_CORE_CLK 39
|
||||
#define CAM_CC_FD_CORE_CLK_SRC 40
|
||||
#define CAM_CC_FD_CORE_UAR_CLK 41
|
||||
#define CAM_CC_GDSC_CLK 42
|
||||
#define CAM_CC_ICP_AHB_CLK 43
|
||||
#define CAM_CC_ICP_CLK 44
|
||||
#define CAM_CC_ICP_CLK_SRC 45
|
||||
#define CAM_CC_IFE_0_AXI_CLK 46
|
||||
#define CAM_CC_IFE_0_CLK 47
|
||||
#define CAM_CC_IFE_0_CLK_SRC 48
|
||||
#define CAM_CC_IFE_0_CPHY_RX_CLK 49
|
||||
#define CAM_CC_IFE_0_CSID_CLK 50
|
||||
#define CAM_CC_IFE_0_CSID_CLK_SRC 51
|
||||
#define CAM_CC_IFE_0_DSP_CLK 52
|
||||
#define CAM_CC_IFE_1_AXI_CLK 53
|
||||
#define CAM_CC_IFE_1_CLK 54
|
||||
#define CAM_CC_IFE_1_CLK_SRC 55
|
||||
#define CAM_CC_IFE_1_CPHY_RX_CLK 56
|
||||
#define CAM_CC_IFE_1_CSID_CLK 57
|
||||
#define CAM_CC_IFE_1_CSID_CLK_SRC 58
|
||||
#define CAM_CC_IFE_1_DSP_CLK 59
|
||||
#define CAM_CC_IFE_LITE_0_CLK 60
|
||||
#define CAM_CC_IFE_LITE_0_CLK_SRC 61
|
||||
#define CAM_CC_IFE_LITE_0_CPHY_RX_CLK 62
|
||||
#define CAM_CC_IFE_LITE_0_CSID_CLK 63
|
||||
#define CAM_CC_IFE_LITE_0_CSID_CLK_SRC 64
|
||||
#define CAM_CC_IFE_LITE_1_CLK 65
|
||||
#define CAM_CC_IFE_LITE_1_CLK_SRC 66
|
||||
#define CAM_CC_IFE_LITE_1_CPHY_RX_CLK 67
|
||||
#define CAM_CC_IFE_LITE_1_CSID_CLK 68
|
||||
#define CAM_CC_IFE_LITE_1_CSID_CLK_SRC 69
|
||||
#define CAM_CC_IPE_0_AHB_CLK 70
|
||||
#define CAM_CC_IPE_0_AREG_CLK 71
|
||||
#define CAM_CC_IPE_0_AXI_CLK 72
|
||||
#define CAM_CC_IPE_0_CLK 73
|
||||
#define CAM_CC_IPE_0_CLK_SRC 74
|
||||
#define CAM_CC_IPE_1_AHB_CLK 75
|
||||
#define CAM_CC_IPE_1_AREG_CLK 76
|
||||
#define CAM_CC_IPE_1_AXI_CLK 77
|
||||
#define CAM_CC_IPE_1_CLK 78
|
||||
#define CAM_CC_JPEG_CLK 79
|
||||
#define CAM_CC_JPEG_CLK_SRC 80
|
||||
#define CAM_CC_LRME_CLK 81
|
||||
#define CAM_CC_LRME_CLK_SRC 82
|
||||
#define CAM_CC_MCLK0_CLK 83
|
||||
#define CAM_CC_MCLK0_CLK_SRC 84
|
||||
#define CAM_CC_MCLK1_CLK 85
|
||||
#define CAM_CC_MCLK1_CLK_SRC 86
|
||||
#define CAM_CC_MCLK2_CLK 87
|
||||
#define CAM_CC_MCLK2_CLK_SRC 88
|
||||
#define CAM_CC_MCLK3_CLK 89
|
||||
#define CAM_CC_MCLK3_CLK_SRC 90
|
||||
#define CAM_CC_SLOW_AHB_CLK_SRC 91
|
||||
|
||||
/* CAM_CC power domains */
|
||||
#define TITAN_TOP_GDSC 0
|
||||
#define BPS_GDSC 1
|
||||
#define IFE_0_GDSC 2
|
||||
#define IFE_1_GDSC 3
|
||||
#define IPE_0_GDSC 4
|
||||
#define IPE_1_GDSC 5
|
||||
|
||||
/* CAM_CC resets */
|
||||
#define CAM_CC_BPS_BCR 0
|
||||
#define CAM_CC_CAMNOC_BCR 1
|
||||
#define CAM_CC_CCI_BCR 2
|
||||
#define CAM_CC_CPAS_BCR 3
|
||||
#define CAM_CC_CSI0PHY_BCR 4
|
||||
#define CAM_CC_CSI1PHY_BCR 5
|
||||
#define CAM_CC_CSI2PHY_BCR 6
|
||||
#define CAM_CC_CSI3PHY_BCR 7
|
||||
#define CAM_CC_FD_BCR 8
|
||||
#define CAM_CC_ICP_BCR 9
|
||||
#define CAM_CC_IFE_0_BCR 10
|
||||
#define CAM_CC_IFE_1_BCR 11
|
||||
#define CAM_CC_IFE_LITE_0_BCR 12
|
||||
#define CAM_CC_IFE_LITE_1_BCR 13
|
||||
#define CAM_CC_IPE_0_BCR 14
|
||||
#define CAM_CC_IPE_1_BCR 15
|
||||
#define CAM_CC_JPEG_BCR 16
|
||||
#define CAM_CC_LRME_BCR 17
|
||||
#define CAM_CC_MCLK0_BCR 18
|
||||
#define CAM_CC_MCLK1_BCR 19
|
||||
#define CAM_CC_MCLK2_BCR 20
|
||||
#define CAM_CC_MCLK3_BCR 21
|
||||
|
||||
#endif
|
||||
@ -1,102 +0,0 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
|
||||
* Copyright (c) 2023, Linaro Ltd.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H
|
||||
|
||||
/* DISP_CC clocks */
|
||||
#define DISP_CC_MDSS_ACCU_CLK 0
|
||||
#define DISP_CC_MDSS_AHB1_CLK 1
|
||||
#define DISP_CC_MDSS_AHB_CLK 2
|
||||
#define DISP_CC_MDSS_AHB_CLK_SRC 3
|
||||
#define DISP_CC_MDSS_BYTE0_CLK 4
|
||||
#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
|
||||
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
|
||||
#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
|
||||
#define DISP_CC_MDSS_BYTE1_CLK 8
|
||||
#define DISP_CC_MDSS_BYTE1_CLK_SRC 9
|
||||
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10
|
||||
#define DISP_CC_MDSS_BYTE1_INTF_CLK 11
|
||||
#define DISP_CC_MDSS_DPTX0_AUX_CLK 12
|
||||
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13
|
||||
#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 14
|
||||
#define DISP_CC_MDSS_DPTX0_LINK_CLK 15
|
||||
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16
|
||||
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17
|
||||
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18
|
||||
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19
|
||||
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20
|
||||
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21
|
||||
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22
|
||||
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 23
|
||||
#define DISP_CC_MDSS_DPTX1_AUX_CLK 24
|
||||
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 25
|
||||
#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 26
|
||||
#define DISP_CC_MDSS_DPTX1_LINK_CLK 27
|
||||
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 28
|
||||
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 29
|
||||
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 30
|
||||
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 31
|
||||
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 32
|
||||
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 33
|
||||
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 34
|
||||
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 35
|
||||
#define DISP_CC_MDSS_DPTX2_AUX_CLK 36
|
||||
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 37
|
||||
#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 38
|
||||
#define DISP_CC_MDSS_DPTX2_LINK_CLK 39
|
||||
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 40
|
||||
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 41
|
||||
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 42
|
||||
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 43
|
||||
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 44
|
||||
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 45
|
||||
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 46
|
||||
#define DISP_CC_MDSS_DPTX3_AUX_CLK 47
|
||||
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 48
|
||||
#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 49
|
||||
#define DISP_CC_MDSS_DPTX3_LINK_CLK 50
|
||||
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 51
|
||||
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 52
|
||||
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 53
|
||||
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 54
|
||||
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 55
|
||||
#define DISP_CC_MDSS_ESC0_CLK 56
|
||||
#define DISP_CC_MDSS_ESC0_CLK_SRC 57
|
||||
#define DISP_CC_MDSS_ESC1_CLK 58
|
||||
#define DISP_CC_MDSS_ESC1_CLK_SRC 59
|
||||
#define DISP_CC_MDSS_MDP1_CLK 60
|
||||
#define DISP_CC_MDSS_MDP_CLK 61
|
||||
#define DISP_CC_MDSS_MDP_CLK_SRC 62
|
||||
#define DISP_CC_MDSS_MDP_LUT1_CLK 63
|
||||
#define DISP_CC_MDSS_MDP_LUT_CLK 64
|
||||
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 65
|
||||
#define DISP_CC_MDSS_PCLK0_CLK 66
|
||||
#define DISP_CC_MDSS_PCLK0_CLK_SRC 67
|
||||
#define DISP_CC_MDSS_PCLK1_CLK 68
|
||||
#define DISP_CC_MDSS_PCLK1_CLK_SRC 69
|
||||
#define DISP_CC_MDSS_RSCC_AHB_CLK 70
|
||||
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 71
|
||||
#define DISP_CC_MDSS_VSYNC1_CLK 72
|
||||
#define DISP_CC_MDSS_VSYNC_CLK 73
|
||||
#define DISP_CC_MDSS_VSYNC_CLK_SRC 74
|
||||
#define DISP_CC_PLL0 75
|
||||
#define DISP_CC_PLL1 76
|
||||
#define DISP_CC_SLEEP_CLK 77
|
||||
#define DISP_CC_SLEEP_CLK_SRC 78
|
||||
#define DISP_CC_XO_CLK 79
|
||||
#define DISP_CC_XO_CLK_SRC 80
|
||||
|
||||
/* DISP_CC resets */
|
||||
#define DISP_CC_MDSS_CORE_BCR 0
|
||||
#define DISP_CC_MDSS_CORE_INT2_BCR 1
|
||||
#define DISP_CC_MDSS_RSCC_BCR 2
|
||||
|
||||
/* DISP_CC GDSCR */
|
||||
#define MDSS_GDSC 0
|
||||
#define MDSS_INT2_GDSC 1
|
||||
|
||||
#endif
|
||||
1
include/dt-bindings/clock/qcom,sm8650-dispcc.h
Symbolic link
1
include/dt-bindings/clock/qcom,sm8650-dispcc.h
Symbolic link
@ -0,0 +1 @@
|
||||
qcom,sm8550-dispcc.h
|
||||
@ -94,8 +94,6 @@
|
||||
#define HCLK_CPU 477
|
||||
#define HCLK_PERI 478
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_PERI + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0 0
|
||||
#define SRST_CORE1 1
|
||||
|
||||
@ -146,8 +146,6 @@
|
||||
#define HCLK_S_CRYPTO 477
|
||||
#define HCLK_PERI 478
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_PERI + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0_PO 0
|
||||
#define SRST_CORE1_PO 1
|
||||
|
||||
@ -195,8 +195,6 @@
|
||||
#define HCLK_CPU 477
|
||||
#define HCLK_PERI 478
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_PERI + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0 0
|
||||
#define SRST_CORE1 1
|
||||
|
||||
@ -212,8 +212,6 @@
|
||||
#define PCLK_CAN 233
|
||||
#define PCLK_OWIRE 234
|
||||
|
||||
#define CLK_NR_CLKS (PCLK_OWIRE + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
|
||||
/* cru_softrst_con0 */
|
||||
|
||||
@ -201,8 +201,6 @@
|
||||
#define HCLK_RGA 340
|
||||
#define HCLK_HDCP 341
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_HDCP + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0_PO 0
|
||||
#define SRST_CORE1_PO 1
|
||||
|
||||
@ -182,8 +182,6 @@
|
||||
#define HCLK_BUS 477
|
||||
#define HCLK_PERI 478
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_PERI + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE_B0 0
|
||||
#define SRST_CORE_B1 1
|
||||
|
||||
@ -335,8 +335,6 @@
|
||||
#define HCLK_SDIO_NOC 495
|
||||
#define HCLK_SDIOAUDIO_NOC 496
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1)
|
||||
|
||||
/* pmu-clocks indices */
|
||||
|
||||
#define PLL_PPLL 1
|
||||
@ -378,8 +376,6 @@
|
||||
#define PCLK_INTR_ARB_PMU 49
|
||||
#define HCLK_NOC_PMU 50
|
||||
|
||||
#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
|
||||
/* cru_softrst_con0 */
|
||||
|
||||
592
include/dt-bindings/clock/rockchip,rk3576-cru.h
Normal file
592
include/dt-bindings/clock/rockchip,rk3576-cru.h
Normal file
@ -0,0 +1,592 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co. Ltd.
|
||||
* Copyright (c) 2024 Collabora Ltd.
|
||||
*
|
||||
* Author: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
* Author: Detlev Casanova <detlev.casanova@collabora.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H
|
||||
|
||||
/* cru-clocks indices */
|
||||
|
||||
/* cru plls */
|
||||
#define PLL_BPLL 0
|
||||
#define PLL_LPLL 1
|
||||
#define PLL_VPLL 2
|
||||
#define PLL_AUPLL 3
|
||||
#define PLL_CPLL 4
|
||||
#define PLL_GPLL 5
|
||||
#define PLL_PPLL 6
|
||||
#define ARMCLK_L 7
|
||||
#define ARMCLK_B 8
|
||||
|
||||
/* cru clocks */
|
||||
#define CLK_CPLL_DIV20 9
|
||||
#define CLK_CPLL_DIV10 10
|
||||
#define CLK_GPLL_DIV8 11
|
||||
#define CLK_GPLL_DIV6 12
|
||||
#define CLK_CPLL_DIV4 13
|
||||
#define CLK_GPLL_DIV4 14
|
||||
#define CLK_SPLL_DIV2 15
|
||||
#define CLK_GPLL_DIV3 16
|
||||
#define CLK_CPLL_DIV2 17
|
||||
#define CLK_GPLL_DIV2 18
|
||||
#define CLK_SPLL_DIV1 19
|
||||
#define PCLK_TOP_ROOT 20
|
||||
#define ACLK_TOP 21
|
||||
#define HCLK_TOP 22
|
||||
#define CLK_AUDIO_FRAC_0 23
|
||||
#define CLK_AUDIO_FRAC_1 24
|
||||
#define CLK_AUDIO_FRAC_2 25
|
||||
#define CLK_AUDIO_FRAC_3 26
|
||||
#define CLK_UART_FRAC_0 27
|
||||
#define CLK_UART_FRAC_1 28
|
||||
#define CLK_UART_FRAC_2 29
|
||||
#define CLK_UART1_SRC_TOP 30
|
||||
#define CLK_AUDIO_INT_0 31
|
||||
#define CLK_AUDIO_INT_1 32
|
||||
#define CLK_AUDIO_INT_2 33
|
||||
#define CLK_PDM0_SRC_TOP 34
|
||||
#define CLK_PDM1_OUT 35
|
||||
#define CLK_GMAC0_125M_SRC 36
|
||||
#define CLK_GMAC1_125M_SRC 37
|
||||
#define LCLK_ASRC_SRC_0 38
|
||||
#define LCLK_ASRC_SRC_1 39
|
||||
#define REF_CLK0_OUT_PLL 40
|
||||
#define REF_CLK1_OUT_PLL 41
|
||||
#define REF_CLK2_OUT_PLL 42
|
||||
#define REFCLKO25M_GMAC0_OUT 43
|
||||
#define REFCLKO25M_GMAC1_OUT 44
|
||||
#define CLK_CIFOUT_OUT 45
|
||||
#define CLK_GMAC0_RMII_CRU 46
|
||||
#define CLK_GMAC1_RMII_CRU 47
|
||||
#define CLK_OTPC_AUTO_RD_G 48
|
||||
#define CLK_OTP_PHY_G 49
|
||||
#define CLK_MIPI_CAMERAOUT_M0 50
|
||||
#define CLK_MIPI_CAMERAOUT_M1 51
|
||||
#define CLK_MIPI_CAMERAOUT_M2 52
|
||||
#define MCLK_PDM0_SRC_TOP 53
|
||||
#define HCLK_AUDIO_ROOT 54
|
||||
#define HCLK_ASRC_2CH_0 55
|
||||
#define HCLK_ASRC_2CH_1 56
|
||||
#define HCLK_ASRC_4CH_0 57
|
||||
#define HCLK_ASRC_4CH_1 58
|
||||
#define CLK_ASRC_2CH_0 59
|
||||
#define CLK_ASRC_2CH_1 60
|
||||
#define CLK_ASRC_4CH_0 61
|
||||
#define CLK_ASRC_4CH_1 62
|
||||
#define MCLK_SAI0_8CH_SRC 63
|
||||
#define MCLK_SAI0_8CH 64
|
||||
#define HCLK_SAI0_8CH 65
|
||||
#define HCLK_SPDIF_RX0 66
|
||||
#define MCLK_SPDIF_RX0 67
|
||||
#define HCLK_SPDIF_RX1 68
|
||||
#define MCLK_SPDIF_RX1 69
|
||||
#define MCLK_SAI1_8CH_SRC 70
|
||||
#define MCLK_SAI1_8CH 71
|
||||
#define HCLK_SAI1_8CH 72
|
||||
#define MCLK_SAI2_2CH_SRC 73
|
||||
#define MCLK_SAI2_2CH 74
|
||||
#define HCLK_SAI2_2CH 75
|
||||
#define MCLK_SAI3_2CH_SRC 76
|
||||
#define MCLK_SAI3_2CH 77
|
||||
#define HCLK_SAI3_2CH 78
|
||||
#define MCLK_SAI4_2CH_SRC 79
|
||||
#define MCLK_SAI4_2CH 80
|
||||
#define HCLK_SAI4_2CH 81
|
||||
#define HCLK_ACDCDIG_DSM 82
|
||||
#define MCLK_ACDCDIG_DSM 83
|
||||
#define CLK_PDM1 84
|
||||
#define HCLK_PDM1 85
|
||||
#define MCLK_PDM1 86
|
||||
#define HCLK_SPDIF_TX0 87
|
||||
#define MCLK_SPDIF_TX0 88
|
||||
#define HCLK_SPDIF_TX1 89
|
||||
#define MCLK_SPDIF_TX1 90
|
||||
#define CLK_SAI1_MCLKOUT 91
|
||||
#define CLK_SAI2_MCLKOUT 92
|
||||
#define CLK_SAI3_MCLKOUT 93
|
||||
#define CLK_SAI4_MCLKOUT 94
|
||||
#define CLK_SAI0_MCLKOUT 95
|
||||
#define HCLK_BUS_ROOT 96
|
||||
#define PCLK_BUS_ROOT 97
|
||||
#define ACLK_BUS_ROOT 98
|
||||
#define HCLK_CAN0 99
|
||||
#define CLK_CAN0 100
|
||||
#define HCLK_CAN1 101
|
||||
#define CLK_CAN1 102
|
||||
#define CLK_KEY_SHIFT 103
|
||||
#define PCLK_I2C1 104
|
||||
#define PCLK_I2C2 105
|
||||
#define PCLK_I2C3 106
|
||||
#define PCLK_I2C4 107
|
||||
#define PCLK_I2C5 108
|
||||
#define PCLK_I2C6 109
|
||||
#define PCLK_I2C7 110
|
||||
#define PCLK_I2C8 111
|
||||
#define PCLK_I2C9 112
|
||||
#define PCLK_WDT_BUSMCU 113
|
||||
#define TCLK_WDT_BUSMCU 114
|
||||
#define ACLK_GIC 115
|
||||
#define CLK_I2C1 116
|
||||
#define CLK_I2C2 117
|
||||
#define CLK_I2C3 118
|
||||
#define CLK_I2C4 119
|
||||
#define CLK_I2C5 120
|
||||
#define CLK_I2C6 121
|
||||
#define CLK_I2C7 122
|
||||
#define CLK_I2C8 123
|
||||
#define CLK_I2C9 124
|
||||
#define PCLK_SARADC 125
|
||||
#define CLK_SARADC 126
|
||||
#define PCLK_TSADC 127
|
||||
#define CLK_TSADC 128
|
||||
#define PCLK_UART0 129
|
||||
#define PCLK_UART2 130
|
||||
#define PCLK_UART3 131
|
||||
#define PCLK_UART4 132
|
||||
#define PCLK_UART5 133
|
||||
#define PCLK_UART6 134
|
||||
#define PCLK_UART7 135
|
||||
#define PCLK_UART8 136
|
||||
#define PCLK_UART9 137
|
||||
#define PCLK_UART10 138
|
||||
#define PCLK_UART11 139
|
||||
#define SCLK_UART0 140
|
||||
#define SCLK_UART2 141
|
||||
#define SCLK_UART3 142
|
||||
#define SCLK_UART4 143
|
||||
#define SCLK_UART5 144
|
||||
#define SCLK_UART6 145
|
||||
#define SCLK_UART7 146
|
||||
#define SCLK_UART8 147
|
||||
#define SCLK_UART9 148
|
||||
#define SCLK_UART10 149
|
||||
#define SCLK_UART11 150
|
||||
#define PCLK_SPI0 151
|
||||
#define PCLK_SPI1 152
|
||||
#define PCLK_SPI2 153
|
||||
#define PCLK_SPI3 154
|
||||
#define PCLK_SPI4 155
|
||||
#define CLK_SPI0 156
|
||||
#define CLK_SPI1 157
|
||||
#define CLK_SPI2 158
|
||||
#define CLK_SPI3 159
|
||||
#define CLK_SPI4 160
|
||||
#define PCLK_WDT0 161
|
||||
#define TCLK_WDT0 162
|
||||
#define PCLK_PWM1 163
|
||||
#define CLK_PWM1 164
|
||||
#define CLK_OSC_PWM1 165
|
||||
#define CLK_RC_PWM1 166
|
||||
#define PCLK_BUSTIMER0 167
|
||||
#define PCLK_BUSTIMER1 168
|
||||
#define CLK_TIMER0_ROOT 169
|
||||
#define CLK_TIMER0 170
|
||||
#define CLK_TIMER1 171
|
||||
#define CLK_TIMER2 172
|
||||
#define CLK_TIMER3 173
|
||||
#define CLK_TIMER4 174
|
||||
#define CLK_TIMER5 175
|
||||
#define PCLK_MAILBOX0 176
|
||||
#define PCLK_GPIO1 177
|
||||
#define DBCLK_GPIO1 178
|
||||
#define PCLK_GPIO2 179
|
||||
#define DBCLK_GPIO2 180
|
||||
#define PCLK_GPIO3 181
|
||||
#define DBCLK_GPIO3 182
|
||||
#define PCLK_GPIO4 183
|
||||
#define DBCLK_GPIO4 184
|
||||
#define ACLK_DECOM 185
|
||||
#define PCLK_DECOM 186
|
||||
#define DCLK_DECOM 187
|
||||
#define CLK_TIMER1_ROOT 188
|
||||
#define CLK_TIMER6 189
|
||||
#define CLK_TIMER7 190
|
||||
#define CLK_TIMER8 191
|
||||
#define CLK_TIMER9 192
|
||||
#define CLK_TIMER10 193
|
||||
#define CLK_TIMER11 194
|
||||
#define ACLK_DMAC0 195
|
||||
#define ACLK_DMAC1 196
|
||||
#define ACLK_DMAC2 197
|
||||
#define ACLK_SPINLOCK 198
|
||||
#define HCLK_I3C0 199
|
||||
#define HCLK_I3C1 200
|
||||
#define HCLK_BUS_CM0_ROOT 201
|
||||
#define FCLK_BUS_CM0_CORE 202
|
||||
#define CLK_BUS_CM0_RTC 203
|
||||
#define PCLK_PMU2 204
|
||||
#define PCLK_PWM2 205
|
||||
#define CLK_PWM2 206
|
||||
#define CLK_RC_PWM2 207
|
||||
#define CLK_OSC_PWM2 208
|
||||
#define CLK_FREQ_PWM1 209
|
||||
#define CLK_COUNTER_PWM1 210
|
||||
#define SAI_SCLKIN_FREQ 211
|
||||
#define SAI_SCLKIN_COUNTER 212
|
||||
#define CLK_I3C0 213
|
||||
#define CLK_I3C1 214
|
||||
#define PCLK_CSIDPHY1 215
|
||||
#define PCLK_DDR_ROOT 216
|
||||
#define PCLK_DDR_MON_CH0 217
|
||||
#define TMCLK_DDR_MON_CH0 218
|
||||
#define ACLK_DDR_ROOT 219
|
||||
#define HCLK_DDR_ROOT 220
|
||||
#define FCLK_DDR_CM0_CORE 221
|
||||
#define CLK_DDR_TIMER_ROOT 222
|
||||
#define CLK_DDR_TIMER0 223
|
||||
#define CLK_DDR_TIMER1 224
|
||||
#define TCLK_WDT_DDR 225
|
||||
#define PCLK_WDT 226
|
||||
#define PCLK_TIMER 227
|
||||
#define CLK_DDR_CM0_RTC 228
|
||||
#define ACLK_RKNN0 229
|
||||
#define ACLK_RKNN1 230
|
||||
#define HCLK_RKNN_ROOT 231
|
||||
#define CLK_RKNN_DSU0 232
|
||||
#define PCLK_NPUTOP_ROOT 233
|
||||
#define PCLK_NPU_TIMER 234
|
||||
#define CLK_NPUTIMER_ROOT 235
|
||||
#define CLK_NPUTIMER0 236
|
||||
#define CLK_NPUTIMER1 237
|
||||
#define PCLK_NPU_WDT 238
|
||||
#define TCLK_NPU_WDT 239
|
||||
#define ACLK_RKNN_CBUF 240
|
||||
#define HCLK_NPU_CM0_ROOT 241
|
||||
#define FCLK_NPU_CM0_CORE 242
|
||||
#define CLK_NPU_CM0_RTC 243
|
||||
#define HCLK_RKNN_CBUF 244
|
||||
#define HCLK_NVM_ROOT 245
|
||||
#define ACLK_NVM_ROOT 246
|
||||
#define SCLK_FSPI_X2 247
|
||||
#define HCLK_FSPI 248
|
||||
#define CCLK_SRC_EMMC 249
|
||||
#define HCLK_EMMC 250
|
||||
#define ACLK_EMMC 251
|
||||
#define BCLK_EMMC 252
|
||||
#define TCLK_EMMC 253
|
||||
#define PCLK_PHP_ROOT 254
|
||||
#define ACLK_PHP_ROOT 255
|
||||
#define PCLK_PCIE0 256
|
||||
#define CLK_PCIE0_AUX 257
|
||||
#define ACLK_PCIE0_MST 258
|
||||
#define ACLK_PCIE0_SLV 259
|
||||
#define ACLK_PCIE0_DBI 260
|
||||
#define ACLK_USB3OTG1 261
|
||||
#define CLK_REF_USB3OTG1 262
|
||||
#define CLK_SUSPEND_USB3OTG1 263
|
||||
#define ACLK_MMU0 264
|
||||
#define ACLK_SLV_MMU0 265
|
||||
#define ACLK_MMU1 266
|
||||
#define ACLK_SLV_MMU1 267
|
||||
#define PCLK_PCIE1 268
|
||||
#define CLK_PCIE1_AUX 269
|
||||
#define ACLK_PCIE1_MST 270
|
||||
#define ACLK_PCIE1_SLV 271
|
||||
#define ACLK_PCIE1_DBI 272
|
||||
#define CLK_RXOOB0 273
|
||||
#define CLK_RXOOB1 274
|
||||
#define CLK_PMALIVE0 275
|
||||
#define CLK_PMALIVE1 276
|
||||
#define ACLK_SATA0 277
|
||||
#define ACLK_SATA1 278
|
||||
#define CLK_USB3OTG1_PIPE_PCLK 279
|
||||
#define CLK_USB3OTG1_UTMI 280
|
||||
#define CLK_USB3OTG0_PIPE_PCLK 281
|
||||
#define CLK_USB3OTG0_UTMI 282
|
||||
#define HCLK_SDGMAC_ROOT 283
|
||||
#define ACLK_SDGMAC_ROOT 284
|
||||
#define PCLK_SDGMAC_ROOT 285
|
||||
#define ACLK_GMAC0 286
|
||||
#define ACLK_GMAC1 287
|
||||
#define PCLK_GMAC0 288
|
||||
#define PCLK_GMAC1 289
|
||||
#define CCLK_SRC_SDIO 290
|
||||
#define HCLK_SDIO 291
|
||||
#define CLK_GMAC1_PTP_REF 292
|
||||
#define CLK_GMAC0_PTP_REF 293
|
||||
#define CLK_GMAC1_PTP_REF_SRC 294
|
||||
#define CLK_GMAC0_PTP_REF_SRC 295
|
||||
#define CCLK_SRC_SDMMC0 296
|
||||
#define HCLK_SDMMC0 297
|
||||
#define SCLK_FSPI1_X2 298
|
||||
#define HCLK_FSPI1 299
|
||||
#define ACLK_DSMC_ROOT 300
|
||||
#define ACLK_DSMC 301
|
||||
#define PCLK_DSMC 302
|
||||
#define CLK_DSMC_SYS 303
|
||||
#define HCLK_HSGPIO 304
|
||||
#define CLK_HSGPIO_TX 305
|
||||
#define CLK_HSGPIO_RX 306
|
||||
#define ACLK_HSGPIO 307
|
||||
#define PCLK_PHPPHY_ROOT 308
|
||||
#define PCLK_PCIE2_COMBOPHY0 309
|
||||
#define PCLK_PCIE2_COMBOPHY1 310
|
||||
#define CLK_PCIE_100M_SRC 311
|
||||
#define CLK_PCIE_100M_NDUTY_SRC 312
|
||||
#define CLK_REF_PCIE0_PHY 313
|
||||
#define CLK_REF_PCIE1_PHY 314
|
||||
#define CLK_REF_MPHY_26M 315
|
||||
#define HCLK_RKVDEC_ROOT 316
|
||||
#define ACLK_RKVDEC_ROOT 317
|
||||
#define HCLK_RKVDEC 318
|
||||
#define CLK_RKVDEC_HEVC_CA 319
|
||||
#define CLK_RKVDEC_CORE 320
|
||||
#define ACLK_UFS_ROOT 321
|
||||
#define ACLK_USB_ROOT 322
|
||||
#define PCLK_USB_ROOT 323
|
||||
#define ACLK_USB3OTG0 324
|
||||
#define CLK_REF_USB3OTG0 325
|
||||
#define CLK_SUSPEND_USB3OTG0 326
|
||||
#define ACLK_MMU2 327
|
||||
#define ACLK_SLV_MMU2 328
|
||||
#define ACLK_UFS_SYS 329
|
||||
#define ACLK_VPU_ROOT 330
|
||||
#define ACLK_VPU_MID_ROOT 331
|
||||
#define HCLK_VPU_ROOT 332
|
||||
#define ACLK_JPEG_ROOT 333
|
||||
#define ACLK_VPU_LOW_ROOT 334
|
||||
#define HCLK_RGA2E_0 335
|
||||
#define ACLK_RGA2E_0 336
|
||||
#define CLK_CORE_RGA2E_0 337
|
||||
#define ACLK_JPEG 338
|
||||
#define HCLK_JPEG 339
|
||||
#define HCLK_VDPP 340
|
||||
#define ACLK_VDPP 341
|
||||
#define CLK_CORE_VDPP 342
|
||||
#define HCLK_RGA2E_1 343
|
||||
#define ACLK_RGA2E_1 344
|
||||
#define CLK_CORE_RGA2E_1 345
|
||||
#define DCLK_EBC_FRAC_SRC 346
|
||||
#define HCLK_EBC 347
|
||||
#define ACLK_EBC 348
|
||||
#define DCLK_EBC 349
|
||||
#define HCLK_VEPU0_ROOT 350
|
||||
#define ACLK_VEPU0_ROOT 351
|
||||
#define HCLK_VEPU0 352
|
||||
#define ACLK_VEPU0 353
|
||||
#define CLK_VEPU0_CORE 354
|
||||
#define ACLK_VI_ROOT 355
|
||||
#define HCLK_VI_ROOT 356
|
||||
#define PCLK_VI_ROOT 357
|
||||
#define DCLK_VICAP 358
|
||||
#define ACLK_VICAP 359
|
||||
#define HCLK_VICAP 360
|
||||
#define CLK_ISP_CORE 361
|
||||
#define CLK_ISP_CORE_MARVIN 362
|
||||
#define CLK_ISP_CORE_VICAP 363
|
||||
#define ACLK_ISP 364
|
||||
#define HCLK_ISP 365
|
||||
#define ACLK_VPSS 366
|
||||
#define HCLK_VPSS 367
|
||||
#define CLK_CORE_VPSS 368
|
||||
#define PCLK_CSI_HOST_0 369
|
||||
#define PCLK_CSI_HOST_1 370
|
||||
#define PCLK_CSI_HOST_2 371
|
||||
#define PCLK_CSI_HOST_3 372
|
||||
#define PCLK_CSI_HOST_4 373
|
||||
#define ICLK_CSIHOST01 374
|
||||
#define ICLK_CSIHOST0 375
|
||||
#define CLK_ISP_PVTPLL_SRC 376
|
||||
#define ACLK_VI_ROOT_INTER 377
|
||||
#define CLK_VICAP_I0CLK 378
|
||||
#define CLK_VICAP_I1CLK 379
|
||||
#define CLK_VICAP_I2CLK 380
|
||||
#define CLK_VICAP_I3CLK 381
|
||||
#define CLK_VICAP_I4CLK 382
|
||||
#define ACLK_VOP_ROOT 383
|
||||
#define HCLK_VOP_ROOT 384
|
||||
#define PCLK_VOP_ROOT 385
|
||||
#define HCLK_VOP 386
|
||||
#define ACLK_VOP 387
|
||||
#define DCLK_VP0_SRC 388
|
||||
#define DCLK_VP1_SRC 389
|
||||
#define DCLK_VP2_SRC 390
|
||||
#define DCLK_VP0 391
|
||||
#define DCLK_VP1 392
|
||||
#define DCLK_VP2 393
|
||||
#define PCLK_VOPGRF 394
|
||||
#define ACLK_VO0_ROOT 395
|
||||
#define HCLK_VO0_ROOT 396
|
||||
#define PCLK_VO0_ROOT 397
|
||||
#define PCLK_VO0_GRF 398
|
||||
#define ACLK_HDCP0 399
|
||||
#define HCLK_HDCP0 400
|
||||
#define PCLK_HDCP0 401
|
||||
#define CLK_TRNG0_SKP 402
|
||||
#define PCLK_DSIHOST0 403
|
||||
#define CLK_DSIHOST0 404
|
||||
#define PCLK_HDMITX0 405
|
||||
#define CLK_HDMITX0_EARC 406
|
||||
#define CLK_HDMITX0_REF 407
|
||||
#define PCLK_EDP0 408
|
||||
#define CLK_EDP0_24M 409
|
||||
#define CLK_EDP0_200M 410
|
||||
#define MCLK_SAI5_8CH_SRC 411
|
||||
#define MCLK_SAI5_8CH 412
|
||||
#define HCLK_SAI5_8CH 413
|
||||
#define MCLK_SAI6_8CH_SRC 414
|
||||
#define MCLK_SAI6_8CH 415
|
||||
#define HCLK_SAI6_8CH 416
|
||||
#define HCLK_SPDIF_TX2 417
|
||||
#define MCLK_SPDIF_TX2 418
|
||||
#define HCLK_SPDIF_RX2 419
|
||||
#define MCLK_SPDIF_RX2 420
|
||||
#define HCLK_SAI8_8CH 421
|
||||
#define MCLK_SAI8_8CH_SRC 422
|
||||
#define MCLK_SAI8_8CH 423
|
||||
#define ACLK_VO1_ROOT 424
|
||||
#define HCLK_VO1_ROOT 425
|
||||
#define PCLK_VO1_ROOT 426
|
||||
#define MCLK_SAI7_8CH_SRC 427
|
||||
#define MCLK_SAI7_8CH 428
|
||||
#define HCLK_SAI7_8CH 429
|
||||
#define HCLK_SPDIF_TX3 430
|
||||
#define HCLK_SPDIF_TX4 431
|
||||
#define HCLK_SPDIF_TX5 432
|
||||
#define MCLK_SPDIF_TX3 433
|
||||
#define CLK_AUX16MHZ_0 434
|
||||
#define ACLK_DP0 435
|
||||
#define PCLK_DP0 436
|
||||
#define PCLK_VO1_GRF 437
|
||||
#define ACLK_HDCP1 438
|
||||
#define HCLK_HDCP1 439
|
||||
#define PCLK_HDCP1 440
|
||||
#define CLK_TRNG1_SKP 441
|
||||
#define HCLK_SAI9_8CH 442
|
||||
#define MCLK_SAI9_8CH_SRC 443
|
||||
#define MCLK_SAI9_8CH 444
|
||||
#define MCLK_SPDIF_TX4 445
|
||||
#define MCLK_SPDIF_TX5 446
|
||||
#define CLK_GPU_SRC_PRE 447
|
||||
#define CLK_GPU 448
|
||||
#define PCLK_GPU_ROOT 449
|
||||
#define ACLK_CENTER_ROOT 450
|
||||
#define ACLK_CENTER_LOW_ROOT 451
|
||||
#define HCLK_CENTER_ROOT 452
|
||||
#define PCLK_CENTER_ROOT 453
|
||||
#define ACLK_DMA2DDR 454
|
||||
#define ACLK_DDR_SHAREMEM 455
|
||||
#define PCLK_DMA2DDR 456
|
||||
#define PCLK_SHAREMEM 457
|
||||
#define HCLK_VEPU1_ROOT 458
|
||||
#define ACLK_VEPU1_ROOT 459
|
||||
#define HCLK_VEPU1 460
|
||||
#define ACLK_VEPU1 461
|
||||
#define CLK_VEPU1_CORE 462
|
||||
#define CLK_JDBCK_DAP 463
|
||||
#define PCLK_MIPI_DCPHY 464
|
||||
#define CLK_32K_USB2DEBUG 465
|
||||
#define PCLK_CSIDPHY 466
|
||||
#define PCLK_USBDPPHY 467
|
||||
#define CLK_PMUPHY_REF_SRC 468
|
||||
#define CLK_USBDP_COMBO_PHY_IMMORTAL 469
|
||||
#define CLK_HDMITXHDP 470
|
||||
#define PCLK_MPHY 471
|
||||
#define CLK_REF_OSC_MPHY 472
|
||||
#define CLK_REF_UFS_CLKOUT 473
|
||||
#define HCLK_PMU1_ROOT 474
|
||||
#define HCLK_PMU_CM0_ROOT 475
|
||||
#define CLK_200M_PMU_SRC 476
|
||||
#define CLK_100M_PMU_SRC 477
|
||||
#define CLK_50M_PMU_SRC 478
|
||||
#define FCLK_PMU_CM0_CORE 479
|
||||
#define CLK_PMU_CM0_RTC 480
|
||||
#define PCLK_PMU1 481
|
||||
#define CLK_PMU1 482
|
||||
#define PCLK_PMU1WDT 483
|
||||
#define TCLK_PMU1WDT 484
|
||||
#define PCLK_PMUTIMER 485
|
||||
#define CLK_PMUTIMER_ROOT 486
|
||||
#define CLK_PMUTIMER0 487
|
||||
#define CLK_PMUTIMER1 488
|
||||
#define PCLK_PMU1PWM 489
|
||||
#define CLK_PMU1PWM 490
|
||||
#define CLK_PMU1PWM_OSC 491
|
||||
#define PCLK_PMUPHY_ROOT 492
|
||||
#define PCLK_I2C0 493
|
||||
#define CLK_I2C0 494
|
||||
#define SCLK_UART1 495
|
||||
#define PCLK_UART1 496
|
||||
#define CLK_PMU1PWM_RC 497
|
||||
#define CLK_PDM0 498
|
||||
#define HCLK_PDM0 499
|
||||
#define MCLK_PDM0 500
|
||||
#define HCLK_VAD 501
|
||||
#define CLK_OSCCHK_PVTM 502
|
||||
#define CLK_PDM0_OUT 503
|
||||
#define CLK_HPTIMER_SRC 504
|
||||
#define PCLK_PMU0_ROOT 505
|
||||
#define PCLK_PMU0 506
|
||||
#define PCLK_GPIO0 507
|
||||
#define DBCLK_GPIO0 508
|
||||
#define CLK_OSC0_PMU1 509
|
||||
#define PCLK_PMU1_ROOT 510
|
||||
#define XIN_OSC0_DIV 511
|
||||
#define ACLK_USB 512
|
||||
#define ACLK_UFS 513
|
||||
#define ACLK_SDGMAC 514
|
||||
#define HCLK_SDGMAC 515
|
||||
#define PCLK_SDGMAC 516
|
||||
#define HCLK_VO1 517
|
||||
#define HCLK_VO0 518
|
||||
#define PCLK_CCI_ROOT 519
|
||||
#define ACLK_CCI_ROOT 520
|
||||
#define HCLK_VO0VOP_CHANNEL 521
|
||||
#define ACLK_VO0VOP_CHANNEL 522
|
||||
#define ACLK_TOP_MID 523
|
||||
#define ACLK_SECURE_HIGH 524
|
||||
#define CLK_USBPHY_REF_SRC 525
|
||||
#define CLK_PHY_REF_SRC 526
|
||||
#define CLK_CPLL_REF_SRC 527
|
||||
#define CLK_AUPLL_REF_SRC 528
|
||||
#define PCLK_SECURE_NS 529
|
||||
#define HCLK_SECURE_NS 530
|
||||
#define ACLK_SECURE_NS 531
|
||||
#define PCLK_OTPC_NS 532
|
||||
#define HCLK_CRYPTO_NS 533
|
||||
#define HCLK_TRNG_NS 534
|
||||
#define CLK_OTPC_NS 535
|
||||
#define SCLK_DSU 536
|
||||
#define SCLK_DDR 537
|
||||
#define ACLK_CRYPTO_NS 538
|
||||
#define CLK_PKA_CRYPTO_NS 539
|
||||
#define ACLK_RKVDEC_ROOT_BAK 540
|
||||
#define CLK_AUDIO_FRAC_0_SRC 541
|
||||
#define CLK_AUDIO_FRAC_1_SRC 542
|
||||
#define CLK_AUDIO_FRAC_2_SRC 543
|
||||
#define CLK_AUDIO_FRAC_3_SRC 544
|
||||
#define PCLK_HDPTX_APB 545
|
||||
|
||||
/* secure clk */
|
||||
#define CLK_STIMER0_ROOT 546
|
||||
#define CLK_STIMER1_ROOT 547
|
||||
#define PCLK_SECURE_S 548
|
||||
#define HCLK_SECURE_S 549
|
||||
#define ACLK_SECURE_S 550
|
||||
#define CLK_PKA_CRYPTO_S 551
|
||||
#define HCLK_VO1_S 552
|
||||
#define PCLK_VO1_S 553
|
||||
#define HCLK_VO0_S 554
|
||||
#define PCLK_VO0_S 555
|
||||
#define PCLK_KLAD 556
|
||||
#define HCLK_CRYPTO_S 557
|
||||
#define HCLK_KLAD 558
|
||||
#define ACLK_CRYPTO_S 559
|
||||
#define HCLK_TRNG_S 560
|
||||
#define PCLK_OTPC_S 561
|
||||
#define CLK_OTPC_S 562
|
||||
#define PCLK_WDT_S 563
|
||||
#define TCLK_WDT_S 564
|
||||
#define PCLK_HDCP0_TRNG 565
|
||||
#define PCLK_HDCP1_TRNG 566
|
||||
#define HCLK_HDCP_KEY0 567
|
||||
#define HCLK_HDCP_KEY1 568
|
||||
#define PCLK_EDP_S 569
|
||||
#define ACLK_KLAD 570
|
||||
|
||||
#endif
|
||||
@ -179,6 +179,17 @@
|
||||
#define CLK_GOUT_CORE_CCI_PCLK 4
|
||||
#define CLK_GOUT_CORE_CMU_CORE_PCLK 5
|
||||
|
||||
/* CMU_DPUM */
|
||||
#define CLK_MOUT_DPUM_BUS_USER 1
|
||||
#define CLK_DOUT_DPUM_BUSP 2
|
||||
#define CLK_GOUT_DPUM_ACLK_DECON 3
|
||||
#define CLK_GOUT_DPUM_ACLK_DMA 4
|
||||
#define CLK_GOUT_DPUM_ACLK_DPP 5
|
||||
#define CLK_GOUT_DPUM_SYSMMU_D0_CLK 6
|
||||
#define CLK_GOUT_DPUM_SYSMMU_D1_CLK 7
|
||||
#define CLK_GOUT_DPUM_SYSMMU_D2_CLK 8
|
||||
#define CLK_GOUT_DPUM_SYSMMU_D3_CLK 9
|
||||
|
||||
/* CMU_FSYS0 */
|
||||
#define CLK_MOUT_FSYS0_BUS_USER 1
|
||||
#define CLK_MOUT_FSYS0_PCIE_USER 2
|
||||
|
||||
191
include/dt-bindings/clock/samsung,exynosautov920.h
Normal file
191
include/dt-bindings/clock/samsung,exynosautov920.h
Normal file
@ -0,0 +1,191 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2024 Samsung Electronics Co., Ltd.
|
||||
* Author: Sunyeal Hong <sunyeal.hong@samsung.com>
|
||||
*
|
||||
* Device Tree binding constants for ExynosAuto v920 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H
|
||||
|
||||
/* CMU_TOP */
|
||||
#define FOUT_SHARED0_PLL 1
|
||||
#define FOUT_SHARED1_PLL 2
|
||||
#define FOUT_SHARED2_PLL 3
|
||||
#define FOUT_SHARED3_PLL 4
|
||||
#define FOUT_SHARED4_PLL 5
|
||||
#define FOUT_SHARED5_PLL 6
|
||||
#define FOUT_MMC_PLL 7
|
||||
|
||||
/* MUX in CMU_TOP */
|
||||
#define MOUT_SHARED0_PLL 8
|
||||
#define MOUT_SHARED1_PLL 9
|
||||
#define MOUT_SHARED2_PLL 10
|
||||
#define MOUT_SHARED3_PLL 11
|
||||
#define MOUT_SHARED4_PLL 12
|
||||
#define MOUT_SHARED5_PLL 13
|
||||
#define MOUT_MMC_PLL 14
|
||||
#define MOUT_CLKCMU_CMU_BOOST 15
|
||||
#define MOUT_CLKCMU_CMU_CMUREF 16
|
||||
#define MOUT_CLKCMU_ACC_NOC 17
|
||||
#define MOUT_CLKCMU_ACC_ORB 18
|
||||
#define MOUT_CLKCMU_APM_NOC 19
|
||||
#define MOUT_CLKCMU_AUD_CPU 20
|
||||
#define MOUT_CLKCMU_AUD_NOC 21
|
||||
#define MOUT_CLKCMU_CPUCL0_SWITCH 22
|
||||
#define MOUT_CLKCMU_CPUCL0_CLUSTER 23
|
||||
#define MOUT_CLKCMU_CPUCL0_DBG 24
|
||||
#define MOUT_CLKCMU_CPUCL1_SWITCH 25
|
||||
#define MOUT_CLKCMU_CPUCL1_CLUSTER 26
|
||||
#define MOUT_CLKCMU_CPUCL2_SWITCH 27
|
||||
#define MOUT_CLKCMU_CPUCL2_CLUSTER 28
|
||||
#define MOUT_CLKCMU_DNC_NOC 29
|
||||
#define MOUT_CLKCMU_DPTX_NOC 30
|
||||
#define MOUT_CLKCMU_DPTX_DPGTC 31
|
||||
#define MOUT_CLKCMU_DPTX_DPOSC 32
|
||||
#define MOUT_CLKCMU_DPUB_NOC 33
|
||||
#define MOUT_CLKCMU_DPUB_DSIM 34
|
||||
#define MOUT_CLKCMU_DPUF0_NOC 35
|
||||
#define MOUT_CLKCMU_DPUF1_NOC 36
|
||||
#define MOUT_CLKCMU_DPUF2_NOC 37
|
||||
#define MOUT_CLKCMU_DSP_NOC 38
|
||||
#define MOUT_CLKCMU_G3D_SWITCH 39
|
||||
#define MOUT_CLKCMU_G3D_NOCP 40
|
||||
#define MOUT_CLKCMU_GNPU_NOC 41
|
||||
#define MOUT_CLKCMU_HSI0_NOC 42
|
||||
#define MOUT_CLKCMU_HSI1_NOC 43
|
||||
#define MOUT_CLKCMU_HSI1_USBDRD 44
|
||||
#define MOUT_CLKCMU_HSI1_MMC_CARD 45
|
||||
#define MOUT_CLKCMU_HSI2_NOC 46
|
||||
#define MOUT_CLKCMU_HSI2_NOC_UFS 47
|
||||
#define MOUT_CLKCMU_HSI2_UFS_EMBD 48
|
||||
#define MOUT_CLKCMU_HSI2_ETHERNET 49
|
||||
#define MOUT_CLKCMU_ISP_NOC 50
|
||||
#define MOUT_CLKCMU_M2M_NOC 51
|
||||
#define MOUT_CLKCMU_M2M_JPEG 52
|
||||
#define MOUT_CLKCMU_MFC_MFC 53
|
||||
#define MOUT_CLKCMU_MFC_WFD 54
|
||||
#define MOUT_CLKCMU_MFD_NOC 55
|
||||
#define MOUT_CLKCMU_MIF_SWITCH 56
|
||||
#define MOUT_CLKCMU_MIF_NOCP 57
|
||||
#define MOUT_CLKCMU_MISC_NOC 58
|
||||
#define MOUT_CLKCMU_NOCL0_NOC 59
|
||||
#define MOUT_CLKCMU_NOCL1_NOC 60
|
||||
#define MOUT_CLKCMU_NOCL2_NOC 61
|
||||
#define MOUT_CLKCMU_PERIC0_NOC 62
|
||||
#define MOUT_CLKCMU_PERIC0_IP 63
|
||||
#define MOUT_CLKCMU_PERIC1_NOC 64
|
||||
#define MOUT_CLKCMU_PERIC1_IP 65
|
||||
#define MOUT_CLKCMU_SDMA_NOC 66
|
||||
#define MOUT_CLKCMU_SNW_NOC 67
|
||||
#define MOUT_CLKCMU_SSP_NOC 68
|
||||
#define MOUT_CLKCMU_TAA_NOC 69
|
||||
|
||||
/* DIV in CMU_TOP */
|
||||
#define DOUT_SHARED0_DIV1 70
|
||||
#define DOUT_SHARED0_DIV2 71
|
||||
#define DOUT_SHARED0_DIV3 72
|
||||
#define DOUT_SHARED0_DIV4 73
|
||||
#define DOUT_SHARED1_DIV1 74
|
||||
#define DOUT_SHARED1_DIV2 75
|
||||
#define DOUT_SHARED1_DIV3 76
|
||||
#define DOUT_SHARED1_DIV4 77
|
||||
#define DOUT_SHARED2_DIV1 78
|
||||
#define DOUT_SHARED2_DIV2 79
|
||||
#define DOUT_SHARED2_DIV3 80
|
||||
#define DOUT_SHARED2_DIV4 81
|
||||
#define DOUT_SHARED3_DIV1 82
|
||||
#define DOUT_SHARED3_DIV2 83
|
||||
#define DOUT_SHARED3_DIV3 84
|
||||
#define DOUT_SHARED3_DIV4 85
|
||||
#define DOUT_SHARED4_DIV1 86
|
||||
#define DOUT_SHARED4_DIV2 87
|
||||
#define DOUT_SHARED4_DIV3 88
|
||||
#define DOUT_SHARED4_DIV4 89
|
||||
#define DOUT_SHARED5_DIV1 90
|
||||
#define DOUT_SHARED5_DIV2 91
|
||||
#define DOUT_SHARED5_DIV3 92
|
||||
#define DOUT_SHARED5_DIV4 93
|
||||
#define DOUT_CLKCMU_CMU_BOOST 94
|
||||
#define DOUT_CLKCMU_ACC_NOC 95
|
||||
#define DOUT_CLKCMU_ACC_ORB 96
|
||||
#define DOUT_CLKCMU_APM_NOC 97
|
||||
#define DOUT_CLKCMU_AUD_CPU 98
|
||||
#define DOUT_CLKCMU_AUD_NOC 99
|
||||
#define DOUT_CLKCMU_CPUCL0_SWITCH 100
|
||||
#define DOUT_CLKCMU_CPUCL0_CLUSTER 101
|
||||
#define DOUT_CLKCMU_CPUCL0_DBG 102
|
||||
#define DOUT_CLKCMU_CPUCL1_SWITCH 103
|
||||
#define DOUT_CLKCMU_CPUCL1_CLUSTER 104
|
||||
#define DOUT_CLKCMU_CPUCL2_SWITCH 105
|
||||
#define DOUT_CLKCMU_CPUCL2_CLUSTER 106
|
||||
#define DOUT_CLKCMU_DNC_NOC 107
|
||||
#define DOUT_CLKCMU_DPTX_NOC 108
|
||||
#define DOUT_CLKCMU_DPTX_DPGTC 109
|
||||
#define DOUT_CLKCMU_DPTX_DPOSC 110
|
||||
#define DOUT_CLKCMU_DPUB_NOC 111
|
||||
#define DOUT_CLKCMU_DPUB_DSIM 112
|
||||
#define DOUT_CLKCMU_DPUF0_NOC 113
|
||||
#define DOUT_CLKCMU_DPUF1_NOC 114
|
||||
#define DOUT_CLKCMU_DPUF2_NOC 115
|
||||
#define DOUT_CLKCMU_DSP_NOC 116
|
||||
#define DOUT_CLKCMU_G3D_SWITCH 117
|
||||
#define DOUT_CLKCMU_G3D_NOCP 118
|
||||
#define DOUT_CLKCMU_GNPU_NOC 119
|
||||
#define DOUT_CLKCMU_HSI0_NOC 120
|
||||
#define DOUT_CLKCMU_HSI1_NOC 121
|
||||
#define DOUT_CLKCMU_HSI1_USBDRD 122
|
||||
#define DOUT_CLKCMU_HSI1_MMC_CARD 123
|
||||
#define DOUT_CLKCMU_HSI2_NOC 124
|
||||
#define DOUT_CLKCMU_HSI2_NOC_UFS 125
|
||||
#define DOUT_CLKCMU_HSI2_UFS_EMBD 126
|
||||
#define DOUT_CLKCMU_HSI2_ETHERNET 127
|
||||
#define DOUT_CLKCMU_ISP_NOC 128
|
||||
#define DOUT_CLKCMU_M2M_NOC 129
|
||||
#define DOUT_CLKCMU_M2M_JPEG 130
|
||||
#define DOUT_CLKCMU_MFC_MFC 131
|
||||
#define DOUT_CLKCMU_MFC_WFD 132
|
||||
#define DOUT_CLKCMU_MFD_NOC 133
|
||||
#define DOUT_CLKCMU_MIF_NOCP 134
|
||||
#define DOUT_CLKCMU_MISC_NOC 135
|
||||
#define DOUT_CLKCMU_NOCL0_NOC 136
|
||||
#define DOUT_CLKCMU_NOCL1_NOC 137
|
||||
#define DOUT_CLKCMU_NOCL2_NOC 138
|
||||
#define DOUT_CLKCMU_PERIC0_NOC 139
|
||||
#define DOUT_CLKCMU_PERIC0_IP 140
|
||||
#define DOUT_CLKCMU_PERIC1_NOC 141
|
||||
#define DOUT_CLKCMU_PERIC1_IP 142
|
||||
#define DOUT_CLKCMU_SDMA_NOC 143
|
||||
#define DOUT_CLKCMU_SNW_NOC 144
|
||||
#define DOUT_CLKCMU_SSP_NOC 145
|
||||
#define DOUT_CLKCMU_TAA_NOC 146
|
||||
|
||||
/* CMU_PERIC0 */
|
||||
#define CLK_MOUT_PERIC0_IP_USER 1
|
||||
#define CLK_MOUT_PERIC0_NOC_USER 2
|
||||
#define CLK_MOUT_PERIC0_USI00_USI 3
|
||||
#define CLK_MOUT_PERIC0_USI01_USI 4
|
||||
#define CLK_MOUT_PERIC0_USI02_USI 5
|
||||
#define CLK_MOUT_PERIC0_USI03_USI 6
|
||||
#define CLK_MOUT_PERIC0_USI04_USI 7
|
||||
#define CLK_MOUT_PERIC0_USI05_USI 8
|
||||
#define CLK_MOUT_PERIC0_USI06_USI 9
|
||||
#define CLK_MOUT_PERIC0_USI07_USI 10
|
||||
#define CLK_MOUT_PERIC0_USI08_USI 11
|
||||
#define CLK_MOUT_PERIC0_USI_I2C 12
|
||||
#define CLK_MOUT_PERIC0_I3C 13
|
||||
|
||||
#define CLK_DOUT_PERIC0_USI00_USI 14
|
||||
#define CLK_DOUT_PERIC0_USI01_USI 15
|
||||
#define CLK_DOUT_PERIC0_USI02_USI 16
|
||||
#define CLK_DOUT_PERIC0_USI03_USI 17
|
||||
#define CLK_DOUT_PERIC0_USI04_USI 18
|
||||
#define CLK_DOUT_PERIC0_USI05_USI 19
|
||||
#define CLK_DOUT_PERIC0_USI06_USI 20
|
||||
#define CLK_DOUT_PERIC0_USI07_USI 21
|
||||
#define CLK_DOUT_PERIC0_USI08_USI 22
|
||||
#define CLK_DOUT_PERIC0_USI_I2C 23
|
||||
#define CLK_DOUT_PERIC0_I3C 24
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */
|
||||
46
include/dt-bindings/interconnect/qcom,ipq5332.h
Normal file
46
include/dt-bindings/interconnect/qcom,ipq5332.h
Normal file
@ -0,0 +1,46 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
#ifndef INTERCONNECT_QCOM_IPQ5332_H
|
||||
#define INTERCONNECT_QCOM_IPQ5332_H
|
||||
|
||||
#define MASTER_SNOC_PCIE3_1_M 0
|
||||
#define SLAVE_SNOC_PCIE3_1_M 1
|
||||
#define MASTER_ANOC_PCIE3_1_S 2
|
||||
#define SLAVE_ANOC_PCIE3_1_S 3
|
||||
#define MASTER_SNOC_PCIE3_2_M 4
|
||||
#define SLAVE_SNOC_PCIE3_2_M 5
|
||||
#define MASTER_ANOC_PCIE3_2_S 6
|
||||
#define SLAVE_ANOC_PCIE3_2_S 7
|
||||
#define MASTER_SNOC_USB 8
|
||||
#define SLAVE_SNOC_USB 9
|
||||
#define MASTER_NSSNOC_NSSCC 10
|
||||
#define SLAVE_NSSNOC_NSSCC 11
|
||||
#define MASTER_NSSNOC_SNOC_0 12
|
||||
#define SLAVE_NSSNOC_SNOC_0 13
|
||||
#define MASTER_NSSNOC_SNOC_1 14
|
||||
#define SLAVE_NSSNOC_SNOC_1 15
|
||||
#define MASTER_NSSNOC_ATB 16
|
||||
#define SLAVE_NSSNOC_ATB 17
|
||||
#define MASTER_NSSNOC_PCNOC_1 18
|
||||
#define SLAVE_NSSNOC_PCNOC_1 19
|
||||
#define MASTER_NSSNOC_QOSGEN_REF 20
|
||||
#define SLAVE_NSSNOC_QOSGEN_REF 21
|
||||
#define MASTER_NSSNOC_TIMEOUT_REF 22
|
||||
#define SLAVE_NSSNOC_TIMEOUT_REF 23
|
||||
#define MASTER_NSSNOC_XO_DCD 24
|
||||
#define SLAVE_NSSNOC_XO_DCD 25
|
||||
|
||||
#define MASTER_NSSNOC_PPE 0
|
||||
#define SLAVE_NSSNOC_PPE 1
|
||||
#define MASTER_NSSNOC_PPE_CFG 2
|
||||
#define SLAVE_NSSNOC_PPE_CFG 3
|
||||
#define MASTER_NSSNOC_NSS_CSR 4
|
||||
#define SLAVE_NSSNOC_NSS_CSR 5
|
||||
#define MASTER_NSSNOC_CE_APB 6
|
||||
#define SLAVE_NSSNOC_CE_APB 7
|
||||
#define MASTER_NSSNOC_CE_AXI 8
|
||||
#define SLAVE_NSSNOC_CE_AXI 9
|
||||
|
||||
#define MASTER_CNOC_AHB 0
|
||||
#define SLAVE_CNOC_AHB 1
|
||||
|
||||
#endif /* INTERCONNECT_QCOM_IPQ5332_H */
|
||||
564
include/dt-bindings/reset/rockchip,rk3576-cru.h
Normal file
564
include/dt-bindings/reset/rockchip,rk3576-cru.h
Normal file
@ -0,0 +1,564 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co. Ltd.
|
||||
* Copyright (c) 2024 Collabora Ltd.
|
||||
*
|
||||
* Author: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
* Author: Detlev Casanova <detlev.casanova@collabora.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H
|
||||
#define _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H
|
||||
|
||||
#define SRST_A_TOP_BIU 0
|
||||
#define SRST_P_TOP_BIU 1
|
||||
#define SRST_A_TOP_MID_BIU 2
|
||||
#define SRST_A_SECURE_HIGH_BIU 3
|
||||
#define SRST_H_TOP_BIU 4
|
||||
|
||||
#define SRST_H_VO0VOP_CHANNEL_BIU 5
|
||||
#define SRST_A_VO0VOP_CHANNEL_BIU 6
|
||||
|
||||
#define SRST_BISRINTF 7
|
||||
|
||||
#define SRST_H_AUDIO_BIU 8
|
||||
#define SRST_H_ASRC_2CH_0 9
|
||||
#define SRST_H_ASRC_2CH_1 10
|
||||
#define SRST_H_ASRC_4CH_0 11
|
||||
#define SRST_H_ASRC_4CH_1 12
|
||||
#define SRST_ASRC_2CH_0 13
|
||||
#define SRST_ASRC_2CH_1 14
|
||||
#define SRST_ASRC_4CH_0 15
|
||||
#define SRST_ASRC_4CH_1 16
|
||||
#define SRST_M_SAI0_8CH 17
|
||||
#define SRST_H_SAI0_8CH 18
|
||||
#define SRST_H_SPDIF_RX0 19
|
||||
#define SRST_M_SPDIF_RX0 20
|
||||
|
||||
#define SRST_H_SPDIF_RX1 21
|
||||
#define SRST_M_SPDIF_RX1 22
|
||||
#define SRST_M_SAI1_8CH 23
|
||||
#define SRST_H_SAI1_8CH 24
|
||||
#define SRST_M_SAI2_2CH 25
|
||||
#define SRST_H_SAI2_2CH 26
|
||||
#define SRST_M_SAI3_2CH 27
|
||||
#define SRST_H_SAI3_2CH 28
|
||||
|
||||
#define SRST_M_SAI4_2CH 29
|
||||
#define SRST_H_SAI4_2CH 30
|
||||
#define SRST_H_ACDCDIG_DSM 31
|
||||
#define SRST_M_ACDCDIG_DSM 32
|
||||
#define SRST_PDM1 33
|
||||
#define SRST_H_PDM1 34
|
||||
#define SRST_M_PDM1 35
|
||||
#define SRST_H_SPDIF_TX0 36
|
||||
#define SRST_M_SPDIF_TX0 37
|
||||
#define SRST_H_SPDIF_TX1 38
|
||||
#define SRST_M_SPDIF_TX1 39
|
||||
|
||||
#define SRST_A_BUS_BIU 40
|
||||
#define SRST_P_BUS_BIU 41
|
||||
#define SRST_P_CRU 42
|
||||
#define SRST_H_CAN0 43
|
||||
#define SRST_CAN0 44
|
||||
#define SRST_H_CAN1 45
|
||||
#define SRST_CAN1 46
|
||||
#define SRST_P_INTMUX2BUS 47
|
||||
#define SRST_P_VCCIO_IOC 48
|
||||
#define SRST_H_BUS_BIU 49
|
||||
#define SRST_KEY_SHIFT 50
|
||||
|
||||
#define SRST_P_I2C1 51
|
||||
#define SRST_P_I2C2 52
|
||||
#define SRST_P_I2C3 53
|
||||
#define SRST_P_I2C4 54
|
||||
#define SRST_P_I2C5 55
|
||||
#define SRST_P_I2C6 56
|
||||
#define SRST_P_I2C7 57
|
||||
#define SRST_P_I2C8 58
|
||||
#define SRST_P_I2C9 59
|
||||
#define SRST_P_WDT_BUSMCU 60
|
||||
#define SRST_T_WDT_BUSMCU 61
|
||||
#define SRST_A_GIC 62
|
||||
#define SRST_I2C1 63
|
||||
#define SRST_I2C2 64
|
||||
#define SRST_I2C3 65
|
||||
#define SRST_I2C4 66
|
||||
|
||||
#define SRST_I2C5 67
|
||||
#define SRST_I2C6 68
|
||||
#define SRST_I2C7 69
|
||||
#define SRST_I2C8 70
|
||||
#define SRST_I2C9 71
|
||||
#define SRST_P_SARADC 72
|
||||
#define SRST_SARADC 73
|
||||
#define SRST_P_TSADC 74
|
||||
#define SRST_TSADC 75
|
||||
#define SRST_P_UART0 76
|
||||
#define SRST_P_UART2 77
|
||||
#define SRST_P_UART3 78
|
||||
#define SRST_P_UART4 79
|
||||
#define SRST_P_UART5 80
|
||||
#define SRST_P_UART6 81
|
||||
|
||||
#define SRST_P_UART7 82
|
||||
#define SRST_P_UART8 83
|
||||
#define SRST_P_UART9 84
|
||||
#define SRST_P_UART10 85
|
||||
#define SRST_P_UART11 86
|
||||
#define SRST_S_UART0 87
|
||||
#define SRST_S_UART2 88
|
||||
#define SRST_S_UART3 89
|
||||
#define SRST_S_UART4 90
|
||||
#define SRST_S_UART5 91
|
||||
|
||||
#define SRST_S_UART6 92
|
||||
#define SRST_S_UART7 93
|
||||
#define SRST_S_UART8 94
|
||||
#define SRST_S_UART9 95
|
||||
#define SRST_S_UART10 96
|
||||
#define SRST_S_UART11 97
|
||||
#define SRST_P_SPI0 98
|
||||
#define SRST_P_SPI1 99
|
||||
#define SRST_P_SPI2 100
|
||||
|
||||
#define SRST_P_SPI3 101
|
||||
#define SRST_P_SPI4 102
|
||||
#define SRST_SPI0 103
|
||||
#define SRST_SPI1 104
|
||||
#define SRST_SPI2 105
|
||||
#define SRST_SPI3 106
|
||||
#define SRST_SPI4 107
|
||||
#define SRST_P_WDT0 108
|
||||
#define SRST_T_WDT0 109
|
||||
#define SRST_P_SYS_GRF 110
|
||||
#define SRST_P_PWM1 111
|
||||
#define SRST_PWM1 112
|
||||
|
||||
#define SRST_P_BUSTIMER0 113
|
||||
#define SRST_P_BUSTIMER1 114
|
||||
#define SRST_TIMER0 115
|
||||
#define SRST_TIMER1 116
|
||||
#define SRST_TIMER2 117
|
||||
#define SRST_TIMER3 118
|
||||
#define SRST_TIMER4 119
|
||||
#define SRST_TIMER5 120
|
||||
#define SRST_P_BUSIOC 121
|
||||
#define SRST_P_MAILBOX0 122
|
||||
#define SRST_P_GPIO1 123
|
||||
|
||||
#define SRST_GPIO1 124
|
||||
#define SRST_P_GPIO2 125
|
||||
#define SRST_GPIO2 126
|
||||
#define SRST_P_GPIO3 127
|
||||
#define SRST_GPIO3 128
|
||||
#define SRST_P_GPIO4 129
|
||||
#define SRST_GPIO4 130
|
||||
#define SRST_A_DECOM 131
|
||||
#define SRST_P_DECOM 132
|
||||
#define SRST_D_DECOM 133
|
||||
#define SRST_TIMER6 134
|
||||
#define SRST_TIMER7 135
|
||||
#define SRST_TIMER8 136
|
||||
#define SRST_TIMER9 137
|
||||
#define SRST_TIMER10 138
|
||||
|
||||
#define SRST_TIMER11 139
|
||||
#define SRST_A_DMAC0 140
|
||||
#define SRST_A_DMAC1 141
|
||||
#define SRST_A_DMAC2 142
|
||||
#define SRST_A_SPINLOCK 143
|
||||
#define SRST_REF_PVTPLL_BUS 144
|
||||
#define SRST_H_I3C0 145
|
||||
#define SRST_H_I3C1 146
|
||||
#define SRST_H_BUS_CM0_BIU 147
|
||||
#define SRST_F_BUS_CM0_CORE 148
|
||||
#define SRST_T_BUS_CM0_JTAG 149
|
||||
|
||||
#define SRST_P_INTMUX2PMU 150
|
||||
#define SRST_P_INTMUX2DDR 151
|
||||
#define SRST_P_PVTPLL_BUS 152
|
||||
#define SRST_P_PWM2 153
|
||||
#define SRST_PWM2 154
|
||||
#define SRST_FREQ_PWM1 155
|
||||
#define SRST_COUNTER_PWM1 156
|
||||
#define SRST_I3C0 157
|
||||
#define SRST_I3C1 158
|
||||
|
||||
#define SRST_P_DDR_MON_CH0 159
|
||||
#define SRST_P_DDR_BIU 160
|
||||
#define SRST_P_DDR_UPCTL_CH0 161
|
||||
#define SRST_TM_DDR_MON_CH0 162
|
||||
#define SRST_A_DDR_BIU 163
|
||||
#define SRST_DFI_CH0 164
|
||||
#define SRST_DDR_MON_CH0 165
|
||||
#define SRST_P_DDR_HWLP_CH0 166
|
||||
#define SRST_P_DDR_MON_CH1 167
|
||||
#define SRST_P_DDR_HWLP_CH1 168
|
||||
|
||||
#define SRST_P_DDR_UPCTL_CH1 169
|
||||
#define SRST_TM_DDR_MON_CH1 170
|
||||
#define SRST_DFI_CH1 171
|
||||
#define SRST_A_DDR01_MSCH0 172
|
||||
#define SRST_A_DDR01_MSCH1 173
|
||||
#define SRST_DDR_MON_CH1 174
|
||||
#define SRST_DDR_SCRAMBLE_CH0 175
|
||||
#define SRST_DDR_SCRAMBLE_CH1 176
|
||||
#define SRST_P_AHB2APB 177
|
||||
#define SRST_H_AHB2APB 178
|
||||
#define SRST_H_DDR_BIU 179
|
||||
#define SRST_F_DDR_CM0_CORE 180
|
||||
|
||||
#define SRST_P_DDR01_MSCH0 181
|
||||
#define SRST_P_DDR01_MSCH1 182
|
||||
#define SRST_DDR_TIMER0 183
|
||||
#define SRST_DDR_TIMER1 184
|
||||
#define SRST_T_WDT_DDR 185
|
||||
#define SRST_P_WDT 186
|
||||
#define SRST_P_TIMER 187
|
||||
#define SRST_T_DDR_CM0_JTAG 188
|
||||
#define SRST_P_DDR_GRF 189
|
||||
|
||||
#define SRST_DDR_UPCTL_CH0 190
|
||||
#define SRST_A_DDR_UPCTL_0_CH0 191
|
||||
#define SRST_A_DDR_UPCTL_1_CH0 192
|
||||
#define SRST_A_DDR_UPCTL_2_CH0 193
|
||||
#define SRST_A_DDR_UPCTL_3_CH0 194
|
||||
#define SRST_A_DDR_UPCTL_4_CH0 195
|
||||
|
||||
#define SRST_DDR_UPCTL_CH1 196
|
||||
#define SRST_A_DDR_UPCTL_0_CH1 197
|
||||
#define SRST_A_DDR_UPCTL_1_CH1 198
|
||||
#define SRST_A_DDR_UPCTL_2_CH1 199
|
||||
#define SRST_A_DDR_UPCTL_3_CH1 200
|
||||
#define SRST_A_DDR_UPCTL_4_CH1 201
|
||||
|
||||
#define SRST_REF_PVTPLL_DDR 202
|
||||
#define SRST_P_PVTPLL_DDR 203
|
||||
|
||||
#define SRST_A_RKNN0 204
|
||||
#define SRST_A_RKNN0_BIU 205
|
||||
#define SRST_L_RKNN0_BIU 206
|
||||
|
||||
#define SRST_A_RKNN1 207
|
||||
#define SRST_A_RKNN1_BIU 208
|
||||
#define SRST_L_RKNN1_BIU 209
|
||||
|
||||
#define SRST_NPU_DAP 210
|
||||
#define SRST_L_NPUSUBSYS_BIU 211
|
||||
#define SRST_P_NPUTOP_BIU 212
|
||||
#define SRST_P_NPU_TIMER 213
|
||||
#define SRST_NPUTIMER0 214
|
||||
#define SRST_NPUTIMER1 215
|
||||
#define SRST_P_NPU_WDT 216
|
||||
#define SRST_T_NPU_WDT 217
|
||||
|
||||
#define SRST_A_RKNN_CBUF 218
|
||||
#define SRST_A_RVCORE0 219
|
||||
#define SRST_P_NPU_GRF 220
|
||||
#define SRST_P_PVTPLL_NPU 221
|
||||
#define SRST_NPU_PVTPLL 222
|
||||
#define SRST_H_NPU_CM0_BIU 223
|
||||
#define SRST_F_NPU_CM0_CORE 224
|
||||
#define SRST_T_NPU_CM0_JTAG 225
|
||||
#define SRST_A_RKNNTOP_BIU 226
|
||||
#define SRST_H_RKNN_CBUF 227
|
||||
#define SRST_H_RKNNTOP_BIU 228
|
||||
|
||||
#define SRST_H_NVM_BIU 229
|
||||
#define SRST_A_NVM_BIU 230
|
||||
#define SRST_S_FSPI 231
|
||||
#define SRST_H_FSPI 232
|
||||
#define SRST_C_EMMC 233
|
||||
#define SRST_H_EMMC 234
|
||||
#define SRST_A_EMMC 235
|
||||
#define SRST_B_EMMC 236
|
||||
#define SRST_T_EMMC 237
|
||||
|
||||
#define SRST_P_GRF 238
|
||||
#define SRST_P_PHP_BIU 239
|
||||
#define SRST_A_PHP_BIU 240
|
||||
#define SRST_P_PCIE0 241
|
||||
#define SRST_PCIE0_POWER_UP 242
|
||||
|
||||
#define SRST_A_USB3OTG1 243
|
||||
#define SRST_A_MMU0 244
|
||||
#define SRST_A_SLV_MMU0 245
|
||||
#define SRST_A_MMU1 246
|
||||
|
||||
#define SRST_A_SLV_MMU1 247
|
||||
#define SRST_P_PCIE1 248
|
||||
#define SRST_PCIE1_POWER_UP 249
|
||||
|
||||
#define SRST_RXOOB0 250
|
||||
#define SRST_RXOOB1 251
|
||||
#define SRST_PMALIVE0 252
|
||||
#define SRST_PMALIVE1 253
|
||||
#define SRST_A_SATA0 254
|
||||
#define SRST_A_SATA1 255
|
||||
#define SRST_ASIC1 256
|
||||
#define SRST_ASIC0 257
|
||||
|
||||
#define SRST_P_CSIDPHY1 258
|
||||
#define SRST_SCAN_CSIDPHY1 259
|
||||
|
||||
#define SRST_P_SDGMAC_GRF 260
|
||||
#define SRST_P_SDGMAC_BIU 261
|
||||
#define SRST_A_SDGMAC_BIU 262
|
||||
#define SRST_H_SDGMAC_BIU 263
|
||||
#define SRST_A_GMAC0 264
|
||||
#define SRST_A_GMAC1 265
|
||||
#define SRST_P_GMAC0 266
|
||||
#define SRST_P_GMAC1 267
|
||||
#define SRST_H_SDIO 268
|
||||
|
||||
#define SRST_H_SDMMC0 269
|
||||
#define SRST_S_FSPI1 270
|
||||
#define SRST_H_FSPI1 271
|
||||
#define SRST_A_DSMC_BIU 272
|
||||
#define SRST_A_DSMC 273
|
||||
#define SRST_P_DSMC 274
|
||||
#define SRST_H_HSGPIO 275
|
||||
#define SRST_HSGPIO 276
|
||||
#define SRST_A_HSGPIO 277
|
||||
|
||||
#define SRST_H_RKVDEC 278
|
||||
#define SRST_H_RKVDEC_BIU 279
|
||||
#define SRST_A_RKVDEC_BIU 280
|
||||
#define SRST_RKVDEC_HEVC_CA 281
|
||||
#define SRST_RKVDEC_CORE 282
|
||||
|
||||
#define SRST_A_USB_BIU 283
|
||||
#define SRST_P_USBUFS_BIU 284
|
||||
#define SRST_A_USB3OTG0 285
|
||||
#define SRST_A_UFS_BIU 286
|
||||
#define SRST_A_MMU2 287
|
||||
#define SRST_A_SLV_MMU2 288
|
||||
#define SRST_A_UFS_SYS 289
|
||||
|
||||
#define SRST_A_UFS 290
|
||||
#define SRST_P_USBUFS_GRF 291
|
||||
#define SRST_P_UFS_GRF 292
|
||||
|
||||
#define SRST_H_VPU_BIU 293
|
||||
#define SRST_A_JPEG_BIU 294
|
||||
#define SRST_A_RGA_BIU 295
|
||||
#define SRST_A_VDPP_BIU 296
|
||||
#define SRST_A_EBC_BIU 297
|
||||
#define SRST_H_RGA2E_0 298
|
||||
#define SRST_A_RGA2E_0 299
|
||||
#define SRST_CORE_RGA2E_0 300
|
||||
|
||||
#define SRST_A_JPEG 301
|
||||
#define SRST_H_JPEG 302
|
||||
#define SRST_H_VDPP 303
|
||||
#define SRST_A_VDPP 304
|
||||
#define SRST_CORE_VDPP 305
|
||||
#define SRST_H_RGA2E_1 306
|
||||
#define SRST_A_RGA2E_1 307
|
||||
#define SRST_CORE_RGA2E_1 308
|
||||
#define SRST_H_EBC 309
|
||||
#define SRST_A_EBC 310
|
||||
#define SRST_D_EBC 311
|
||||
|
||||
#define SRST_H_VEPU0_BIU 312
|
||||
#define SRST_A_VEPU0_BIU 313
|
||||
#define SRST_H_VEPU0 314
|
||||
#define SRST_A_VEPU0 315
|
||||
#define SRST_VEPU0_CORE 316
|
||||
|
||||
#define SRST_A_VI_BIU 317
|
||||
#define SRST_H_VI_BIU 318
|
||||
#define SRST_P_VI_BIU 319
|
||||
#define SRST_D_VICAP 320
|
||||
#define SRST_A_VICAP 321
|
||||
#define SRST_H_VICAP 322
|
||||
#define SRST_ISP0 323
|
||||
#define SRST_ISP0_VICAP 324
|
||||
|
||||
#define SRST_CORE_VPSS 325
|
||||
#define SRST_P_CSI_HOST_0 326
|
||||
#define SRST_P_CSI_HOST_1 327
|
||||
#define SRST_P_CSI_HOST_2 328
|
||||
#define SRST_P_CSI_HOST_3 329
|
||||
#define SRST_P_CSI_HOST_4 330
|
||||
|
||||
#define SRST_CIFIN 331
|
||||
#define SRST_VICAP_I0CLK 332
|
||||
#define SRST_VICAP_I1CLK 333
|
||||
#define SRST_VICAP_I2CLK 334
|
||||
#define SRST_VICAP_I3CLK 335
|
||||
#define SRST_VICAP_I4CLK 336
|
||||
|
||||
#define SRST_A_VOP_BIU 337
|
||||
#define SRST_A_VOP2_BIU 338
|
||||
#define SRST_H_VOP_BIU 339
|
||||
#define SRST_P_VOP_BIU 340
|
||||
#define SRST_H_VOP 341
|
||||
#define SRST_A_VOP 342
|
||||
#define SRST_D_VP0 343
|
||||
|
||||
#define SRST_D_VP1 344
|
||||
#define SRST_D_VP2 345
|
||||
#define SRST_P_VOP2_BIU 346
|
||||
#define SRST_P_VOPGRF 347
|
||||
|
||||
#define SRST_H_VO0_BIU 348
|
||||
#define SRST_P_VO0_BIU 349
|
||||
#define SRST_A_HDCP0_BIU 350
|
||||
#define SRST_P_VO0_GRF 351
|
||||
#define SRST_A_HDCP0 352
|
||||
#define SRST_H_HDCP0 353
|
||||
#define SRST_HDCP0 354
|
||||
|
||||
#define SRST_P_DSIHOST0 355
|
||||
#define SRST_DSIHOST0 356
|
||||
#define SRST_P_HDMITX0 357
|
||||
#define SRST_HDMITX0_REF 358
|
||||
#define SRST_P_EDP0 359
|
||||
#define SRST_EDP0_24M 360
|
||||
|
||||
#define SRST_M_SAI5_8CH 361
|
||||
#define SRST_H_SAI5_8CH 362
|
||||
#define SRST_M_SAI6_8CH 363
|
||||
#define SRST_H_SAI6_8CH 364
|
||||
#define SRST_H_SPDIF_TX2 365
|
||||
#define SRST_M_SPDIF_TX2 366
|
||||
#define SRST_H_SPDIF_RX2 367
|
||||
#define SRST_M_SPDIF_RX2 368
|
||||
|
||||
#define SRST_H_SAI8_8CH 369
|
||||
#define SRST_M_SAI8_8CH 370
|
||||
|
||||
#define SRST_H_VO1_BIU 371
|
||||
#define SRST_P_VO1_BIU 372
|
||||
#define SRST_M_SAI7_8CH 373
|
||||
#define SRST_H_SAI7_8CH 374
|
||||
#define SRST_H_SPDIF_TX3 375
|
||||
#define SRST_H_SPDIF_TX4 376
|
||||
#define SRST_H_SPDIF_TX5 377
|
||||
#define SRST_M_SPDIF_TX3 378
|
||||
|
||||
#define SRST_DP0 379
|
||||
#define SRST_P_VO1_GRF 380
|
||||
#define SRST_A_HDCP1_BIU 381
|
||||
#define SRST_A_HDCP1 382
|
||||
#define SRST_H_HDCP1 383
|
||||
#define SRST_HDCP1 384
|
||||
#define SRST_H_SAI9_8CH 385
|
||||
#define SRST_M_SAI9_8CH 386
|
||||
#define SRST_M_SPDIF_TX4 387
|
||||
#define SRST_M_SPDIF_TX5 388
|
||||
|
||||
#define SRST_GPU 389
|
||||
#define SRST_A_S_GPU_BIU 390
|
||||
#define SRST_A_M0_GPU_BIU 391
|
||||
#define SRST_P_GPU_BIU 392
|
||||
#define SRST_P_GPU_GRF 393
|
||||
#define SRST_GPU_PVTPLL 394
|
||||
#define SRST_P_PVTPLL_GPU 395
|
||||
|
||||
#define SRST_A_CENTER_BIU 396
|
||||
#define SRST_A_DMA2DDR 397
|
||||
#define SRST_A_DDR_SHAREMEM 398
|
||||
#define SRST_A_DDR_SHAREMEM_BIU 399
|
||||
#define SRST_H_CENTER_BIU 400
|
||||
#define SRST_P_CENTER_GRF 401
|
||||
#define SRST_P_DMA2DDR 402
|
||||
#define SRST_P_SHAREMEM 403
|
||||
#define SRST_P_CENTER_BIU 404
|
||||
|
||||
#define SRST_LINKSYM_HDMITXPHY0 405
|
||||
|
||||
#define SRST_DP0_PIXELCLK 406
|
||||
#define SRST_PHY_DP0_TX 407
|
||||
#define SRST_DP1_PIXELCLK 408
|
||||
#define SRST_DP2_PIXELCLK 409
|
||||
|
||||
#define SRST_H_VEPU1_BIU 410
|
||||
#define SRST_A_VEPU1_BIU 411
|
||||
#define SRST_H_VEPU1 412
|
||||
#define SRST_A_VEPU1 413
|
||||
#define SRST_VEPU1_CORE 414
|
||||
|
||||
#define SRST_P_PHPPHY_CRU 415
|
||||
#define SRST_P_APB2ASB_SLV_CHIP_TOP 416
|
||||
#define SRST_P_PCIE2_COMBOPHY0 417
|
||||
#define SRST_P_PCIE2_COMBOPHY0_GRF 418
|
||||
#define SRST_P_PCIE2_COMBOPHY1 419
|
||||
#define SRST_P_PCIE2_COMBOPHY1_GRF 420
|
||||
|
||||
#define SRST_PCIE0_PIPE_PHY 421
|
||||
#define SRST_PCIE1_PIPE_PHY 422
|
||||
|
||||
#define SRST_H_CRYPTO_NS 423
|
||||
#define SRST_H_TRNG_NS 424
|
||||
#define SRST_P_OTPC_NS 425
|
||||
#define SRST_OTPC_NS 426
|
||||
|
||||
#define SRST_P_HDPTX_GRF 427
|
||||
#define SRST_P_HDPTX_APB 428
|
||||
#define SRST_P_MIPI_DCPHY 429
|
||||
#define SRST_P_DCPHY_GRF 430
|
||||
#define SRST_P_BOT0_APB2ASB 431
|
||||
#define SRST_P_BOT1_APB2ASB 432
|
||||
#define SRST_USB2DEBUG 433
|
||||
#define SRST_P_CSIPHY_GRF 434
|
||||
#define SRST_P_CSIPHY 435
|
||||
#define SRST_P_USBPHY_GRF_0 436
|
||||
#define SRST_P_USBPHY_GRF_1 437
|
||||
#define SRST_P_USBDP_GRF 438
|
||||
#define SRST_P_USBDPPHY 439
|
||||
#define SRST_USBDP_COMBO_PHY_INIT 440
|
||||
|
||||
#define SRST_USBDP_COMBO_PHY_CMN 441
|
||||
#define SRST_USBDP_COMBO_PHY_LANE 442
|
||||
#define SRST_USBDP_COMBO_PHY_PCS 443
|
||||
#define SRST_M_MIPI_DCPHY 444
|
||||
#define SRST_S_MIPI_DCPHY 445
|
||||
#define SRST_SCAN_CSIPHY 446
|
||||
#define SRST_P_VCCIO6_IOC 447
|
||||
#define SRST_OTGPHY_0 448
|
||||
#define SRST_OTGPHY_1 449
|
||||
#define SRST_HDPTX_INIT 450
|
||||
#define SRST_HDPTX_CMN 451
|
||||
#define SRST_HDPTX_LANE 452
|
||||
#define SRST_HDMITXHDP 453
|
||||
|
||||
#define SRST_MPHY_INIT 454
|
||||
#define SRST_P_MPHY_GRF 455
|
||||
#define SRST_P_VCCIO7_IOC 456
|
||||
|
||||
#define SRST_H_PMU1_BIU 457
|
||||
#define SRST_P_PMU1_NIU 458
|
||||
#define SRST_H_PMU_CM0_BIU 459
|
||||
#define SRST_PMU_CM0_CORE 460
|
||||
#define SRST_PMU_CM0_JTAG 461
|
||||
|
||||
#define SRST_P_CRU_PMU1 462
|
||||
#define SRST_P_PMU1_GRF 463
|
||||
#define SRST_P_PMU1_IOC 464
|
||||
#define SRST_P_PMU1WDT 465
|
||||
#define SRST_T_PMU1WDT 466
|
||||
#define SRST_P_PMUTIMER 467
|
||||
#define SRST_PMUTIMER0 468
|
||||
#define SRST_PMUTIMER1 469
|
||||
#define SRST_P_PMU1PWM 470
|
||||
#define SRST_PMU1PWM 471
|
||||
|
||||
#define SRST_P_I2C0 472
|
||||
#define SRST_I2C0 473
|
||||
#define SRST_S_UART1 474
|
||||
#define SRST_P_UART1 475
|
||||
#define SRST_PDM0 476
|
||||
#define SRST_H_PDM0 477
|
||||
|
||||
#define SRST_M_PDM0 478
|
||||
#define SRST_H_VAD 479
|
||||
|
||||
#define SRST_P_PMU0GRF 480
|
||||
#define SRST_P_PMU0IOC 481
|
||||
#define SRST_P_GPIO0 482
|
||||
#define SRST_DB_GPIO0 483
|
||||
|
||||
#endif
|
||||
@ -393,6 +393,20 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
|
||||
#define devm_clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
|
||||
__clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
|
||||
NULL, (flags), (fixed_rate), 0, 0, true)
|
||||
/**
|
||||
* devm_clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
|
||||
* the clock framework
|
||||
* @dev: device that is registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_data: parent clk data
|
||||
* @flags: framework-specific flags
|
||||
* @fixed_rate: non-adjustable clock rate
|
||||
*/
|
||||
#define devm_clk_hw_register_fixed_rate_parent_data(dev, name, parent_data, flags, \
|
||||
fixed_rate) \
|
||||
__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
|
||||
(parent_data), (flags), (fixed_rate), 0, \
|
||||
0, true)
|
||||
/**
|
||||
* clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
|
||||
* the clock framework
|
||||
|
||||
@ -640,6 +640,32 @@ struct clk *devm_clk_get_optional_prepared(struct device *dev, const char *id);
|
||||
*/
|
||||
struct clk *devm_clk_get_optional_enabled(struct device *dev, const char *id);
|
||||
|
||||
/**
|
||||
* devm_clk_get_optional_enabled_with_rate - devm_clk_get_optional() +
|
||||
* clk_set_rate() +
|
||||
* clk_prepare_enable()
|
||||
* @dev: device for clock "consumer"
|
||||
* @id: clock consumer ID
|
||||
* @rate: new clock rate
|
||||
*
|
||||
* Context: May sleep.
|
||||
*
|
||||
* Return: a struct clk corresponding to the clock producer, or
|
||||
* valid IS_ERR() condition containing errno. The implementation
|
||||
* uses @dev and @id to determine the clock consumer, and thereby
|
||||
* the clock producer. If no such clk is found, it returns NULL
|
||||
* which serves as a dummy clk. That's the only difference compared
|
||||
* to devm_clk_get_enabled().
|
||||
*
|
||||
* The returned clk (if valid) is prepared and enabled and rate was set.
|
||||
*
|
||||
* The clock will automatically be disabled, unprepared and freed
|
||||
* when the device is unbound from the bus.
|
||||
*/
|
||||
struct clk *devm_clk_get_optional_enabled_with_rate(struct device *dev,
|
||||
const char *id,
|
||||
unsigned long rate);
|
||||
|
||||
/**
|
||||
* devm_get_clk_from_child - lookup and obtain a managed reference to a
|
||||
* clock producer from child node.
|
||||
@ -982,6 +1008,13 @@ static inline struct clk *devm_clk_get_optional_enabled(struct device *dev,
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline struct clk *
|
||||
devm_clk_get_optional_enabled_with_rate(struct device *dev, const char *id,
|
||||
unsigned long rate)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline int __must_check devm_clk_bulk_get(struct device *dev, int num_clks,
|
||||
struct clk_bulk_data *clks)
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user