Ben Skeggs
|
1ae73f2f16
|
drm/nvc0/pm: restrict pll mode to clocks that can actually use it
Fixes reclocking failure on some chips where we attempted to set PDAEMON
to PLL mode.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
|
2012-03-13 17:14:58 +10:00 |
|
Ben Skeggs
|
045da4e555
|
drm/nvc0/pm: initial engine reclocking
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
|
2011-12-21 19:01:46 +10:00 |
|
Ben Skeggs
|
8ce51fcfee
|
drm/nvc0/pm: minor clock readback fixes
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
|
2011-09-20 16:11:55 +10:00 |
|
Ben Skeggs
|
9698b9a680
|
drm/nvc0/pm: more complete parsing of clock domains
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
|
2011-09-20 16:03:34 +10:00 |
|
Ben Skeggs
|
354d0781e5
|
drm/nvc0/pm: initial implementation of clocks_get()
Not too certain on memory clock yet, but it gets the right numbers for
each perflvl on my NVC0.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
|
2011-09-20 16:03:16 +10:00 |
|