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drm/nvc0/pm: restrict pll mode to clocks that can actually use it

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Fixes reclocking failure on some chips where we attempted to set PDAEMON
to PLL mode.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2012-02-07 09:59:54 +10:00
parent 44ab8cc56c
commit 1ae73f2f16
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/nouveau/nvc0_pm.c
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@ -269,7 +269,7 @@ calc_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info, u32 freq)
clk0 = calc_div(dev, clk, clk0, freq, &div1D);
/* see if we can get any closer using PLLs */
if (clk0 != freq) {
if (clk0 != freq && (0x00004387 & (1 << clk))) {
if (clk < 7)
clk1 = calc_pll(dev, clk, freq, &info->coef);
else