Will be used for exposing current clocks via INFO ioctl.
Tested-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This adds a possibility to control fan on CI parts
via exported hwmon variables. Note that automatic
ucode fan management pauses if you choose to enable
manual fan control. Use with caution!
v2: agd5f: fix formatting, squash in:
minor fix for pwm1_enable exposed value
Track smc control in addition to fan mode
This fixes pwm1_enable being constantly set
to 1 because of enabled smc control
also handle the case where smc fan control is disabled.
Signed-off-by: Oleg Chernovskiy <algonkvel@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This seems to work well on CI boards after fixing the
last few bugs noticed by Chernovsky Oleg.
On boards with a high default fan speed this should
reduce fan noise. Manual fan control is not enabled
yet.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The current code always reprogrammed the sclk levels,
but we don't currently handle disp sclk requirements
so just skip it.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Enable smc fan control for CI boards. Should
reduce the fan noise on systems with a higher
default fan profile.
v2: disable by default, add additional fan setup, rpm control
bug:
https://bugs.freedesktop.org/show_bug.cgi?id=73338
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
include radeon_asic.h header file in the various xxx_dpm.c files
to reduce sparse false positive warnings. Not so great patch
in itself, but reducing warning count from 391 to 258 may help
to see real problems..
Signed-off-by: Michele Curti <michele.curti@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Not sure this was ever necessary for CI, was just done
to be on the safe side.
bug:
https://bugs.freedesktop.org/show_bug.cgi?id=69721
Reviewed-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Properly set the thermal min and max temp on CI.
Otherwise, we end up setting the thermal ranges
to 0 on resume and end up in the lowest power state.
Signed-off-by: Oleg Chernovskiy <algonkvel@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Need to use the RREG32_SMC() accessor since the register
is an smc indirect index.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Some of the vce clocks are automatic, others need to
be manually enabled. For ease, just disable cg when
vce is active.
v2: rebased
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Noticed by Rashika Kheria and cherry-picked from
her larger patch set.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Rashika Kheria <rashika.kheria@gmail.com>
We need more control over the ordering of dpm init with
respect to the rest of the asic. Specifically, the SMC
has to be initialized before the rlc and cg/pg. The pm
code currently initializes late in the driver, but we need
it to happen much earlier so move pm handling into the asic
specific callbacks.
This makes dpm more reliable and makes clockgating work
properly on CIK parts and should help on SI parts as well.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Right now it's called right after enable, but after
reworking the dpm init order, it will get called later
to accomodate loading the smc early, but enabling
thermal interrupts and block powergating later after
the ring tests are complete.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Make sure interrupts are enabled
before we enable thermal interrupts.
Also, don't powergate uvd until after
the ring tests.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Filter out mclk and sclk levels higher than listed in the clk
voltage dependency tables. Supporting these clocks will require
additional driver tweaking that isn't supported yet.
See bug:
https://bugs.freedesktop.org/show_bug.cgi?id=68235
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Calling force_performance_level() from set_power_state()
doesn't work on some asics because the current power
state pointer has not been properly updated at that point.
Move the calls to force_performance_level() out of the
asic specific set_power_state() functions and into
the main power state sequence.
Fixes dpm resume on SI.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Alex Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@gmail.com>
