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drm/radeon: rework CI dpm thermal setup
In preparation for fan control. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
2271e2e2a2
commit
1955f107a7
@ -814,7 +814,7 @@ static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
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}
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}
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static int ci_set_thermal_temperature_range(struct radeon_device *rdev,
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static int ci_thermal_set_temperature_range(struct radeon_device *rdev,
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int min_temp, int max_temp)
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{
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int low_temp = 0 * 1000;
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@ -850,6 +850,35 @@ static int ci_set_thermal_temperature_range(struct radeon_device *rdev,
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return 0;
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}
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static int ci_thermal_enable_alert(struct radeon_device *rdev,
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bool enable)
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{
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u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);
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PPSMC_Result result;
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if (enable) {
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thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
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rdev->irq.dpm_thermal = false;
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result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable);
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if (result != PPSMC_Result_OK) {
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DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
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return -EINVAL;
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}
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} else {
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thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
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rdev->irq.dpm_thermal = true;
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result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable);
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if (result != PPSMC_Result_OK) {
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DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
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return -EINVAL;
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}
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}
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WREG32_SMC(CG_THERMAL_INT, thermal_int);
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return 0;
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}
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#if 0
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static int ci_read_smc_soft_register(struct radeon_device *rdev,
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u16 reg_offset, u32 *value)
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@ -4682,29 +4711,30 @@ int ci_dpm_enable(struct radeon_device *rdev)
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return 0;
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}
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static int ci_set_temperature_range(struct radeon_device *rdev)
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{
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int ret;
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ret = ci_thermal_enable_alert(rdev, false);
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if (ret)
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return ret;
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ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
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if (ret)
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return ret;
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ret = ci_thermal_enable_alert(rdev, true);
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if (ret)
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return ret;
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return ret;
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}
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int ci_dpm_late_enable(struct radeon_device *rdev)
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{
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int ret;
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if (rdev->irq.installed &&
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r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
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#if 0
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PPSMC_Result result;
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#endif
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ret = ci_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
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if (ret) {
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DRM_ERROR("ci_set_thermal_temperature_range failed\n");
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return ret;
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}
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rdev->irq.dpm_thermal = true;
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radeon_irq_set(rdev);
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#if 0
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result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
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if (result != PPSMC_Result_OK)
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DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
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#endif
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}
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ret = ci_set_temperature_range(rdev);
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if (ret)
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return ret;
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ci_dpm_powergate_uvd(rdev, true);
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@ -106,6 +106,7 @@ typedef uint8_t PPSMC_Result;
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#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130)
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#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131)
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#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132)
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#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133)
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#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135)
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#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136)
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#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d)
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@ -157,10 +158,11 @@ typedef uint8_t PPSMC_Result;
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#define PPSMC_MSG_DPM_Config ((uint32_t) 0x102)
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#define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104)
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#define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108)
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#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112)
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#define PPSMC_MSG_Thermal_Cntl_Enable ((uint32_t) 0x10a)
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#define PPSMC_MSG_Voltage_Cntl_Enable ((uint32_t) 0x109)
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#define PPSMC_MSG_VCEPowerOFF ((uint32_t) 0x10e)
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#define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f)
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#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112)
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#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d)
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#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e)
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#define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120)
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