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Author SHA1 Message Date
shenwei.wang@nxp.com
82a9c55a2b pwm: fsl-ftm: Added a dedicated IP interface clock 
The current driver assumes that the ftm_sys clock works as one of the
clock sources for the IP block as well as the IP interface clock. This
assumption does not apply any more on the latest i.MX8x SoC family. On
i.MX8x SoCs, a dedicated IP interface clock is introduced and it must be
enabled before accessing any FTM registers. Moreover, the clock can not
be used as the source clock for the FTM IP block. This patch introduces
the ipg_clk as the dedicated IP interface clock and by default it is the
same as the ftm_sys clock if not specified.

Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-07-09 19:04:19 +02:00
Enric Balletbo i Serra
4964cb52b2 pwm: cros-ec: Switch to SPDX identifier 
Adopt the SPDX license identifier headers to ease license compliance
management.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-07-09 19:02:23 +02:00
Fabio Estevam
a99290c586 pwm: imx: Switch to SPDX identifier 
Adopt the SPDX license identifier headers to ease license compliance
management.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-07-09 18:59:14 +02:00
Vignesh R
38dabd91ff pwm: tiehrpwm: Fix disabling of output of PWMs 
pwm-tiehrpwm driver disables PWM output by putting it in low output
state via active AQCSFRC register in ehrpwm_pwm_disable(). But, the
AQCSFRC shadow register is not updated. Therefore, when shadow AQCSFRC
register is re-enabled in ehrpwm_pwm_enable() (say to enable second PWM
output), previous settings are lost as shadow register value is loaded
into active register. This results in things like PWMA getting enabled
automatically, when PWMB is enabled and vice versa. Fix this by
updating AQCSFRC shadow register as well during ehrpwm_pwm_disable().

Fixes: 19891b20e7 ("pwm: pwm-tiehrpwm: PWM driver support for EHRPWM")
Cc: stable@vger.kernel.org
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-07-09 18:58:22 +02:00
Vignesh R
aa49d628f6 pwm: tiehrpwm: Don't use emulation mode bits to control PWM output 
As per AM335x TRM SPRUH73P "15.2.2.11 ePWM Behavior During Emulation",
TBCTL[15:14] only have effect during emulation suspend events (IOW,
to stop PWM when debugging using a debugger). These bits have no effect
on PWM output during normal running of system. Hence, remove code
accessing these bits as they have no role in enabling/disabling PWMs.

Fixes: 19891b20e7 ("pwm: pwm-tiehrpwm: PWM driver support for EHRPWM")
Cc: stable@vger.kernel.org
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-07-09 18:57:52 +02:00
Thomas Hebb
4de445cb43 pwm: berlin: Don't use broken prescaler values 
The Berlin PWM driver is currently broken on at least BG2CD. The
symptoms manifest as a very non-linear and erratic mapping from the duty
cycle configured in software to the duty cycle produced by hardware.

The cause of the bug is software's configuration of the prescaler, and
in particular its usage of the six prescaler values between the minimum
value of 1 and the maximum value of 4096. As it turns out, these six
values do not actually slow down the PWM clock; rather, they emulate
slowing down the clock by internally multiplying the value of TCNT.

This would be a fine trick, if not for the fact that the internal,
scaled TCNT value has no extra bits beyond the 16 already exposed to
software in the register. What this means is that, for a prescaler of 4,
the software must ensure that the top two bits of TCNT are not set,
because hardware will chop them off; for a prescaler of 8, the top three
bits must not be set, and so forth. Software does not currently ensure
this, resulting in a TCNT several orders of magnitude lower than
intended any time one of those six prescalers are selected.

Because hardware chops off the high bits in its internal shift, the
middle six prescalers don't actually allow *anything* that the first
doesn't. In fact, they are strictly worse than the first, since the
internal shift of TCNT prevents software from setting the low bits,
decreasing the resolution, without providing any extra high bits.

By skipping the useless prescalers entirely, this patch both fixes the
driver's behavior and increases its performance (since, when the 4096
prescaler is selected, it now does only a single shift rather than the
seven successive divisions it did before).

Tested on BG2CD.

Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-07-09 18:57:03 +02:00
Linus Torvalds
4b4bb99b62 pwm: Changes for v4.18-rc1 
This contains a couple of fixes and cleanups for the Meson and ACPI/LPSS
 drivers as well as capture support for STM32. Note that given the cross-
 subsystem changes, the STM32 patches were merged through the MFD and PWM
 trees, both sharing an immutable branch.
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Merge tag 'pwm/for-4.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm

Pull pwm updates from Thierry Reding:
 "This contains a couple of fixes and cleanups for the Meson and
  ACPI/LPSS drivers as well as capture support for STM32.

  Note that given the cross- subsystem changes, the STM32 patches were
  merged through the MFD and PWM trees, both sharing an immutable
  branch"

* tag 'pwm/for-4.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
  pwm: stm32: Fix build warning with CONFIG_DMA_ENGINE disabled
  pwm: stm32: Enforce dependency on CONFIG_MFD_STM32_TIMERS
  ACPI / LPSS: Add missing prv_offset setting for byt/cht PWM devices
  pwm: lpss: platform: Save/restore the ctrl register over a suspend/resume
  dt-bindings: mfd: stm32-timers: Add support for dmas
  pwm: simplify getting .drvdata
  pwm: meson: Fix allocation of PWM channel array
 2018-06-14 16:25:43 +09:00
Kees Cook
a86854d0c5 treewide: devm_kzalloc() -> devm_kcalloc() 
The devm_kzalloc() function has a 2-factor argument form, devm_kcalloc().
This patch replaces cases of:

        devm_kzalloc(handle, a * b, gfp)

with:
        devm_kcalloc(handle, a * b, gfp)

as well as handling cases of:

        devm_kzalloc(handle, a * b * c, gfp)

with:

        devm_kzalloc(handle, array3_size(a, b, c), gfp)

as it's slightly less ugly than:

        devm_kcalloc(handle, array_size(a, b), c, gfp)

This does, however, attempt to ignore constant size factors like:

        devm_kzalloc(handle, 4 * 1024, gfp)

though any constants defined via macros get caught up in the conversion.

Any factors with a sizeof() of "unsigned char", "char", and "u8" were
dropped, since they're redundant.

Some manual whitespace fixes were needed in this patch, as Coccinelle
really liked to write "=devm_kcalloc..." instead of "= devm_kcalloc...".

The Coccinelle script used for this was:

// Fix redundant parens around sizeof().
@@
expression HANDLE;
type TYPE;
expression THING, E;
@@

(
  devm_kzalloc(HANDLE,
-	(sizeof(TYPE)) * E
+	sizeof(TYPE) * E
  , ...)
|
  devm_kzalloc(HANDLE,
-	(sizeof(THING)) * E
+	sizeof(THING) * E
  , ...)
)

// Drop single-byte sizes and redundant parens.
@@
expression HANDLE;
expression COUNT;
typedef u8;
typedef __u8;
@@

(
  devm_kzalloc(HANDLE,
-	sizeof(u8) * (COUNT)
+	COUNT
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(__u8) * (COUNT)
+	COUNT
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(char) * (COUNT)
+	COUNT
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(unsigned char) * (COUNT)
+	COUNT
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(u8) * COUNT
+	COUNT
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(__u8) * COUNT
+	COUNT
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(char) * COUNT
+	COUNT
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(unsigned char) * COUNT
+	COUNT
  , ...)
)

// 2-factor product with sizeof(type/expression) and identifier or constant.
@@
expression HANDLE;
type TYPE;
expression THING;
identifier COUNT_ID;
constant COUNT_CONST;
@@

(
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(TYPE) * (COUNT_ID)
+	COUNT_ID, sizeof(TYPE)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(TYPE) * COUNT_ID
+	COUNT_ID, sizeof(TYPE)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(TYPE) * (COUNT_CONST)
+	COUNT_CONST, sizeof(TYPE)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(TYPE) * COUNT_CONST
+	COUNT_CONST, sizeof(TYPE)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(THING) * (COUNT_ID)
+	COUNT_ID, sizeof(THING)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(THING) * COUNT_ID
+	COUNT_ID, sizeof(THING)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(THING) * (COUNT_CONST)
+	COUNT_CONST, sizeof(THING)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(THING) * COUNT_CONST
+	COUNT_CONST, sizeof(THING)
  , ...)
)

// 2-factor product, only identifiers.
@@
expression HANDLE;
identifier SIZE, COUNT;
@@

- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	SIZE * COUNT
+	COUNT, SIZE
  , ...)

// 3-factor product with 1 sizeof(type) or sizeof(expression), with
// redundant parens removed.
@@
expression HANDLE;
expression THING;
identifier STRIDE, COUNT;
type TYPE;
@@

(
  devm_kzalloc(HANDLE,
-	sizeof(TYPE) * (COUNT) * (STRIDE)
+	array3_size(COUNT, STRIDE, sizeof(TYPE))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(TYPE) * (COUNT) * STRIDE
+	array3_size(COUNT, STRIDE, sizeof(TYPE))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(TYPE) * COUNT * (STRIDE)
+	array3_size(COUNT, STRIDE, sizeof(TYPE))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(TYPE) * COUNT * STRIDE
+	array3_size(COUNT, STRIDE, sizeof(TYPE))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(THING) * (COUNT) * (STRIDE)
+	array3_size(COUNT, STRIDE, sizeof(THING))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(THING) * (COUNT) * STRIDE
+	array3_size(COUNT, STRIDE, sizeof(THING))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(THING) * COUNT * (STRIDE)
+	array3_size(COUNT, STRIDE, sizeof(THING))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(THING) * COUNT * STRIDE
+	array3_size(COUNT, STRIDE, sizeof(THING))
  , ...)
)

// 3-factor product with 2 sizeof(variable), with redundant parens removed.
@@
expression HANDLE;
expression THING1, THING2;
identifier COUNT;
type TYPE1, TYPE2;
@@

(
  devm_kzalloc(HANDLE,
-	sizeof(TYPE1) * sizeof(TYPE2) * COUNT
+	array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+	array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(THING1) * sizeof(THING2) * COUNT
+	array3_size(COUNT, sizeof(THING1), sizeof(THING2))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(THING1) * sizeof(THING2) * (COUNT)
+	array3_size(COUNT, sizeof(THING1), sizeof(THING2))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(TYPE1) * sizeof(THING2) * COUNT
+	array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+	array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
  , ...)
)

// 3-factor product, only identifiers, with redundant parens removed.
@@
expression HANDLE;
identifier STRIDE, SIZE, COUNT;
@@

(
  devm_kzalloc(HANDLE,
-	(COUNT) * STRIDE * SIZE
+	array3_size(COUNT, STRIDE, SIZE)
  , ...)
|
  devm_kzalloc(HANDLE,
-	COUNT * (STRIDE) * SIZE
+	array3_size(COUNT, STRIDE, SIZE)
  , ...)
|
  devm_kzalloc(HANDLE,
-	COUNT * STRIDE * (SIZE)
+	array3_size(COUNT, STRIDE, SIZE)
  , ...)
|
  devm_kzalloc(HANDLE,
-	(COUNT) * (STRIDE) * SIZE
+	array3_size(COUNT, STRIDE, SIZE)
  , ...)
|
  devm_kzalloc(HANDLE,
-	COUNT * (STRIDE) * (SIZE)
+	array3_size(COUNT, STRIDE, SIZE)
  , ...)
|
  devm_kzalloc(HANDLE,
-	(COUNT) * STRIDE * (SIZE)
+	array3_size(COUNT, STRIDE, SIZE)
  , ...)
|
  devm_kzalloc(HANDLE,
-	(COUNT) * (STRIDE) * (SIZE)
+	array3_size(COUNT, STRIDE, SIZE)
  , ...)
|
  devm_kzalloc(HANDLE,
-	COUNT * STRIDE * SIZE
+	array3_size(COUNT, STRIDE, SIZE)
  , ...)
)

// Any remaining multi-factor products, first at least 3-factor products,
// when they're not all constants...
@@
expression HANDLE;
expression E1, E2, E3;
constant C1, C2, C3;
@@

(
  devm_kzalloc(HANDLE, C1 * C2 * C3, ...)
|
  devm_kzalloc(HANDLE,
-	(E1) * E2 * E3
+	array3_size(E1, E2, E3)
  , ...)
|
  devm_kzalloc(HANDLE,
-	(E1) * (E2) * E3
+	array3_size(E1, E2, E3)
  , ...)
|
  devm_kzalloc(HANDLE,
-	(E1) * (E2) * (E3)
+	array3_size(E1, E2, E3)
  , ...)
|
  devm_kzalloc(HANDLE,
-	E1 * E2 * E3
+	array3_size(E1, E2, E3)
  , ...)
)

// And then all remaining 2 factors products when they're not all constants,
// keeping sizeof() as the second factor argument.
@@
expression HANDLE;
expression THING, E1, E2;
type TYPE;
constant C1, C2, C3;
@@

(
  devm_kzalloc(HANDLE, sizeof(THING) * C2, ...)
|
  devm_kzalloc(HANDLE, sizeof(TYPE) * C2, ...)
|
  devm_kzalloc(HANDLE, C1 * C2 * C3, ...)
|
  devm_kzalloc(HANDLE, C1 * C2, ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(TYPE) * (E2)
+	E2, sizeof(TYPE)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(TYPE) * E2
+	E2, sizeof(TYPE)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(THING) * (E2)
+	E2, sizeof(THING)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(THING) * E2
+	E2, sizeof(THING)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	(E1) * E2
+	E1, E2
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	(E1) * (E2)
+	E1, E2
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	E1 * E2
+	E1, E2
  , ...)
)

Signed-off-by: Kees Cook <keescook@chromium.org>
 2018-06-12 16:19:22 -07:00
Arnd Bergmann
414c52b789 pwm: stm32: Fix build warning with CONFIG_DMA_ENGINE disabled 
Without dmaengine support, we get a harmless warning about an unused
function:

	drivers/pwm/pwm-stm32.c:166:12: error: 'stm32_pwm_capture' defined but not used [-Werror=unused-function]

Changing the #ifdef to an IS_ENABLED() check shuts up that warning and
is slightly nicer to read.

Fixes: 53e38fe73f ("pwm: stm32: Add capture support")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-06-06 10:15:55 +02:00
Thierry Reding
91348b1453 Immutable branch between MFD and PWM due for the v4.18 merge window (v2) 
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Merge tag 'ib-mfd-pwm-v4.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into for-next

Immutable branch between MFD and PWM due for the v4.18 merge window (v2)
 2018-06-06 10:15:04 +02:00
Arnd Bergmann
d968e5041f pwm: stm32: Enforce dependency on CONFIG_MFD_STM32_TIMERS 
When compile-testing the PWM driver without also enabling the
stm32_timers MFD, we run into a link error:

	drivers/pwm/pwm-stm32.o: In function `stm32_pwm_raw_capture.isra.6':
	pwm-stm32.c:(.text+0xcb0): undefined reference to `stm32_timers_dma_burst_read'

We don't need the '|| COMPILE_TEST' here, since stm32_timers itself
can be built with CONFIG_COMPILE_TEST on all architectures, so we do
get the coverage through allmodconfig and randconfig builds even
when we make it a hard dependency.

Fixes: 7edf736920 ("pwm: Add driver for STM32 plaftorm")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-06-06 10:04:00 +02:00
Hans de Goede
1d375b58c1 pwm: lpss: platform: Save/restore the ctrl register over a suspend/resume 
On some devices the contents of the ctrl register get lost over a
suspend/resume and the PWM comes back up disabled after the resume.

This is seen on some Bay Trail devices with the PWM in ACPI enumerated
mode, so it shows up as a platform device instead of a PCI device.

If we still think it is enabled and then try to change the duty-cycle
after this, we end up with a "PWM_SW_UPDATE was not cleared" error and
the PWM is stuck in that state from then on.

This commit adds suspend and resume pm callbacks to the pwm-lpss-platform
code, which save/restore the ctrl register over a suspend/resume, fixing
this.

Note that:

1) There is no need to do this over a runtime suspend, since we
only runtime suspend when disabled and then we properly set the enable
bit and reprogram the timings when we re-enable the PWM.

2) This may be happening on more systems then we realize, but has been
covered up sofar by a bug in the acpi-lpss.c code which was save/restoring
the regular device registers instead of the lpss private registers due to
lpss_device_desc.prv_offset not being set. This is fixed by a later patch
in this series.

Cc: stable@vger.kernel.org
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-06-06 10:00:39 +02:00
Fabrice Gasnier
a3b51be3cd pwm: stm32: Initialize raw local variables 
This removes build warning when COMPILE_TEST=y and MFD_STM32_TIMERS=n
in drivers/pwm/pwm-stm32.c. In function 'stm32_pwm_capture' 'raw_prd' and
'raw_dty' may be used uninitialized in this function
[-Wmaybe-uninitialized]

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Tested-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
 2018-06-04 07:13:40 +01:00
Fabrice Gasnier
ab3a897847 pwm: stm32: Use input prescaler to improve period capture 
Using input prescaler, capture unit will trigger DMA once every
configurable /2, /4 or /8 events (rising edge). This helps improve
period (only) capture accuracy at high rates.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
 2018-05-16 09:11:19 +01:00
Fabrice Gasnier
d66ffb91c3 pwm: stm32: Improve capture by tuning counter prescaler 
Currently, capture is based on timeout window to configure prescaler.
PWM capture framework provides 1s window at the time of writing.

There's place for improvement, after input signal has been captured once:
- Finer tune counter clock prescaler, by using 1st capture result (with
arbitrary margin).
- Do a 2nd capture, with scaled capture window.
This increases accuracy, especially at high rates.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
 2018-05-16 09:11:13 +01:00
Fabrice Gasnier
53e38fe73f pwm: stm32: Add capture support 
Add support for PMW input mode on pwm-stm32. STM32 timers support
period and duty cycle capture as long as they have at least two PWM
channels. One capture channel is used for period (rising-edge), one
for duty-cycle (falling-edge).
When there's only one channel available, only period can be captured.
Duty-cycle is simply zero'ed in such a case.

Capture requires exclusive access (e.g. no pwm output running at the
same time, to protect common prescaler).
Timer DMA burst mode (from MFD core) is being used, to take two
snapshots of capture registers (upon each period rising edge).

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
 2018-05-16 09:10:53 +01:00
Wolfram Sang
692099cdcf pwm: simplify getting .drvdata 
We should get drvdata from struct device directly. Going via
platform_device is an unneeded step back and forth.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-04-30 10:40:57 +02:00
Martin Blumenstingl
735596ca8a pwm: meson: Fix allocation of PWM channel array 
Using the pwm-meson driver on the 32-bit SoCs causes memory corruption.
The result are some hard-to-explain errors, for example
devm_clk_register() crashes with a NULL dereference somewhere deep in
the common clock framework code. In some cases the kernel even refused
to boot when any of the PWM controllers were enabled on Meson8b.

The root cause is an incorrect memory size in the devm_kcalloc() call in
meson_pwm_probe(). The code allocates an array of meson_pwm_channel
structs, but the size given is the size of the meson_pwm struct (which
seems like a small copy-and-paste error, as meson_pwm is allocated a few
lines above).

Even with this typo the code seemed to work fine on the 64-bit GX SoCs
(maybe due to the structs having the same size in the compiled result,
but I haven't checked this further).

Fixes: 211ed63075 ("pwm: Add support for Meson PWM Controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-04-30 10:32:30 +02:00
Linus Torvalds
daf3ef6e96 pwm: Changes for v4.17-rc1 
This set of changes adds support for more generations of the RCar
 controller as well as runtime PM support. The JZ4740 driver gains
 support for device tree and can now be used on all Ingenic SoCs.
 
 Rounding things off is a random assortment of fixes and cleanups
 all across the board.
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Merge tag 'pwm/for-4.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm

Pull pwm updates from Thierry Reding:
 "This set of changes adds support for more generations of the RCar
  controller as well as runtime PM support. The JZ4740 driver gains
  support for device tree and can now be used on all Ingenic SoCs.

  Rounding things off is a random assortment of fixes and cleanups all
  across the board"

* tag 'pwm/for-4.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (29 commits)
  pwm: rcar: Add suspend/resume support
  pwm: rcar: Use PM Runtime to control module clock
  dt-bindings: pwm: rcar: Add bindings for R-Car M3N support
  pwm: rcar: Fix a condition to prevent mismatch value setting to duty
  pwm: sysfs: Use put_device() instead of kfree()
  dt-bindings: pwm: sunxi: Add new compatible strings
  pwm: sun4i: Simplify controller mapping
  pwm: sun4i: Drop unused .has_rdy member
  pwm: sun4i: Properly check current state
  pwm: Remove depends on AVR32
  pwm: stm32: LPTimer: Use 3 cells ->of_xlate()
  dt-bindings: pwm-stm32-lp: Add #pwm-cells
  pwm: stm32: Protect common prescaler for all channels
  pwm: stm32: Remove unused struct device
  pwm: mediatek: Improve precision in rate calculation
  pwm: mediatek: Remove redundant MODULE_ALIAS entries
  pwm: mediatek: Fix up PWM4 and PWM5 malfunction on MT7623
  pwm: jz4740: Enable for all Ingenic SoCs
  pwm: jz4740: Add support for devicetree
  pwm: jz4740: Implement ->set_polarity()
  ...
 2018-04-13 15:46:21 -07:00
Linus Torvalds
167569343f ARM: SoC platform updates for 4.17 
This release brings up a new platform based on the old ARM9 core: the
 Nuvoton NPCM is used as a baseboard management controller, competing
 with the better known ASpeed AST2xx series.
 
 Another important change is the addition of ARMv7-A based chips
 in mach-stm32. The older parts in this platform are ARMv7-M based
 microcontrollers, now they are expanding to general-purpose workloads.
 
 The other changes are the usual defconfig updates to enable additional
 drivers, lesser bugfixes. The largest updates as often are the ongoing
 OMAP cleanups, but we also have a number of changes for the older
 PXA and davinci platforms this time.
 
 For the Renesas shmobile/r-car platform, some new infrastructure
 is needed to make the watchdog work correctly.
 
 Supporting Multiprocessing on Allwinner A80 required a significant
 amount of new code, but is not doing anything unexpected.
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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform updates from Arnd Bergmann:
 "This release brings up a new platform based on the old ARM9 core: the
  Nuvoton NPCM is used as a baseboard management controller, competing
  with the better known ASpeed AST2xx series.

  Another important change is the addition of ARMv7-A based chips in
  mach-stm32. The older parts in this platform are ARMv7-M based
  microcontrollers, now they are expanding to general-purpose workloads.

  The other changes are the usual defconfig updates to enable additional
  drivers, lesser bugfixes. The largest updates as often are the ongoing
  OMAP cleanups, but we also have a number of changes for the older PXA
  and davinci platforms this time.

  For the Renesas shmobile/r-car platform, some new infrastructure is
  needed to make the watchdog work correctly.

  Supporting Multiprocessing on Allwinner A80 required a significant
  amount of new code, but is not doing anything unexpected"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (179 commits)
  arm: npcm: modify configuration for the NPCM7xx BMC.
  MAINTAINERS: update entry for ARM/berlin
  ARM: omap2: fix am43xx build without L2X0
  ARM: davinci: da8xx: simplify CFGCHIP regmap_config
  ARM: davinci: da8xx: fix oops in USB PHY driver due to stack allocated platform_data
  ARM: multi_v7_defconfig: add NXP FlexCAN IP support
  ARM: multi_v7_defconfig: enable thermal driver for i.MX devices
  ARM: multi_v7_defconfig: add RN5T618 PMIC family support
  ARM: multi_v7_defconfig: add NXP graphics drivers
  ARM: multi_v7_defconfig: add GPMI NAND controller support
  ARM: multi_v7_defconfig: add OCOTP driver for NXP SoCs
  ARM: multi_v7_defconfig: configure I2C driver built-in
  arm64: defconfig: add CONFIG_UNIPHIER_THERMAL and CONFIG_SNI_AVE
  ARM: imx: fix imx6sll-only build
  ARM: imx: select ARM_CPU_SUSPEND for CPU_IDLE as well
  ARM: mxs_defconfig: Re-sync defconfig
  ARM: imx_v4_v5_defconfig: Use the generic fsl-asoc-card driver
  ARM: imx_v4_v5_defconfig: Re-sync defconfig
  arm64: defconfig: enable stmmac ethernet to defconfig
  ARM: EXYNOS: Simplify code in coupled CPU idle hot path
  ...
 2018-04-05 21:21:08 -07:00
Yoshihiro Shimoda
6873842235 pwm: rcar: Add suspend/resume support 
This patch adds suspend/resume support for Renesas PWM driver.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 01:27:10 +02:00
Hien Dang
f2e6142cdc pwm: rcar: Use PM Runtime to control module clock 
Runtime PM API (pm_runtime_get_sync/pm_runtime_put) should be used
to control module clock instead of clk_prepare_enable and
clk_disable_unprepare.

Signed-off-by: Hien Dang <hien.dang.eb@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 01:26:15 +02:00
Ryo Kodama
6225f9c64b pwm: rcar: Fix a condition to prevent mismatch value setting to duty 
This patch fixes an issue that is possible to set mismatch value to duty
for R-Car PWM if we input the following commands:

 # cd /sys/class/pwm/<pwmchip>/
 # echo 0 > export
 # cd pwm0
 # echo 30 > period
 # echo 30 > duty_cycle
 # echo 0 > duty_cycle
 # cat duty_cycle
 0
 # echo 1 > enable
 --> Then, the actual duty_cycle is 30, not 0.

So, this patch adds a condition into rcar_pwm_config() to fix this
issue.

Signed-off-by: Ryo Kodama <ryo.kodama.vz@renesas.com>
[shimoda: revise the commit log and add Fixes and Cc tags]
Fixes: ed6c1476bf ("pwm: Add support for R-Car PWM Timer")
Cc: Cc: <stable@vger.kernel.org> # v4.4+
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 01:20:13 +02:00
Arvind Yadav
8bbf5b4261 pwm: sysfs: Use put_device() instead of kfree() 
Never directly free @dev after calling device_register(), even if it
returned an error! Always use put_device() to give up the reference
initialized.

Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 01:18:53 +02:00
Andre Przywara
7b4c7c567d pwm: sun4i: Simplify controller mapping 
At the moment we assign our supported compatible strings to a respective
instance of our sun4i_pwm_data structure, even though some of them
are the same.
To avoid further clutter, split out the three different combinations of
features we have at the moment and name them accordingly.
This should make it more obvious which compatible string to use for new
SoCs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 01:12:12 +02:00
Andre Przywara
6a89bb6cc0 pwm: sun4i: Drop unused .has_rdy member 
Commit a054c4d684 ("pwm: sun4i: Drop legacy callbacks") dropped the
only user of the .has_rdy member in our sun4i_pwm_data struct.
Consequently we don't need to store this anymore for the various SoCs,
which paves the way for further simplifications.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 01:11:53 +02:00
Alexandre Belloni
989ae7a5b2 pwm: sun4i: Properly check current state 
Correctly extract the prescaler value from CTRL_REG before comparing it
to PWM_PRESCAL_MASK.

Also, check that both PWM_CLK_GATING and PWM_EN to ensure the PWM is
enabled instead of relying on only one of those.

Fixes: 93e0dfb2c5 ("pwm: sun4i: Improve hardware read out")
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 01:07:57 +02:00
Corentin Labbe
120cc2fff4 pwm: Remove depends on AVR32 
AVR32 is gone, so no more need to depend on it.

Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 00:57:05 +02:00
Gerald Baeza
f6ea025f6e pwm: stm32: LPTimer: Use 3 cells ->of_xlate() 
STM32 Low-Power Timer supports generic 3 cells PWM to encode PWM number,
period and polarity.

Signed-off-by: Gerald Baeza <gerald.baeza@st.com>
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 00:54:56 +02:00
Fabrice Gasnier
4eb67a2096 pwm: stm32: Protect common prescaler for all channels 
There may be a race, when configuring two PWM channels, with different
prescaler values, when there's no active channel yet.
Add mutex lock to avoid concurrent access on PWM apply state.
This is also precursor patch for PWM capture support.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 00:37:37 +02:00
Fabrice Gasnier
3af0bdd1d0 pwm: stm32: Remove unused struct device 
dev is never assigned or used. Remove it.

Fixes: 7edf736920 ("pwm: Add driver for STM32 plaftorm")
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 00:36:12 +02:00
Sean Wang
04c0a4e00d pwm: mediatek: Improve precision in rate calculation 
Add a way that turning resolution from in nanosecond into in picosecond
to improve noticeably almost 4.5% precision.

It's necessary to hold the new resolution with type u64 and thus related
operations on u64 are applied instead in those rate calculations.

And the patch has a dependency on [1].

[1] http://lists.infradead.org/pipermail/linux-mediatek/2018-March/012225.html

Cc: stable@vger.kernel.org
Fixes: caf065f8fd ("pwm: Add MediaTek PWM support")
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 00:32:25 +02:00
Sean Wang
f361787636 pwm: mediatek: Remove redundant MODULE_ALIAS entries 
MODULE_ALIAS exports information to allow the module to be auto-loaded at
boot for the drivers registered using legacy platform registration.

However, currently the driver is always used by DT-only platform,
MODULE_ALIAS is redundant and should be removed properly.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 00:31:59 +02:00
Sean Wang
360cc03656 pwm: mediatek: Fix up PWM4 and PWM5 malfunction on MT7623 
Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to
control PWM4 or PWM5 are distinct from the other PWMs, whose wrong
programming on PWM hardware causes waveform cannot be output as expected.
Thus, the patch adds the extra condition for fixing up the weird case to
let PWM4 or PWM5 able to work on MT7623.

v1 -> v2: use pwm45_fixup naming instead of pwm45_quirk
v2 -> v3: add more tags for Reviewed-by, Fixes, and Cc stable

Cc: stable@vger.kernel.org
Fixes: caf065f8fd ("pwm: Add MediaTek PWM support")
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Zhi Mao <zhi.mao@mediatek.com>
Cc: John Crispin <john@phrozen.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 00:29:58 +02:00
Paul Cercueil
b419006275 pwm: jz4740: Enable for all Ingenic SoCs 
This driver works perfectly with all the versions of the SoCs from
Ingenic that are supported upstream.

This makes the driver usable on JZ4740, JZ4770 and JZ4780 SoCs.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 00:23:57 +02:00
Paul Cercueil
cc20173304 pwm: jz4740: Add support for devicetree 
Add support for probing the pwm-jz4740 directly from devicetree.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 00:23:56 +02:00
Paul Cercueil
174dcc8eae pwm: jz4740: Implement ->set_polarity() 
This permits clients of this driver to specify the polarity to use for
their PWM channel.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 00:23:45 +02:00
Maarten ter Huurne
df56b1712d pwm: jz4740: Make disable operation compatible with TCU2 mode 
On the JZ4750 and later SoCs, channel 1 and 2 operate in a different
way (TCU2 mode) as the other channels. If a TCU2 mode counter is
stopped before its PWM functionality is disabled, the output is not
guaranteed to return to the initial level.

Signed-off-by: Maarten ter Huurne <maarten@treewalker.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 00:22:03 +02:00
Fabio Estevam
1f6eefeb7c pwm: imx: Let PWM be active during suspend 
On a imx6q-cubox-i board, which has an LED driven by PWM, when the system
goes into suspend the PWM block is disabled by default, then the PWM pin
goes to logic level zero and turn on the LED during suspend, which is not
really the behaviour we want to see.

By keeping the PWM enabled during suspend via STOPEN bit, the pwm-leds
driver sets the brightness to zero in suspend and then the LED is
turned off as expected.

So always set the STOPEN to fix the PWM behaviour in suspend.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-28 00:17:36 +02:00
Markus Elfring
708aa931bd pwm: atmel-tcb: Delete an error message for a failed memory allocation 
Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-27 23:28:53 +02:00
Markus Elfring
6106d888a0 pwm: puv3: Delete an error message for a failed memory allocation 
Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-27 23:27:05 +02:00
Benjamin Gaignard
d7a131d3a4 pwm: stm32: Adopt SPDX identifier 
Add SPDX identifier to make it easier to determine the license of the
file.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2018-03-27 23:22:31 +02:00
Arnd Bergmann
4dab216d1f pwm: remove pwm-bfin driver 
The blackfin architecture is getting removed, so this driver is now
obsolete as well.

Acked-by: Thierry Reding <thierry.reding@gmail.com>
Acked-by: Aaron Wu <aaron.wu@analog.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2018-03-26 15:57:08 +02:00
Arnd Bergmann
a687a53370 treewide: simplify Kconfig dependencies for removed archs 
A lot of Kconfig symbols have architecture specific dependencies.
In those cases that depend on architectures we have already removed,
they can be omitted.

Acked-by: Kalle Valo <kvalo@codeaurora.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2018-03-26 15:55:57 +02:00
Keerthy
b7290cf6ff pwm: pwm-omap-dmtimer: Adapt driver to utilize dmtimer pdata ops 
Adapt driver to utilize dmtimer pdata ops instead of pdata-quirks.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2018-02-22 10:54:24 -08:00
Jian Hu
bccaa3f917 pwm: meson: Add clock source configuration for Meson-AXG 
For PWM controller in the Meson-AXG SoC, the EE domain and AO domain
have different clock sources. This patch tries to describe them in the
DT compatible data.

Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-12-05 09:51:36 +01:00
Axel Lin
8472b529e1 pwm: stmpe: Fix wrong register offset for hwpwm=2 case 
Fix trivial copy/paste bug.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Fixes: ef1f09eca7 ("pwm: Add a driver for the STMPE PWM")
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-12-05 09:33:05 +01:00
Gottfried Haider
7e5d1fd75c pwm: Set class for exported channels in sysfs 
Notifications for devices without bus or class set get dropped by
dev_uevent_filter(). Adding the class to the exported child matches
what the GPIO subsystem is doing.

With this change exporting a channel triggers a udev event, which
gives userspace a chance to fixup permissions and makes it possible
for non-root users to make use of the PWM subsystem.

Signed-off-by: Gottfried Haider <gottfried.haider@gmail.com>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: H Hartley Sweeten <hsweeten@visionengravers.com>
CC: linux-pwm@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-rpi-kernel@lists.infradead.org
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-12-05 09:24:58 +01:00
Linus Torvalds
5a787756b8 pwm: Changes for v4.15-rc1 
The changes for this release include power management improvements for
 the pwm-img driver, support for the backup mode on pwm-atmel-tcb as well
 as support for more hardware with the R-Car and Mediatek drivers.
 
 To round things off there's a bit of cleanup for sunxi and stm32-lp.
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Merge tag 'pwm/for-4.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm

Pull pwm updates from Thierry Reding:
 "The changes for this release include power management improvements for
  the pwm-img driver, support for the backup mode on pwm-atmel-tcb as
  well as support for more hardware with the R-Car and Mediatek drivers.

  To round things off there's a bit of cleanup for sunxi and stm32-lp"

* tag 'pwm/for-4.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
  pwm: stm32-lp: Remove pwm_is_enabled() check before calling pwm_disable()
  pwm: mediatek: Add MT2712/MT7622 support
  pwm: sunxi: Use of_device_get_match_data()
  pwm: atmel-tcb: Support backup mode
  dt-bindings: pwm: Add R-Car D3 device tree bindings
  pwm: img: Add runtime PM
  pwm: img: Add suspend / resume handling
 2017-11-22 21:09:18 -10:00
Axel Lin
f83e2ae260 pwm: stm32-lp: Remove pwm_is_enabled() check before calling pwm_disable() 
The same checking is done by the implementation of pwm_disable().

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-11-15 11:02:06 +01:00
Zhi Mao
424268c749 pwm: mediatek: Add MT2712/MT7622 support 
Add support for MT2712 and MT7622. Due to register offset address of
pwm7 for MT2712 is not fixed 0x40, add mtk_pwm_reg_offset array for PWM
register offset.

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-11-15 10:57:53 +01:00
Corentin Labbe
df4f6e8c9f pwm: sunxi: Use of_device_get_match_data() 
The usage of of_device_get_match_data reduce the code size a bit.
Furthermore, it prevents an improbable dereference when
of_match_device() returns NULL.

Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-11-15 10:56:55 +01:00
Romain Izard
1b3d9a93ed pwm: atmel-tcb: Support backup mode 
Save and restore registers for the PWM on suspend and resume, which
makes hibernation and backup modes possible.

Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-11-15 10:51:31 +01:00
Ed Blake
e690ae5262 pwm: img: Add runtime PM 
Add runtime PM to disable the clocks when the h/w is not in use.

Signed-off-by: Ed Blake <ed.blake@sondrel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-11-15 10:38:37 +01:00
Ed Blake
a18afce522 pwm: img: Add suspend / resume handling 
The power may be disabled during suspend, so implement suspend and
resume callbacks to save and restore register state.

Signed-off-by: Ed Blake <ed.blake@sondrel.com>
[thierry.reding@gmail.com: guard using PM_SLEEP instead of PM]
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-11-15 10:38:04 +01:00
Greg Kroah-Hartman
b24413180f License cleanup: add SPDX GPL-2.0 license identifier to files with no license 
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.

By default all files without license information are under the default
license of the kernel, which is GPL version 2.

Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier.  The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.

This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.

How this work was done:

Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
 - file had no licensing information it it.
 - file was a */uapi/* one with no licensing information in it,
 - file was a */uapi/* one with existing licensing information,

Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.

The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne.  Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.

The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed.  Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.

Criteria used to select files for SPDX license identifier tagging was:
 - Files considered eligible had to be source code files.
 - Make and config files were included as candidates if they contained >5
   lines of source
 - File already had some variant of a license header in it (even if <5
   lines).

All documentation files were explicitly excluded.

The following heuristics were used to determine which SPDX license
identifiers to apply.

 - when both scanners couldn't find any license traces, file was
   considered to have no license information in it, and the top level
   COPYING file license applied.

   For non */uapi/* files that summary was:

   SPDX license identifier                            # files
   ---------------------------------------------------|-------
   GPL-2.0                                              11139

   and resulted in the first patch in this series.

   If that file was a */uapi/* path one, it was "GPL-2.0 WITH
   Linux-syscall-note" otherwise it was "GPL-2.0".  Results of that was:

   SPDX license identifier                            # files
   ---------------------------------------------------|-------
   GPL-2.0 WITH Linux-syscall-note                        930

   and resulted in the second patch in this series.

 - if a file had some form of licensing information in it, and was one
   of the */uapi/* ones, it was denoted with the Linux-syscall-note if
   any GPL family license was found in the file or had no licensing in
   it (per prior point).  Results summary:

   SPDX license identifier                            # files
   ---------------------------------------------------|------
   GPL-2.0 WITH Linux-syscall-note                       270
   GPL-2.0+ WITH Linux-syscall-note                      169
   ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause)    21
   ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)    17
   LGPL-2.1+ WITH Linux-syscall-note                      15
   GPL-1.0+ WITH Linux-syscall-note                       14
   ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause)    5
   LGPL-2.0+ WITH Linux-syscall-note                       4
   LGPL-2.1 WITH Linux-syscall-note                        3
   ((GPL-2.0 WITH Linux-syscall-note) OR MIT)              3
   ((GPL-2.0 WITH Linux-syscall-note) AND MIT)             1

   and that resulted in the third patch in this series.

 - when the two scanners agreed on the detected license(s), that became
   the concluded license(s).

 - when there was disagreement between the two scanners (one detected a
   license but the other didn't, or they both detected different
   licenses) a manual inspection of the file occurred.

 - In most cases a manual inspection of the information in the file
   resulted in a clear resolution of the license that should apply (and
   which scanner probably needed to revisit its heuristics).

 - When it was not immediately clear, the license identifier was
   confirmed with lawyers working with the Linux Foundation.

 - If there was any question as to the appropriate license identifier,
   the file was flagged for further research and to be revisited later
   in time.

In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.

Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights.  The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.

Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.

In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.

Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
 - a full scancode scan run, collecting the matched texts, detected
   license ids and scores
 - reviewing anything where there was a license detected (about 500+
   files) to ensure that the applied SPDX license was correct
 - reviewing anything where there was no detection but the patch license
   was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
   SPDX license was correct

This produced a worksheet with 20 files needing minor correction.  This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.

These .csv files were then reviewed by Greg.  Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected.  This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.)  Finally Greg ran the script using the .csv files to
generate the patches.

Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2017-11-02 11:10:55 +01:00
Linus Torvalds
66c9457df3 pwm: Changes for v4.14-rc1 
The changes for this release include a new driver for the PWM controller
 found on SoCs of the ZTX ZX family. Support for an old SH-Mobile SoC has
 been dropped and the Rockchip and MediaTek drivers gain support for more
 generations.
 
 Other than that there are a bunch of coding style fixes, minor bug fixes
 and cleanup as well as documentation patches.
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Merge tag 'pwm/for-4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm

Pull pwm updates from Thierry Reding:
 "The changes for this release include a new driver for the PWM
  controller found on SoCs of the ZTX ZX family. Support for an old
  SH-Mobile SoC has been dropped and the Rockchip and MediaTek drivers
  gain support for more generations.

  Other than that there are a bunch of coding style fixes, minor bug
  fixes and cleanup as well as documentation patches"

* tag 'pwm/for-4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (32 commits)
  pwm: pwm-samsung: fix suspend/resume support
  pwm: samsung: Remove redundant checks from pwm_samsung_config()
  pwm: mediatek: Disable clock on PWM configuration failure
  dt-bindings: pwm: Add MT2712/MT7622 information
  pwm: mediatek: Fix clock control issue
  pwm: mediatek: Fix PWM source clock selection
  pwm: mediatek: Fix Kconfig description
  pwm: tegra: Explicitly request exclusive reset control
  pwm: hibvt: Explicitly request exclusive reset control
  pwm: tiehrpwm: Set driver data before runtime PM enable
  pwm: tiehrpwm: Miscellaneous coding style fixups
  pwm: tiecap: Set driver data before runtime PM enable
  pwm: tiecap: Miscellaneous coding style fixups
  dt-bindings: pwm: tiecap: Add TI 66AK2G SoC specific compatible
  pwm: tiehrpwm: fix clock imbalance in probe error path
  pwm: tiehrpwm: Fix runtime PM imbalance at unbind
  pwm: Kconfig: Enable pwm-tiecap to be built for Keystone
  pwm: Add ZTE ZX PWM device driver
  dt-bindings: pwm: Add bindings doc for ZTE ZX PWM controller
  pwm: bcm2835: Support for polarity setting via DT
  ...
 2017-09-11 13:04:32 -07:00
Lee Jones
3f979bf8f5 Merge branches 'ib-mfd-arm-i2c-4.14', 'ib-mfd-arm-usb-video-4.14', 'ib-mfd-hwmon-4.14', 'ib-mfd-iio-pwm-4.14', 'ib-mfd-input-rtc-4.14', 'ib-mfd-many-4.14' and 'ib-mfd-pinctrl-regulator-4.14' into ibs-for-mfd-merged 2017-09-05 08:45:36 +01:00
Fabrice Gasnier
e70a540b4e pwm: Add STM32 LPTimer PWM driver 
Add support for single PWM channel on Low-Power Timer, that can be
found on some STM32 platforms.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
 2017-09-04 14:49:09 +01:00
Wolfram Sang
a205425658 mfd: twl: Move header file out of I2C realm 
include/linux/i2c is not for client devices. Move the header file to a
more appropriate location.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Jonathan Cameron <jic23@kernel.org>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Daniel Thompson <daniel.thompson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
 2017-09-04 14:41:02 +01:00
Bartlomiej Zolnierkiewicz
08a4d8ec42 pwm: pwm-samsung: fix suspend/resume support 
Fix suspend/resume support:

- add disabled_mask to struct samsung_pwm_chip to track PWM
  disabled state information in pwm_samsung_{disable,enable}()

- rename pwm_samsung_config() to __pwm_samsung_config() and
  add extra force_period parameter to be used during resume
  (to force tin_ns and tcnt recalculation)

- add pwm_samsung_config() wrapper for preserving old behavior

- properly restore PWM configuration in pwm_samsung_resume()

- remove no longer needed pwm_samsung_suspend()

- update Copyrights

Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-21 10:39:12 +02:00
Bartlomiej Zolnierkiewicz
23aa19a22e pwm: samsung: Remove redundant checks from pwm_samsung_config() 
If the requested period_ns and duty_ns values are identical to the last
programmed ones pwm_samsung_config() returns early and skips the
hardware configuration. The same checks are now done by the PWM core so
the driver specific ones can be removed.

Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-21 10:39:11 +02:00
Zhi Mao
8bdb65dc85 pwm: mediatek: Disable clock on PWM configuration failure 
Make sure to disable the PWM clock if the PWM cannot be configured due
to the clock divider exceeding the maximum value.

While at it, replace the hardcoded maximum clock divider with a defined
constant to improve code readability.

Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
Acked-by: John Crispin <john@phrozen.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-21 10:39:11 +02:00
Zhi Mao
e7c197ec97 pwm: mediatek: Fix clock control issue 
In order to save some power, do not prepare the top and main clocks
during mtk_pwm_probe(). Instead, prepare the clocks only when necessary
and also make sure to enable the clocks to match the semantics of the
common clock framework.

While at it, don't explicitly disable all PWM channels in ->remove()
because all users should have done that already.

Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
Acked-by: John Crispin <john@phrozen.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-21 10:39:09 +02:00
Zhi Mao
cd30798a6c pwm: mediatek: Fix PWM source clock selection 
In original code, the PWM output frequency is not correct when set
bit<3>=1 to PWMCON register.

Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: John Crispin <john@phrozen.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-21 10:39:09 +02:00
Zhi Mao
aa12d7a7a9 pwm: mediatek: Fix Kconfig description 
Fix a copy/paste error that sneaked into the Kconfig description of the
Mediatek PWM driver.

Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
Acked-by: John Crispin <john@phrozen.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-21 10:39:08 +02:00
Philipp Zabel
6b03ef24ea pwm: tegra: Explicitly request exclusive reset control 
Commit a53e35db70 ("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control request API calls
to explicitly state whether the driver needs exclusive or shared reset
control behavior. Convert all drivers requesting exclusive resets to the
explicit API call so the temporary transition helpers can be removed.

No functional changes.

Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-pwm@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-21 08:53:07 +02:00
Philipp Zabel
0fd3b93f61 pwm: hibvt: Explicitly request exclusive reset control 
Commit a53e35db70 ("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control request API calls
to explicitly state whether the driver needs exclusive or shared reset
control behavior. Convert all drivers requesting exclusive resets to the
explicit API call so the temporary transition helpers can be removed.

No functional changes.

Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-pwm@vger.kernel.org
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-21 08:52:40 +02:00
Thierry Reding
d870c80e1d pwm: tiehrpwm: Set driver data before runtime PM enable 
Runtime PM callbacks can be run right after runtime PM is enabled, so
make sure to set the driver data before that. This is unlikely to ever
happen with the current driver, but it doesn't hurt to follow best
practices anyway.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-21 08:42:56 +02:00
Thierry Reding
d2c95e47f8 pwm: tiehrpwm: Miscellaneous coding style fixups 
I noticed most of these while reviewing another patch and thought I'd
fix them while at it. These are mostly changes to make variable types
more strict and whitespace fixups.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-21 08:42:25 +02:00
Thierry Reding
23f373e6fe pwm: tiecap: Set driver data before runtime PM enable 
Runtime PM callbacks can be run right after runtime PM is enabled, so
make sure to set the driver data before that. This is unlikely to ever
happen with the current driver, but it doesn't hurt to follow best
practices anyway.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-21 08:31:37 +02:00
Thierry Reding
53c7972d6d pwm: tiecap: Miscellaneous coding style fixups 
I noticed most of these while reviewing another patch and thought I'd
fix them while at it. These are mostly changes to make variable types
more strict and whitespace fixups.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-21 08:29:41 +02:00
Johan Hovold
e2b5602af7 pwm: tiehrpwm: fix clock imbalance in probe error path 
Make sure to unprepare the clock before returning on late probe errors.

Fixes: b388f15fd1 ("pwm: pwm-tiehrpwm: Use clk_enable/disable instead clk_prepare/unprepare.")
Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-21 08:11:26 +02:00
Johan Hovold
c7fdd3f529 pwm: tiehrpwm: Fix runtime PM imbalance at unbind 
Remove unbalanced RPM put at driver unbind which resulted in a negative
usage count.

Fixes: 19891b20e7 ("pwm: pwm-tiehrpwm: PWM driver support for EHRPWM")
Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-21 08:11:25 +02:00
Vignesh R
cd9b53daaf pwm: Kconfig: Enable pwm-tiecap to be built for Keystone 
66AK2G SoC has ECAP subsystem that is used as pwm-backlight provider for
display. Hence, enable pwm-tiecap driver to be built for Keystone
architecture.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-21 08:11:24 +02:00
Shawn Guo
4836193c43 pwm: Add ZTE ZX PWM device driver 
It adds PWM device driver for ZTE ZX family SoCs. The PWM controller
supports 4 devices with polarity configuration.

The driver has been tested with pwm-regulator support to scale core
voltage via cpufreq.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-21 08:11:24 +02:00
Stefan Wahren
8a88b2a201 pwm: bcm2835: Support for polarity setting via DT 
This adds support for the third (optional) pwm cell to specify the
polarity, which is needed by display backlights for example.

Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-21 07:27:58 +02:00
David Wu
3f9a363133 pwm: rockchip: Add rk3328 support 
The rk3328 SoC supports atomic update, we could lock the configuration
of period and duty at first, after unlock is configured, the period and
duty are effective at the same time.

If the polarity, period and duty need to be configured together,
the way for atomic update is "configure lock and old polarity" ->
"configure period and duty" -> "configure unlock and new polarity".

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-18 17:44:34 +02:00
David Wu
831b279050 pwm: rockchip: Use same PWM ops for each IP 
Just use the same PWM ops for each IP, and get rid of the ops in struct
rockchip_pwm_data, but still define the three different instances of the
struct to use common interface for each IP.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-18 17:42:30 +02:00
David Wu
bc834d7b07 pwm: rockchip: Move the configuration of polarity 
It is usually possible to configure the polarity, cycle and duty all at
once, so that the polarity and cycle and duty are applied atomically.
Move it from rockchip_pwm_set_enable() into rockchip_pwm_config(), as
well as prepare for the next atomic update commit.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-18 17:40:05 +02:00
David Wu
ed054693d7 pwm: rockchip: Use pwm_apply() instead of pwm_enable() 
Drop the custom hook of pwm_enable() and implement pwm_apply_v1() and
pwm_apply_v2() instead.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-18 17:36:56 +02:00
David Wu
f90df9cda6 pwm: rockchip: Remove the judge from return value of pwm_config() 
It seems the rockchip_pwm_config() always returns the result 0, so
remove the judge.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-18 17:33:07 +02:00
David Wu
27922ff598 pwm: rockchip: Add APB and function both clocks support 
New PWM module provides two individual clocks for APB clock and function
clock.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-18 17:31:56 +02:00
Simon Horman
1f8736c4e1 pwm: renesas-tpu: Remove support for SH7372 
Remove support for the SH7372 (SH-Mobile AP4) from the renesas-tpu
driver.

Commit edf4100906 ("ARM: shmobile: sh7372 dtsi: Remove Legacy
file") removed this SoC from the kernel in v4.1.

Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-08-18 17:27:14 +02:00
Arvind Yadav
0bd24f9b5b pwm: vt8500: Undo preparation of a clock source. 
Undo preparation of a clock source if vt8500_pwm_probe() is not
successful.

Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-07-25 13:43:28 +02:00
Sven Van Asbroeck
0829326ab2 pwm: pca9685: clarify pca9685_set_sleep_mode() interface. 
The function
static void pca9685_set_sleep_mode(struct pca9685 *pca, int sleep)
takes the chip in and out of sleep mode, depending on the value of
sleep, which is interpreted as a boolean.

To clarify that 'int sleep' is a boolean and not a sleep delay,
change the function interface to:
static void pca9685_set_sleep_mode(struct pca9685 *pca, bool enable)

Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sven Van Asbroeck <thesven73@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-07-25 13:41:59 +02:00
Rob Herring
36af66a790 pwm: Convert to using %pOF instead of full_name 
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Carlo Caione <carlo@caione.org>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: linux-pwm@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-amlogic@lists.infradead.org
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-07-25 13:38:22 +02:00
Linus Torvalds
38f7d2da4e pwm: Changes for v4.13-rc1 
This release cycle's changes include mostly updates and cleanups to
 existing drivers along with a few cleanups to the core, documentation
 and device tree bindings.
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Merge tag 'pwm/for-4.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm

Pull pwm updates from Thierry Reding:
 "This release cycle's changes include mostly updates and cleanups to
  existing drivers along with a few cleanups to the core, documentation
  and device tree bindings"

* tag 'pwm/for-4.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
  pwm: cros-ec: Fix transposed param settings
  pwm: meson: Improve PWM calculation precision
  dt-bindings: pwm: meson: Add compatible for gxbb ao PWMs
  pwm: meson: Add compatible for the gxbb ao PWMs
  pwm: sun4i: Drop legacy callbacks
  pwm: sun4i: Switch to atomic PWM
  pwm: sun4i: Improve hardware read out
  pwm: hibvt: Constify hibvt_pwm_ops
  pwm: Silently error out on EPROBE_DEFER
  pwm: Standardize document format
  pwm: bfin: Remove unneeded error message
  dt-bindings: pwm: Update STM32 timers clock names
  dt-bindings: pwm: Add R-Car M3-W device tree bindings
  pwm: tegra: Set maximum pwm clock source per SoC tapeout
 2017-07-13 11:49:52 -07:00
Thierry Reding
5ec8c48a62 Merge branch 'for-4.13/drivers' into for-next 2017-07-06 17:16:47 +02:00
Nick Vaccaro
e47866a177 pwm: cros-ec: Fix transposed param settings 
The __cros_ec_pwm_get_duty() routine was transposing the insize and
outsize fields when calling cros_ec_cmd_xfer_status().

The original code worked without error due to size of the two particular
parameter blocks passed to cros_ec_cmd_xfer_status(), so this change is
not fixing an actual runtime problem, just correcting the calling usage.

Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-07-06 17:16:37 +02:00
Jerome Brunet
fd7b2be8cb pwm: meson: Improve PWM calculation precision 
When using input clocks with high rates, such as clk81 (166MHz), the
fin_ns = NSEC_PER_SEC / fin_freq can introduce a significant error.

Ex: fin_freq = 166666667, NSEC_PER_SEC = 1000000000
    fin_ns = 5,9999999

which is, of course, rounded down to 5. This introduces an error of ~20%
on the period requested from the PWM.

This patch uses ps instead of ns (and 64 bit integers) to perform the
calculation. This should give a good enough precision.

Fixes: 211ed63075 ("pwm: Add support for Meson PWM Controller")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

squash! pwm: meson: Improve pwm calculation precision
 2017-07-06 17:15:43 +02:00
Jerome Brunet
d396b20a1e pwm: meson: Add compatible for the gxbb ao PWMs 
On the gxbb (and gxl) family, the PWMs of the AO domain require a
specific compatible because the possible input clocks are different
from the EE PWMs input clocks.

Since the number of possible input clocks is also different, the
'num_parents' field is added to all the Meson PWM data.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-07-06 09:05:22 +02:00
Alexandre Belloni
a054c4d684 pwm: sun4i: Drop legacy callbacks 
Remove the legacy callbacks .enable(), .disable(), .set_polarity() and
.config().

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-07-06 09:05:21 +02:00
Alexandre Belloni
c32c5c50d4 pwm: sun4i: Switch to atomic PWM 
Switch the driver to atomic PWM. This makes it easier to wait a proper
amount of time when changing the duty cycle before disabling the channel
(main use case is switching the duty cycle to 0 before disabling).

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-07-06 09:05:21 +02:00
Alexandre Belloni
93e0dfb2c5 pwm: sun4i: Improve hardware read out 
Implement .get_state instead of only reading the polarity at probe time.
This allows to get the proper state, period and duty cycle.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-07-06 09:05:17 +02:00
Arvind Yadav
c034a6fda0 pwm: hibvt: Constify hibvt_pwm_ops 
File size before:
   text	   data	    bss	    dec	    hex	filename
   1510	    296	      0	   1806	    70e	drivers/pwm/pwm-hibvt.o
File size After adding 'const':
   text	   data	    bss	    dec	    hex	filename
   1606	    192	      0	   1798	    706	drivers/pwm/pwm-hibvt.o

Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-07-06 08:38:53 +02:00
Jerome Brunet
93c292ef3c pwm: Silently error out on EPROBE_DEFER 
In of_pwm_get(), if we fail to get the PWM chip due to probe deferal, we
shouldn't print an error message. Just be silent in this case.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-07-06 08:29:16 +02:00
Markus Elfring
0e1921dcd8 pwm: bfin: Remove unneeded error message 
Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.

Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-07-06 07:56:54 +02:00
Laxman Dewangan
0527eb3723 pwm: tegra: Set maximum pwm clock source per SoC tapeout 
The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.

From HW team:

	Before Tegra186, it is 48 MHz.
	In Tegra186, it is 102 MHz.

Add support to limit the clock source frequency to the maximum IP
supported frequency. Provide these values via SoC chipdata.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-06-13 14:30:22 +02:00
Paul Cercueil
47096d702c pwm: jz4740: Let the pinctrl driver configure the pins 
Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.

One inherent problem of this new approach is that the pinctrl framework
does not allow us to configure each pin on demand, when the various PWM
channels are requested or released. For instance, the PWM channels can
be configured from sysfs, which would require all PWM pins to be configured
properly beforehand for the PWM function, eventually causing conflicts
with other platform or board drivers.

The proper solution here would be to modify the pwm-jz4740 driver to
handle only one PWM channel, and create an instance of this driver
for each one of the 8 PWM channels. Then, it could use the pinctrl
framework to dynamically configure the PWM pin it controls.

Until this can be done, the only jz4740 board supported upstream
(Qi lb60) can configure all of its connected PWM pins in PWM function
mode, since those are not used by other drivers nor by GPIOs on the
board.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2017-05-22 17:21:06 +02:00
Thierry Reding
97512ceafa Merge branch 'for-4.12/drivers' into for-next 2017-04-13 17:41:50 +02:00
Laxman Dewangan
46fa8bc087 pwm: tegra: Read PWM clock source rate in driver init 
It is required to know the PWM clock source frequency to calculate the
PWM period.

In driver, the clock source frequency of the PWM does not get change
and, hence, get the clock source frequency in driver init. Get this
values later for period calculation from pwm_config().

This will help in avoiding the clock call for getting clock rate in the
pwm_config() each time.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-04-13 17:35:40 +02:00
Sven Van Asbroeck
c40c461e19 pwm: pca9685: Fix GPIO-only operation 
GPIO-only driver operation never clears the SLEEP bit, which can cause
the GPIOs to become unusable.

Example:
1. user requests first PWM  ->      driver clears SLEEP bit
2. user frees last PWM      ->      driver sets SLEEP bit
3. user requests GPIO
4. user switches GPIO on    ->      output does not turn on
                                    because SLEEP bit is set

Prevent this behaviour by letting the runtime PM framework control the
SLEEP bit. This will put the chip to SLEEP if no PWMs/GPIOs are exported
or in use.

Fixes: bccec89f0a ("Allow any of the 16 PWMs to be used as a GPIO")
Reported-by: Sven Van Asbroeck <TheSven73@googlemail.com>
Signed-off-by: Sven Van Asbroeck <TheSven73@googlemail.com>
Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-04-13 17:35:01 +02:00
kbuild test robot
6db249db5e pwm: mediatek: Don't explicitly set .owner 
drivers/pwm/pwm-mediatek.c:210:3-8: No need to set .owner here. The core will do it.

 Remove .owner field if calls are used which set it automatically

Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci

CC: John Crispin <john@phrozen.org>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-04-13 17:35:00 +02:00
Thierry Reding
6db78b201b pwm: tegra: Avoid potential overflow for short periods 
For very short periods, the result of the division might overflow the
unsigned long hz variable (on 32-bit architectures). Avoid that by
making it an unsigned long long. While at it, also remove an unneeded
local variable whose only purpose is to store a temporary computation.

Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-04-13 17:34:54 +02:00
Laxman Dewangan
4a813b262f pwm: tegra: Add support to configure pin state in suspends/resume 
In some of NVIDIA Tegra's platform, PWM controller is used to
control the PWM controlled regulators. PWM signal is connected to
the VID pin of the regulator where duty cycle of PWM signal decide
the voltage level of the regulator output.

When system enters suspend, some PWM client/slave regulator devices
require the PWM output to be tristated.

Add support to configure the pin state via pinctrl frameworks in
suspend and active state of the system.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-04-12 16:10:09 +02:00
Laxman Dewangan
250b76f43f pwm: tegra: Increase precision in PWM rate calculation 
The rate of the PWM calculated as follows:

	hz = NSEC_PER_SEC / period_ns;
 	rate = (rate + (hz / 2)) / hz;

This has the precision loss in lower PWM rate.

Change this to have more precision as:

	hz = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC * 100, period_ns);
	rate = DIV_ROUND_CLOSEST(rate * 100, hz)

Example:

1. period_ns = 16672000, PWM clock rate is 200 KHz.

	Based on old formula
		hz = NSEC_PER_SEC / period_ns
		   = 1000000000ul/16672000
		   = 59 (59.98)
		rate = (200K + 59/2)/59 = 3390

	Based on new method:
		hz = 5998
		rate = DIV_ROUND_CLOSE(200000*100, 5998) = 3334

	If we measure the PWM signal rate, we will get more accurate
	period with rate value of 3334 instead of 3390.

2.  period_ns = 16803898, PWM clock rate is 200 KHz.

	Based on old formula:
		hz = 59, rate = 3390

	Based on new formula:
		hz = 5951, rate = 3360

	The PWM signal rate of 3360 is more near to requested period
	than 3333.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-04-12 16:08:15 +02:00
Laxman Dewangan
90241fb9b5 pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local implementation 
Use macro DIV_ROUND_CLOSEST_ULL() for 64-bit division to closest one
instead of implementing the same locally. This increase readability.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-04-12 16:08:00 +02:00
John Crispin
caf065f8fd pwm: Add MediaTek PWM support 
This patch adds support for the PWM core found on current ARM base SoCs
made by MediaTek. This IP core supports 5 channels and has 2 operational
modes. There is the old mode, which is a classical PWM and the new mode
which allows the user to define bitmasks that get clocked out on the
pins. As the subsystem currently only supports PWM cores with the "old"
mode, we can safely ignore the "new" mode for now.

Signed-off-by: John Crispin <john@phrozen.org>
[thierry.reding@gmail.com: minor cleanups]
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-04-06 17:45:04 +02:00
Claudiu Beznea
44521afa57 pwm: atmel: Enable PWM on sama5d2 
sama5d2 can use the same atmel_pwm_data as sama5d3.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-04-06 17:45:03 +02:00
Claudiu Beznea
1a722aad58 pwm: atmel: Switch to atomic PWM 
The currently Atmel PWM controllers supported by this driver could
change period or duty factor without channel disable, for regular
channels (sama5d3 support this by using period or duty factor update
registers, sam9rl support this by writing channel update register and
select the corresponding update: period or duty factor). The chip
doesn't support run time changings of signal polarity. To take advantage
of atomic PWM framework and let controller works without glitches, in
this patch only the duty factor could be changed without disabling PWM
channel. For period and signal polarity the atomic PWM is simulated by
disabling + enabling the right PWM channel.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-04-06 17:45:02 +02:00
Boris Brezillon
f9bb9da7c0 pwm: atmel-hlcdc: Implement the suspend/resume hooks 
Implement the suspend/resume hooks to make sure the PWM device is
restored to a correct state after a suspend.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-04-06 17:45:02 +02:00
Boris Brezillon
2267517cd3 pwm: atmel-hlcdc: Convert to the atomic PWM API 
Implement the ->apply() hook and drop the ->enable(), ->disable,
->set_polarity and ->config() ones.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-04-06 16:12:52 +02:00
David Wu
a900152b5c pwm: rockchip: State of PWM clock should synchronize with PWM enabled state 
If the PWM was not enabled at U-Boot loader, PWM could not work for
clock always disabled at PWM driver. The PWM clock is enabled at
beginning of pwm_apply(), but disabled at end of pwm_apply().

If the PWM was enabled at U-Boot loader, PWM clock is always enabled
unless closed by ATF. The pwm-backlight might turn off the power at
early suspend, should disable PWM clock for saving power consume.

It is important to provide opportunity to enable/disable clock at PWM
driver, the PWM consumer should ensure correct order to call PWM enable
and disable, and PWM driver ensure state of PWM clock synchronized with
PWM enabled state.

Fixes: 2bf1c98aa5 ("pwm: rockchip: Add support for atomic update")
Cc: stable@vger.kernel.org
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-04-06 15:08:52 +02:00
Hans de Goede
b997e3edca pwm: lpss: Set enable-bit before waiting for update-bit to go low 
At least on cherrytrail, the update bit will never go low when the
enabled bit is not set.

This causes the backlight on my cube iwork8 air tablet to never turn on
again after being turned off because in the pwm_lpss_apply enable path
pwm_lpss_update will fail causing an error exit and the enable-bit to
never get set. Any following pwm_lpss_apply calls will fail the
pwm_lpss_is_updating check.

Since the docs say that the update bit should be set before the
enable-bit, split pwm_lpss_update into setting the update-bit and
pwm_lpss_wait_for_update, and move the pwm_lpss_wait_for_update call
in the enable path to after setting the enable-bit.

Fixes: 10d56a4 ("pwm: lpss: Avoid reconfiguring while UPDATE bit...")
Cc: Ilkka Koskinen <ilkka.koskinen@intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-04-06 14:48:14 +02:00
Andy Shevchenko
3c1460e934 pwm: lpss: Split Tangier configuration 
As a preparation for special treatment for Broxton we split Tangier
configuration.

Fixes: b89b4b7a3d ("pwm: lpss: pci: Enable PWM module on Intel Edison")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-04-06 14:47:30 +02:00
Linus Torvalds
545b2820c4 pwm: Changes for v4.11-rc1 
This set contains mostly fixes to existing drivers as well as cleanup of
 code that's not been in active use for a while.
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Merge tag 'pwm/for-4.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm

Pull pwm updates from Thierry Reding:
 "This set contains mostly fixes to existing drivers as well as cleanup
  of code that's not been in active use for a while"

* tag 'pwm/for-4.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (27 commits)
  acpi: lpss: call pwm_add_table() for BSW PWM device
  pwm: Try to load modules during pwm_get()
  pwm: Don't hold pwm_lookup_lock longer than necessary
  pwm: Make the PWM_POLARITY flag in DTB optional
  pwm: Print error messages with pr_err() instead of pr_debug()
  pwm: imx: Add polarity inversion support to i.MX's PWMv2
  pwm: imx: doc: Update imx-pwm.txt documentation entry
  pwm: imx: Remove redundant i.MX PWMv2 code
  pwm: imx: Provide atomic PWM support for i.MX PWMv2
  pwm: imx: Move PWMv2 wait for fifo slot code to a separate function
  pwm: imx: Move PWMv2 software reset code to a separate function
  pwm: imx: Rewrite v1 code to facilitate switch to atomic PWM
  pwm: imx: Add separate set of PWM ops for v1 and v2
  pwm: imx: Remove ipg clock and enable per clock when required
  pwm: lpss: Add Intel Gemini Lake PCI ID
  pwm: lpss: Do not export board infos for different PWM types
  pwm: lpss: Avoid reconfiguring while UPDATE bit is still enabled
  pwm: lpss: Switch to new atomic API
  pwm: lpss: Allow duty cycle to be 0
  pwm: lpss: Avoid potential overflow of base_unit
  ...
 2017-03-01 09:46:02 -08:00
Thierry Reding
38b0a526ec Merge branch 'for-4.11/drivers' into for-next 2017-02-10 15:15:56 +01:00
Hans de Goede
b526a31426 pwm: Try to load modules during pwm_get() 
Add a module name string to the pwm_lookup struct and if specified try
to load the module using request_module() if pwmchip_find_by_name() is
unable to find the PWM chip.

This is a last resort to work around drivers that can't - and can't be
made to - deal with deferred probe.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[thierry.reding@gmail.com: rename new macro, reword commit message]
[thierry.reding@gmail.com: add comment explaining use-case]
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 09:36:42 +01:00
Hans de Goede
69efb3439c pwm: Don't hold pwm_lookup_lock longer than necessary 
There is no need to hold pwm_lookup_lock after we're done with looping
over pwm_lookup_list, so release it earlier.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 09:19:26 +01:00
Lothar Wassmann
42883cbc08 pwm: Make the PWM_POLARITY flag in DTB optional 
Change the PWM chip driver registration so that a chip driver that
supports polarity inversion can still be used with DTBs that don't
provide the polarity flag as part of the specifier.

This is done to provide polarity inversion support for the pwm-imx
driver without having to modify all existing DTS files.

Signed-off-by: Lothar Wassmann <LW@KARO-electronics.de>
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Suggested-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 09:13:34 +01:00
Lothar Wassmann
f2dafc0950 pwm: Print error messages with pr_err() instead of pr_debug() 
Make the messages that are printed in case of fatal errors actually
visible to the user without having to recompile the driver with
debugging enabled.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 09:13:30 +01:00
Lukasz Majewski
326ed314fe pwm: imx: Add polarity inversion support to i.MX's PWMv2 
With this patch the polarity settings for i.MX's PWMv2 is now supported
on top of atomic PWM setting

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 09:13:07 +01:00
Lukasz Majewski
871985b154 pwm: imx: Remove redundant i.MX PWMv2 code 
The code providing functionality surpassed by the atomic PWM is not
needed anymore and hence can be removed.

Suggested-by: Stefan Agner <stefan@agner.ch>
Suggested-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 09:12:59 +01:00
Lukasz Majewski
0ca1a11a1d pwm: imx: Provide atomic PWM support for i.MX PWMv2 
This commit provides apply() callback implementation for i.MX's PWMv2.

Suggested-by: Stefan Agner <stefan@agner.ch>
Suggested-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 09:12:52 +01:00
Lukasz Majewski
73b1ff1f3e pwm: imx: Move PWMv2 wait for fifo slot code to a separate function 
The code, which waits for fifo slot, has been extracted from
imx_pwm_config_v2 function and moved to new one - imx_pwm_wait_fifo_slot().

This change reduces the overall size of imx_pwm_config_v2() and prepares
it for atomic PWM operation.

Suggested-by: Stefan Agner <stefan@agner.ch>
Suggested-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 09:12:48 +01:00
Lukasz Majewski
970247a486 pwm: imx: Move PWMv2 software reset code to a separate function 
The software reset code has been extracted from imx_pwm_config_v2 function
and moved to new one - imx_pwm_sw_reset().

This change reduces the overall size of imx_pwm_config_v2() and prepares
it for atomic PWM operation.

Suggested-by: Stefan Agner <stefan@agner.ch>
Suggested-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 09:12:46 +01:00
Lukasz Majewski
b3c088fe02 pwm: imx: Rewrite v1 code to facilitate switch to atomic PWM 
The code has been rewritten to remove "generic" calls to
imx_pwm_{enable|disable|config}.

Such approach would facilitate switch to atomic PWM (a.k.a ->apply())
implementation.

Suggested-by: Stefan Agner <stefan@agner.ch>
Suggested-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 09:12:42 +01:00
Lukasz Majewski
0038922954 pwm: imx: Add separate set of PWM ops for v1 and v2 
This patch provides separate set of PWM operations utilized by i.MX's
v1 and v2 of the PWM hardware.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 09:12:39 +01:00
Sascha Hauer
9fb27fac39 pwm: imx: Remove ipg clock and enable per clock when required 
The use of the ipg clock was introduced with commit 7b27c160c6 ("pwm:
i.MX: fix clock lookup"). In the commit message it was claimed that the
ipg clock is enabled for register accesses. This is true for the
->config() callback, but not for the ->set_enable() callback. Given that
the ipg clock is not consistently enabled for all register accesses we
can assume that either it is not required at all or that the current
code does not work. Remove the ipg clock code for now so that it's no
longer in the way of refactoring the driver.

On the other hand, the i.MX 7 IP requires the peripheral clock to be
enabled before accessing its registers. Since ->config() can be called
when the PWM is disabled (in which case, the peripheral clock is also
disabled), we need to surround the imx->config() with
clk_prepare_enable(per_clk)/clk_disable_unprepare(per_clk) calls.

Note that the driver was working fine for the i.MX 7 IP so far because
the ipg and peripheral clock use the same hardware clock gate, which
guaranteed peripheral clock activation even when ->config() was called
when the PWM was disabled.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Tested-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 09:12:18 +01:00
Mika Westerberg
ae2520540c pwm: lpss: Add Intel Gemini Lake PCI ID 
Intel Gemini Lake PWM is pretty much same as used in Intel Broxton. Add
this new PCI ID to the list of supported devices.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 08:17:18 +01:00
Andy Shevchenko
9900073cf5 pwm: lpss: Do not export board infos for different PWM types 
The PWM LPSS probe drivers just pass a pointer to the exported board
info structures to pwm_lpss_probe() based on device PCI or ACPI ID.

In order to remove the knowledge of specific devices from library part of
the driver and reduce noise in exported namespace just duplicate the
board info structures and stop exporting them.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 08:16:55 +01:00
Ilkka Koskinen
10d56a4cb1 pwm: lpss: Avoid reconfiguring while UPDATE bit is still enabled 
PWM Configuration register has SW_UPDATE bit that is set when a new
configuration is written to the register. The bit is automatically
cleared at the start of the next output cycle by the IP block.

If one writes a new configuration to the register while it still has
the bit enabled, PWM may freeze. That is, while one can still write
to the register, it won't have an effect. Thus, we try to sleep long
enough that the bit gets cleared and make sure the bit is not
enabled while we update the configuration.

Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Tested-by: Richard Griffiths <richard.a.griffiths@intel.com>
Signed-off-by: Ilkka Koskinen <ilkka.koskinen@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 08:15:12 +01:00
Andy Shevchenko
b14e8ceff0 pwm: lpss: Switch to new atomic API 
Instead of doing things separately, which is not so reliable on some platforms,
switch the driver to use new atomic API, i.e. ->apply() callback.

The change has been tested on Intel platforms such as Broxton, BayTrail, and
Merrifield.

Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 08:13:55 +01:00
Andy Shevchenko
b5c050c719 pwm: lpss: Allow duty cycle to be 0 
A duty cycle is represented by values [0..<period>] which reflects [0%..100%].
0% of the duty cycle means always off (logical "0") on output. Allow this in
the driver.

Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 08:13:39 +01:00
Andy Shevchenko
684309e504 pwm: lpss: Avoid potential overflow of base_unit 
The resolution of base_unit is derived from base_unit_bits and thus must be
equal to (2^base_unit_bits - 1). Otherwise frequency and therefore base_unit
might potentially overflow.

Prevent the above by substracting 1 in all cases where base_unit_bits or
derivative is used.

Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-30 08:13:19 +01:00
Benjamin Gaignard
7edf736920 pwm: Add driver for STM32 plaftorm 
This driver adds support for PWM driver on STM32 platform.
The SoC have multiple instances of the hardware IP and each
of them could have small differences: number of channels,
complementary output, auto reload register size...

version 9:
- fix commit message header
- remove one space MODULE_ALIAS

version 8:
- fix comments done by Thierry on version 7

version 6:
- change st,breakinput parameter to make it usuable for stm32f7 too.

version 4:
- detect at probe time hardware capabilities
- fix comments done on v2 and v3
- use PWM atomic ops

version 2:
- only keep one comptatible
- use DT parameters to discover hardware block configuration

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
 2017-01-25 16:11:55 +00:00
Clemens Gruber
8d254a340e pwm: pca9685: Fix period change with same duty cycle 
When first implementing support for changing the output frequency, an
optimization was added to continue the PWM after changing the prescaler
without having to reprogram the ON and OFF registers for the duty cycle,
in case the duty cycle stayed the same. This was flawed, because we
compared the absolute value of the duty cycle in nanoseconds instead of
the ratio to the period.

Fix the problem by removing the shortcut.

Fixes: 01ec847200 ("pwm-pca9685: Support changing the output frequency")
Cc: <stable@vger.kernel.org> # v4.3+
Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-20 07:43:22 +01:00
Bhumika Goyal
b2ec9efc1f pwm: constify pwm_ops structures 
Declare pwm_ops structures as const as they are only stored in the ops
field of a pwm_chip structure. This field is of type const struct pwm_ops
*, so pwm_ops structures having this property can be declared as const.
Done using Coccinelle:

@r1 disable optional_qualifier@
identifier i;
position p;
@@
static struct pwm_ops i@p={...};

@ok1@
identifier r1.i;
position p;
struct pxa_pwm_chip pwm;
struct bfin_pwm_chip bwm;
struct vt8500_chip vp;
struct imx_chip icp;
@@
(
pwm.chip.ops=&i@p
|
bwm.chip.ops=&i@p
|
vp.chip.ops=&i@p
|
icp.chip.ops=&i@p
)

@bad@
position p!={r1.p,ok1.p};
identifier r1.i;
@@
i@p

@depends on !bad disable optional_qualifier@
identifier r1.i;
@@
+const
struct pwm_ops i;

File size details:

   text	   data	    bss	    dec	    hex	filename
   1646	    328	      0	   1974	    7b6	drivers/pwm/pwm-imx.o
   1742	    224	      0	   1966	    7ae	drivers/pwm/pwm-imx.o

   1941	    296	      0	   2237	    8bd	drivers/pwm/pwm-pxa.o
   2037	    192	      0	   2229	    8b5	drivers/pwm/pwm-pxa.o

   1946	    296	      0	   2242	    8c2	drivers/pwm/pwm-vt8500.o
   2050	    192	      0	   2242	    8c2	drivers/pwm/pwm-vt8500.o

The drivers/pwm/pwm-bfin.o file did not compile.

Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-19 00:38:17 +01:00
Scott Branden
5bf22ff32e pwm: bcm-iproc: Update dependencies for compile-test 
Add dependency on COMMON_CLK and allow COMPILE_TEST for broader compile
coverage. Default to Y for IPROC SoCs. This allows the driver to simply
be enabled by selecting PWM.

Signed-off-by: Scott Branden <scott.branden@broadcom.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
[thierry.reding@gmail.com: reword commit message]
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-19 00:38:17 +01:00
Mika Westerberg
bccec89f0a pwm: pca9685: Allow any of the 16 PWMs to be used as a GPIO 
The PCA9685 controller has full on/off bit for each PWM channel. Setting
this bit bypasses the PWM control and the line works just as it would be a
GPIO. Furthermore in Intel Galileo it is actually used as GPIO output for
discreet muxes on the board.

This patch adds GPIO output only support for the driver so that we can
control the muxes on Galileo using standard GPIO interfaces available in
the kernel. GPIO and PWM functionality is exclusive so only one can be
active at a time on a single PWM channel.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-19 00:38:16 +01:00
Thierry Reding
8c0216f377 pwm: Remove .can_sleep from struct pwm_chip 
All PWM devices have been marked as "might sleep" since v4.5, there is
no longer a need to differentiate on a per-chip basis.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-04 09:40:54 +01:00
Thierry Reding
fe2858c8c6 pwm: Remove pwm_can_sleep() 
The last user of this function has been removed, so it is no longer
needed.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2017-01-04 09:39:52 +01:00
Linus Torvalds
57d64e6f5f pwm: Changes for v4.10-rc1 
This is a very tiny pull request, with just a new driver for HiSilicon
 BVT SoCs and a cleanup for the Amlogic Meson driver.
 
 There are other patches on the list, but my timing was really bad this
 time and I ended up not having the time to look at them in enough detail
 to be comfortable merging them.
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Merge tag 'pwm/for-4.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm

Pull pwm updates from Thierry Reding:
 "This is a very tiny pull request, with just a new driver for HiSilicon
  BVT SoCs and a cleanup for the Amlogic Meson driver.

  There are other patches on the list, but my timing was really bad this
  time and I ended up not having the time to look at them in enough
  detail to be comfortable merging them"

* tag 'pwm/for-4.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
  pwm: Add PWM driver for HiSilicon BVT SOCs
  pwm: meson: Remove unneeded platform MODULE_ALIAS
 2016-12-15 11:45:13 -08:00
yuanjian
d09f008108 pwm: Add PWM driver for HiSilicon BVT SOCs 
Add PWM driver for the PWM controller found on HiSilicon BVT SoCs such
as Hi3519V100, Hi3516CV300, etc. The PWM controller is primarily in
charge of controlling the P-Iris lens.

Reviewed-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Jian Yuan <yuanjian12@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-11-29 16:50:12 +01:00
Johan Hovold
0e1614ac84 pwm: Fix device reference leak 
Make sure to drop the reference to the parent device taken by
class_find_device() after "unexporting" any children when deregistering
a PWM chip.

Fixes: 0733424c9b ("pwm: Unexport children before chip removal")
Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-11-29 16:43:24 +01:00
Javier Martinez Canillas
58d5b69363 pwm: meson: Remove unneeded platform MODULE_ALIAS 
The Amlogic Meson is a DT-only platform, which means the devices are
registered via OF and not using the legacy platform devices support.

So there's no need to have a MODULE_ALIAS("platform:meson-pwm") since
the reported uevent MODALIAS to user-space will always be the OF one.

Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-10-21 09:12:41 +02:00
Axel Lin
c699995663 pwm: meson: Add missing spin_lock_init() 
The driver uses the spin_lock but does not initialize it. Fix it.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-10-21 09:10:11 +02:00
Thierry Reding
dc8e6e1e8f Merge branch 'for-4.9/drivers' into for-next 2016-09-08 10:59:30 +02:00
Arnd Bergmann
2fbc487df6 pwm: meson: Handle unknown ID values 
When building with -Wmaybe-uninitialized, we get a couple of harmless
warnings about three functions in this new driver that don't look
safe to the compiler:

drivers/pwm/pwm-meson.c: In function 'meson_pwm_get_state':
drivers/pwm/pwm-meson.c:355:26: error: 'mask' may be used uninitialized in this function [-Werror=maybe-uninitialized]
drivers/pwm/pwm-meson.c: In function 'meson_pwm_disable':
drivers/pwm/pwm-meson.c:263:13: error: 'enable' may be used uninitialized in this function [-Werror=maybe-uninitialized]
drivers/pwm/pwm-meson.c: In function 'meson_pwm_apply':
drivers/pwm/pwm-meson.c:231:13: error: 'clk_shift' may be used uninitialized in this function [-Werror=maybe-uninitialized]
drivers/pwm/pwm-meson.c:231:36: error: 'enable' may be used uninitialized in this function [-Werror=maybe-uninitialized]
drivers/pwm/pwm-meson.c:231:24: error: 'clk_enable' may be used uninitialized in this function [-Werror=maybe-uninitialized]

Specifically, if we have a device with an ID other than 0 or 1,
this would result in undefined behavior. This is currently not
possible, but the compiler cannot be expected to know this.

This patch adds a 'default' clause to let the compiler know
what to do instead, which shuts up the warning and makes the
code slightly more resiliant in case it gets extended to other
identifiers.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-08 10:58:33 +02:00
Lee Jones
7d8a600c91 pwm: sti: Take the opportunity to conduct a little house keeping 
This includes fixing some Coding Style issues and re-ordering and/or
simplifying a little code.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
[thierry.reding@gmail.com: applied some bikeshedding>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-08 10:55:12 +02:00
Lee Jones
85a834c42a pwm: sti: It's now valid for number of PWM channels to be zero 
Setting up the STI PWM IP as capture only, with zero PWM output devices
is a perfectly valid configuration. It is no longer okay to assume that
there must be at least 1 PWM output device. In this patch we make the
default number of PWM output devices zero and only configure channels
explicitly requested.

Reported-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-08 10:55:11 +02:00
Lee Jones
c97267ae83 pwm: sti: Add PWM capture callback 
Once a PWM capture has been initiated, the capture call enables a rising
edge detection interrupt, then waits. Once each of the 3 phase changes
have been recorded the thread then wakes. The remaining part of the call
carries out the relevant calculations and returns a structure filled out
with the capture data.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-08 10:55:11 +02:00
Lee Jones
25eb538096 pwm: sti: Add support for PWM capture interrupts 
Here we're requesting the PWM capture IRQ and supplying the handler that
will be called in the event of an interrupt to handle it.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-08 10:55:10 +02:00
Lee Jones
3f0925b5a8 pwm: sti: Initialise PWM capture device data 
Each PWM capture device is allocated a structure to hold its own state.
During a capture the device may be partaking in one of 3 phases. Initial
(rising) phase change, a subsequent (falling) phase change indicating
end of the duty-cycle phase and finally a final (rising) phase change
indicating the end of the period. The timer value snapshot each event is
held in a variable of the same name, and the phase number (0, 1, 2) is
contained in the index variable. Other device specific information, such
as GPIO pin, the IRQ wait queue and locking is also contained in the
structure. This patch initialises this structure for each of the
available devices.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-08 10:55:09 +02:00
Lee Jones
d66a928dc0 pwm: sti: Supply PWM Capture clock handling 
ST's PWM IP is supplied by 2 different clocks. One for PWM output and
the other for capture. This patch provides clock handling for the
latter.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-08 10:55:09 +02:00
Lee Jones
f66d78faf2 pwm: sti: Supply PWM capture register addresses and bit locations 
This is in preparation for subsequent patches that add support for PWM
capture to this driver.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-08 10:55:08 +02:00
Lee Jones
d81738b76f pwm: sti: Only request clock rate when needed 
In the original code the clock rate was only obtained during
initialisation; however, the rate may change between then and
its use.  This patch ensures the correct rate is acquired just
before use.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-08 10:55:08 +02:00
Lee Jones
c5f94ae639 pwm: sti: Reorganise register names in preparation for new functionality 
Exciting functionality is on the way to this device.  But
before we can add it, we need to do some basic housekeeping
so the additions can be added cleanly.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-08 10:55:07 +02:00
Lee Jones
09022e61d5 pwm: sti: Rename channel => device 
This is to bring the terminology used in the STi PWM driver more
into line with the PWM subsystem.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-08 10:55:07 +02:00
oliver@schinagl.nl
fe0e2cf931 pwm: lpc-18xx: use pwm_set_chip_data 
The lpc-18xx driver currently manipulates the pwm_device struct directly
rather than using the pwm_set_chip_data() function. While the current
method may save a clock cycle or two, using the explicit function call
makes it more obvious that data is set to the local chip data pointer.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Reviewed-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-08 10:55:05 +02:00
Milo Kim
42ddcf4f9e pwm: sunxi: Add H3 support 
H3 PWM controller has same register layout as sun4i driver, so it works
by adding H3 specific data.

Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: linux-pwm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-08 10:55:05 +02:00
Neil Armstrong
211ed63075 pwm: Add support for Meson PWM Controller 
Add support for the PWM controller found in the Amlogic SoCs. This
driver supports the Meson8b and GXBB SoCs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-08 10:55:00 +02:00
Seung-Woo Kim
04d68dea26 pwm: samsung: Fix to use lowest div for large enough modulation bits 
From pwm_samsung_calc_tin(), there is routine to find the lowest divider
possible to generate lower frequency than requested one. But it is
always possible to generate requested frequency with large enough
modulation bits except on s3c24xx, so this patch fixes to use lowest div
for the case. This patch removes following UBSAN warning:

   UBSAN: Undefined behaviour in drivers/pwm/pwm-samsung.c:197:13
   shift exponent 32 is too large for 32-bit type 'long unsigned int'
   [...]
   [<c0670248>] (ubsan_epilogue) from [<c06707b4>] (__ubsan_handle_shift_out_of_bounds+0xd8/0x120)
   [<c06707b4>] (__ubsan_handle_shift_out_of_bounds) from [<c0694b28>] (pwm_samsung_config+0x508/0x6a4)
   [<c0694b28>] (pwm_samsung_config) from [<c069286c>] (pwm_apply_state+0x174/0x40c)
   [<c069286c>] (pwm_apply_state) from [<c0b2e070>] (pwm_fan_probe+0xc8/0x488)
   [<c0b2e070>] (pwm_fan_probe) from [<c07ba8b0>] (platform_drv_probe+0x70/0x150)
   [...]

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-06 10:48:55 +02:00
Jyri Sarha
549c50af25 pwm: pwm-tipwmss: Remove all runtime PM gets/puts 
Remove all pm_runtime_get_sync() and pm_runtime_put_sync() call as well
as the dummy pm_ops from the pwm-tipwmss driver. No registers are being
modified. The runtime PM still needs to be enabled, so that the runtime
PM framework can take care of enabling/disabling the PWMSS clock when
submodules of PWMSS (ECAP or EHRPWM) call runtime PM APIs. With this
change PWMSS clock goes to idle when none of the submodules are in use.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-06 10:48:54 +02:00
Brian Norris
065cfbbb63 pwm: cros-ec: Add __packed to prevent padding 
While the particular usage in question is likely safe (struct
cros_ec_command is 32-bit aligned, followed by <= 32-bit fields), it's
been suggested this is not a great pattern to follow for the general
case -- for example, if we follow a 'struct cros_ec_command' (which is
32-bit- but not 64-bit-aligned) with a struct that starts with a 64-bit
type (e.g., u64), the compiler may add padding.

Let's add __packed, to inform the compiler of our true intention -- to
have no padding between these struct elements -- and to future proof for
any refactorings that might occur.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-06 10:48:54 +02:00
Weiqing Kong
cd4b45ac44 pwm: Add MediaTek MT2701 display PWM driver support 
Use the mtk_pwm_data struction to define different registers
and add MT2701 specific register operations, such as MT2701
doesn't have commit register, needs to disable double buffer
before writing register, and needs to select manual mode
and use PWM_PERIOD/PWM_HIGH_WIDTH.

Signed-off-by: Weiqing Kong <weiqing.kong@mediatek.com>
[thierry.reding@gmail.com: use of_device_get_match_data()]
[thierry.reding@gmail.com: parameterize more consistently]
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-06 10:48:53 +02:00
Jisheng Zhang
bbf0722c1c pwm: berlin: Add suspend/resume support 
This patch adds suspend-to-RAM support to the Berlin PWM driver.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-06 10:48:52 +02:00
David Hsu
0733424c9b pwm: Unexport children before chip removal 
Exported pwm channels aren't removed before the pwmchip and are
leaked. This results in invalid sysfs files. This fix removes
all exported pwm channels before chip removal.

Signed-off-by: David Hsu <davidhsu@google.com>
Fixes: 76abbdde2d ("pwm: Add sysfs interface")
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-05 16:45:39 +02:00
Paul Kocialkowski
45c0ce847a pwm: twl: Reliably disable TWL6030 PWMs 
The current TWL6030 code for the TWL PWM driver does not reliably disable the
PWM output, as tested with LEDs. The previous commit to that driver introduced
that regression.

However, it does make sense to disable the PWM clock after resetting the PWM,
but for some obscure reason, doing it all at once simply doesn't work.

The TWL6030 datasheet mentions that PWMs have to be disabled in two distinct
steps. However, clearing the clock enable bit in a second step (after issuing a
reset first) does not work.

The only approach that works is the one that was in place before the previous
commit to the driver. It consists in enabling the PWM clock after issuing a
reset. This is what TI kernel trees and production code seem to be using.

However, adding an extra step to disable the PWM clock seems to work reliably,
despite looking quite odd.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-09-05 07:13:47 +02:00
Linus Torvalds
a157b3aaa4 pwm: Changes for v4.8-rc1 
This set of changes improve some aspects of the atomic API as well as
 make use of this new API in the regulator framework to allow properly
 dealing with critical regulators controlled by a PWM.
 
 Aside from that there's a bunch of updates and cleanups for existing
 drivers, as well as the addition of new drivers for the Broadcom iProc,
 STMPE and ChromeOS EC controllers.
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Merge tag 'pwm/for-4.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm

Pull pwm updates from Thierry Reding:
 "This set of changes improve some aspects of the atomic API as well as
  make use of this new API in the regulator framework to allow properly
  dealing with critical regulators controlled by a PWM.

  Aside from that there's a bunch of updates and cleanups for existing
  drivers, as well as the addition of new drivers for the Broadcom
  iProc, STMPE and ChromeOS EC controllers"

* tag 'pwm/for-4.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (44 commits)
  regulator: pwm: Document pwm-dutycycle-unit and pwm-dutycycle-range
  regulator: pwm: Support extra continuous mode cases
  pwm: Add ChromeOS EC PWM driver
  dt-bindings: pwm: Add binding for ChromeOS EC PWM
  mfd: cros_ec: Add EC_PWM function definitions
  mfd: cros_ec: Add cros_ec_cmd_xfer_status() helper
  pwm: atmel: Use of_device_get_match_data()
  pwm: atmel: Fix checkpatch warnings
  pwm: atmel: Fix disabling of PWM channels
  dt-bindings: pwm: Add R-Car H3 device tree bindings
  pwm: rcar: Use ARCH_RENESAS
  pwm: tegra: Add support for Tegra186
  dt-bindings: pwm: tegra: Add compatible string for Tegra186
  pwm: tegra: Avoid overflow when calculating duty cycle
  pwm: tegra: Allow 100 % duty cycle
  pwm: tegra: Add support for reset control
  pwm: tegra: Rename mmio_base to regs
  pwm: tegra: Remove useless padding
  pwm: tegra: Drop NUM_PWM macro
  pwm: lpc32xx: Set PWM_PIN_LEVEL bit to default value
  ...
 2016-08-06 00:01:33 -04:00
Linus Torvalds
43a0a98aa8 ARM: SoC driver updates for v4.8 
Driver updates for ARM SoCs.
 
 A slew of changes this release cycle. The reset driver tree, that we merge
 through arm-soc for historical reasons, is also sizable this time around.
 
 Among the changes:
 
  - clps711x: Treewide changes to compatible strings, merged here for simplicity.
  - Qualcomm: SCM firmware driver cleanups, move to platform driver
  - ux500: Major cleanups, removal of old mach-specific infrastructure.
  - Atmel external bus memory driver
  - Move of brcmstb platform to the rest of bcm
  - PMC driver updates for tegra, various fixes and improvements
  - Samsung platform driver updates to support 64-bit Exynos platforms
  - Reset controller cleanups moving to devm_reset_controller_register() APIs
  - Reset controller driver for Amlogic Meson
  - Reset controller driver for Hisilicon hi6220
  - ARM SCPI power domain support
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Olof Johansson:
 "Driver updates for ARM SoCs.

  A slew of changes this release cycle.  The reset driver tree, that we
  merge through arm-soc for historical reasons, is also sizable this
  time around.

  Among the changes:

   - clps711x: Treewide changes to compatible strings, merged here for simplicity.
   - Qualcomm: SCM firmware driver cleanups, move to platform driver
   - ux500: Major cleanups, removal of old mach-specific infrastructure.
   - Atmel external bus memory driver
   - Move of brcmstb platform to the rest of bcm
   - PMC driver updates for tegra, various fixes and improvements
   - Samsung platform driver updates to support 64-bit Exynos platforms
   - Reset controller cleanups moving to devm_reset_controller_register() APIs
   - Reset controller driver for Amlogic Meson
   - Reset controller driver for Hisilicon hi6220
   - ARM SCPI power domain support"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (100 commits)
  ARM: ux500: consolidate base platform files
  ARM: ux500: move soc_id driver to drivers/soc
  ARM: ux500: call ux500_setup_id later
  ARM: ux500: consolidate soc_device code in id.c
  ARM: ux500: remove cpu_is_u* helpers
  ARM: ux500: use CLK_OF_DECLARE()
  ARM: ux500: move l2x0 init to .init_irq
  mfd: db8500 stop passing around platform data
  ASoC: ab8500-codec: remove platform data based probe
  ARM: ux500: move ab8500_regulator_plat_data into driver
  ARM: ux500: remove unused regulator data
  soc: raspberrypi-power: add CONFIG_OF dependency
  firmware: scpi: add CONFIG_OF dependency
  video: clps711x-fb: Changing the compatibility string to match with the smallest supported chip
  input: clps711x-keypad: Changing the compatibility string to match with the smallest supported chip
  pwm: clps711x: Changing the compatibility string to match with the smallest supported chip
  serial: clps711x: Changing the compatibility string to match with the smallest supported chip
  irqchip: clps711x: Changing the compatibility string to match with the smallest supported chip
  clocksource: clps711x: Changing the compatibility string to match with the smallest supported chip
  clk: clps711x: Changing the compatibility string to match with the smallest supported chip
  ...
 2016-08-01 18:36:01 -04:00
Thierry Reding
070d9a9306 Merge branch 'for-4.8/drivers' into for-next 2016-07-25 16:23:39 +02:00
Thierry Reding
bd2686122d Merge branch 'for-4.8/capture' into for-next 2016-07-25 16:23:39 +02:00
Brian Norris
1f0d3bb027 pwm: Add ChromeOS EC PWM driver 
Use the new ChromeOS EC EC_CMD_PWM_{GET,SET}_DUTY commands to control
one or more PWMs attached to the Embedded Controller. Because the EC
allows us to modify the duty cycle (as a percentage, where U16_MAX is
100%) but not the period, we assign the period a fixed value of
EC_PWM_MAX_DUTY and reject all attempts to change it.

This driver supports only device tree at the moment, because that
provides a very flexible way of describing the relationship between PWMs
and their consumer devices (e.g., backlight). On a non-DT system, we'll
probably want to use the non-GENERIC addressing (i.e., we'll need to
make special device instances that will use EC_PWM_TYPE_KB_LIGHT or
EC_PWM_TYPE_DISPLAY_LIGHT), as well as the relatively inflexible
pwm_lookup infrastructure for matching devices. Defer that work for now.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-25 10:40:41 +02:00
Thierry Reding
017bb04e84 pwm: atmel: Use of_device_get_match_data() 
Use of_device_get_match_data() instead of an open-coded variant.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:36 +02:00
Thierry Reding
313b78efea pwm: atmel: Fix checkpatch warnings 
Avoid an overly long line by moving a comment around, and remove a use
of else-after-return.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:36 +02:00
Guillermo Rodriguez
f718c54c1a pwm: atmel: Fix disabling of PWM channels 
When disabling a PWM channel, the PWM clock was being stopped
immediately after writing to PWM_DIS. As a result, the disabling
of the PWM channel did not complete properly, and the PWM output
might be left at the wrong level.

Fix this by waiting for the channel to be effectively disabled
(by checking the PWM_SR register) before disabling the clock.

Signed-off-by: Guillermo Rodriguez <guille.rodriguez@gmail.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:35 +02:00
Ryo Kodama
48169988cf pwm: rcar: Use ARCH_RENESAS 
Replace ARCH_RCAR_GEN{1,2} with ARCH_RENESAS in order to support R-Car Gen3.

Signed-off-by: Ryo Kodama <ryo.kodama.vz@renesas.com>
Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:34 +02:00
Laxman Dewangan
e9be88a2f0 pwm: tegra: Add support for Tegra186 
Tegra186 has multiple PWM controllers with only one output instead of
one controller with four outputs in earlier SoC generations.

Add support for Tegra186 and detect the number of PWM outputs using
device tree match data.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:34 +02:00
Hyong Bin Kim
b979ed5314 pwm: tegra: Avoid overflow when calculating duty cycle 
duty_ns * (1 << PWM_DUTY_WIDTH) could overflow in integer calculation
when the PWM rate is low. Hence do all calculation on unsigned long long
to avoid overflow.

Signed-off-by: Hyong Bin Kim <hyongbink@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:32 +02:00
Victor(Weiguo) Pan
e0ee1a75f4 pwm: tegra: Allow 100 % duty cycle 
To get 100 % duty cycle (always high), pulse width needs to be set to
256.

Signed-off-by: Victor(Weiguo) Pan <wpan@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:32 +02:00
Rohith Seelaboyina
5dfbd2bd54 pwm: tegra: Add support for reset control 
Add reset control of the PWM controller to reset it before
accessing the PWM register.

Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:31 +02:00
Thierry Reding
4f57f5a01f pwm: tegra: Rename mmio_base to regs 
The former is much longer to type and is ambiguous because the value
stored in the field is not the (physical) base address of the memory-
mapped I/O registers, but the virtual address of those registers as
mapped through the MMU.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:31 +02:00
Thierry Reding
e17c0b2258 pwm: tegra: Remove useless padding 
Use single spaces to separate data type from field names in structure
definitions.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:30 +02:00
Thierry Reding
c009c56475 pwm: tegra: Drop NUM_PWM macro 
This macro is used to initialize the ->npwm field of the PWM chip. Use a
literal instead and make all other places rely on ->npwm.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:30 +02:00
Sylvain Lemieux
acfd92fdfb pwm: lpc32xx: Set PWM_PIN_LEVEL bit to default value 
The PWM_PIN_LEVEL bit is leave unset by the kernel PWM driver.

Prior to commit 08ee77b5a5,
the PWM_PIN_LEVEL bit was always clear when the PWM was disable
and a 0 logic level was apply to the output.

According to the LPC32x0 User Manual [1],
the default value for bit 30 (PWM_PIN_LEVEL) is 0.

This change initialize the pin level to 0 (default value) and
update the register value accordingly.

[1] http://www.nxp.com/documents/user_manual/UM10326.pdf

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:29 +02:00
Linus Walleij
ef1f09eca7 pwm: Add a driver for the STMPE PWM 
This adds a driver for the PWM block found in chips of the STMPE 24xx
series of multi-purpose I2C expanders. (I think STMPE means ST
Microelectronics Multi-Purpose Expander.) This PWM was designed in
accordance with Nokia specifications and is kind of weird and usually
just switched between max and zero duty cycle. However it is indeed a
PWM so it needs to live in the PWM subsystem.

This PWM is mostly used for white LED backlight.

Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:29 +02:00
Boris Brezillon
2bf1c98aa5 pwm: rockchip: Add support for atomic update 
Implement the ->apply() function to add support for atomic update.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:28 +02:00
Boris Brezillon
48cf973cae pwm: rockchip: Avoid glitches on already running PWMs 
The current logic will disable the PWM clk even if the PWM was left
enabled by the bootloader (because it's controlling a critical device
like a regulator for example).
Keep the PWM clk enabled if the PWM is enabled to avoid any glitches.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:27 +02:00
Boris Brezillon
1ebb74cf35 pwm: rockchip: Add support for hardware readout 
Implement the ->get_state() function to expose initial state.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:27 +02:00
Boris Brezillon
12f9ce4a51 pwm: rockchip: Fix period and duty cycle approximation 
The current implementation always round down the duty and period values,
while it would be better to round them to the closest integer.

These changes are needed in preparation of atomic update support to
prevent a period/duty cycle drift when executing several times the
'pwm_get_state() / modify / pwm_apply_state()' sequence.

Say you have an expected period of 3.333 us and a clk rate of
112.666667 MHz -- the clock frequency doesn't divide evenly, so the
period (stashed in nanoseconds) shrinks when we convert to the register
value and back, as follows:

  pwm_apply_state(): register = period * 112666667 / 1000000000;
  pwm_get_state(): period = register * 1000000000 / 112666667;

or in other words:

  period = period * 112666667 / 1000000000 * 1000000000 / 112666667;

which yields a sequence like:

  3333 -> 3328
  3328 -> 3319
  3319 -> 3310
  3310 -> 3301
  3301 -> 3292
  3292 -> ... (etc) ...

With this patch, we'd see instead:

  period = div_round_closest(period * 112666667, 1000000000) *
                   1000000000 / 112666667;

which yields a stable sequence:

  3333 -> 3337
  3337 -> 3337
  3337 -> ... (etc) ...

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:26 +02:00
Yendapally Reddy Dhananjaya Reddy
daa5abc41c pwm: Add support for Broadcom iProc PWM controller 
Add support for the PWM controller present in Broadcom's iProc family of
SoCs. It has been tested on the  Northstar+ bcm958625HR board.

Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
[thierry.reding@gmail.com: bunch of coding style fixes, cleanups]
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:25 +02:00
Andy Shevchenko
d9cd4a7369 pwm: lpss: Move clk_rate check to ->probe() 
There is no need to check each time if the clk_rate defined or not when we call
pwm_lpss_config(). Move the check to ->probe() instead.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:49:24 +02:00
Andy Shevchenko
b89b4b7a3d pwm: lpss: pci: Enable PWM module on Intel Edison 
Intel Edison has 4 PWM channels on the die with the same IP as in
Broxton. Enable it.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:07:25 +02:00
Mika Westerberg
ab248b6039 pwm: lpss: Prevent on_time_div overflow on lower frequencies 
If duty_ns is large enough multiplying it by 255 overflows and results
wrong duty cycle value being programmed. For example with 10ms duty when
period is 20ms (50%) we get

  255 * 10000000 / 20000000 = -87

because 255 * 10000000 overlows int. Whereas correct value should be

  255 * 10000000 / 20000000 = 127

Fix this by using unsigned long long as type for on_time_div and changing
integer literals to use proper type annotation.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:07:24 +02:00
Dan O'Donovan
e5ca42458b pwm: lpss: Fix base_unit calculation for PWM frequency 
The base_unit calculation applies an offset of 0x2 which adds
significant error for lower frequencies and doesn't appear to be
warranted - rounding the division result gives a correct value.

Also, the upper limit check for base_unit is off-by-one; the upper
nibble of base_unit is invalid if >=128 according to the Table 88
in the Z8000 Processor Series Datasheet Volume 1 (Rev. 2).

Verified on UP Board (Cherry Trail) and Minnowboard Max (Bay Trail).

Signed-off-by: Dan O'Donovan <dan@emutex.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:07:23 +02:00
Cooper Jr., Franklin
cc37655e6b pwm: pwm-ti*: Remove support for local clock gating 
The PWMSS local clock gating registers have no real purpose on OMAP ARM
devices. These registers were left over registers from DSP IP where the
PRCM doesn't exist. There is a silicon bug where gating and ungating clocks
don't function properly. TRMs will be update to indicate that these
registers shouldn't be touched.

Therefore, all code that accesses the PWMSS_CLKCONFIG or PWMSS_CLKSTATUS
will be removed by this patch with zero loss of functionality by the ECAP
and EPWM drivers.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-11 12:07:18 +02:00
Cooper Jr., Franklin
ae5200d227 pwm: pwm-ti*: Get the clock from the PWMSS parent when using old bindings 
When using the old eCAP and ePWM bindings for AM335x and AM437x the clock
can be retrieved from the PWMSS parent. Newer bindings will insure that
this clock is provided via device tree.

Therefore, update this driver to support the newer and older bindings. In
the case of the older binding being used give a warning.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
[thierry.reding@gmail.com: rewrite slightly for readability]
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-07-08 17:53:37 +02:00
Arnd Bergmann
82be1178ee Fix a long time regression for ir-rx51 driver for n900 device tree 
booting.
 
 This driver has been unusable with multiarch because of the hardware
 timer access. With the recent PWM changes, we can finally fix the
 driver for multiarch and device tree support. And naturally there
 is no rush for these for the -rc cycle, these can wait for the
 merge window.
 
 The PWM changes have been acked by Thierry. For the media changes
 I did not get an ack from Mauro but he was Cc'd in the discussion
 and these changes do not conflict with other media changes.
 
 After this series we can drop the remaining omap3 legacy booting
 board files finally.
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Merge tag 'omap-for-v4.8/ir-rx51-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers

Merge "omap ir-rx51 driver fixes for multiarch for v4.8 merge window"
from Tony Lindgren:

Fix a long time regression for ir-rx51 driver for n900 device tree
booting.

This driver has been unusable with multiarch because of the hardware
timer access. With the recent PWM changes, we can finally fix the
driver for multiarch and device tree support. And naturally there
is no rush for these for the -rc cycle, these can wait for the
merge window.

The PWM changes have been acked by Thierry. For the media changes
I did not get an ack from Mauro but he was Cc'd in the discussion
and these changes do not conflict with other media changes.

After this series we can drop the remaining omap3 legacy booting
board files finally.

* tag 'omap-for-v4.8/ir-rx51-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ir-rx51: use hrtimer instead of dmtimer
  ir-rx51: add DT support to driver
  ir-rx51: use PWM framework instead of OMAP dmtimer
  pwm: omap-dmtimer: Allow for setting dmtimer clock source
  ir-rx51: Fix build after multiarch changes broke it
 2016-07-07 14:32:08 +02:00
Alexander Shiyan
ba60ae1dc0 pwm: clps711x: Changing the compatibility string to match with the smallest supported chip 
This patch changes the compatibility string to match with the smallest
supported chip (EP7209). Since the DT-support for this CPU is not yet
announced, this change is safe.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2016-07-06 17:38:17 +02:00
Ivaylo Dimitrov
a74a198249 pwm: omap-dmtimer: Allow for setting dmtimer clock source 
OMAP GP timers can have different input clocks that allow different PWM
frequencies. However, there is no other way of setting the clock source but
through clocks or clock-names properties of the timer itself. This limits
PWM functionality to only the frequencies allowed by the particular clock
source. Allowing setting the clock source by PWM rather than by timer
allows different PWMs to have different ranges by not hard-wiring the clock
source to the timer.

Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Pali Rohár <pali.rohar@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2016-06-29 21:54:00 -07:00
Boris Brezillon
cc51846ba8 pwm: atmel-hlcdc: Fix default PWM polarity 
The PWM device exposed by the HLCDC IP is configured with an inverted
polarity by default. Registering the PWM chip with the normal polarity
was not a problem before commit 42e8992c58d4 ("pwm: Add core
infrastructure to allow atomic updates") because the ->set_polarity()
hook was called no matter the current polarity state, but this is no longer
the case.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-06-14 10:51:45 +02:00
Lee Jones
1a366fe915 pwm: sysfs: Add PWM capture support 
Allow a user to read PWM capture results from sysfs. To start a capture
and read the result, simply read the file:

  $ cat $PWMCHIP/capture

The output format is "<period> <duty cycle>".

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-06-10 16:01:40 +02:00
Lee Jones
3a3d1a4e32 pwm: Add PWM capture support 
Supply a PWM capture callback op in order to pass back information
obtained by running analysis on a PWM signal. This would normally (at
least during testing) be called from the sysfs routines with a view to
printing out PWM capture data which has been encoded into a string.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
[thierry.reding@gmail.com: make capture data unsigned int for symmetry]
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-06-10 16:01:35 +02:00
Ryo Kodama
fe5aa34d6e pwm: sysfs: Get return value from pwm_apply_state() 
This patch adds to check the return value from pwm_apply_state()
used in enable_store(). The error of enable_store() doesn't work
if the return value doesn't received.

Signed-off-by: Ryo Kodama <ryo.kodama.vz@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Fixes: 39100ceea7 ("pwm: Switch to the atomic API")
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-06-10 14:24:40 +02:00
Brian Norris
ef2bf4997f pwm: Improve args checking in pwm_apply_state() 
It seems like in the process of refactoring pwm_config() to utilize the
newly-introduced pwm_apply_state() API, some args/bounds checking was
dropped.

In particular, I noted that we are now allowing invalid period
selections, e.g.:

  # echo 1 > /sys/class/pwm/pwmchip0/export
  # cat /sys/class/pwm/pwmchip0/pwm1/period
  100
  # echo 101 > /sys/class/pwm/pwmchip0/pwm1/duty_cycle
  [... driver may or may not reject the value, or trigger some logic bug ...]

It's better to see:

  # echo 1 > /sys/class/pwm/pwmchip0/export
  # cat /sys/class/pwm/pwmchip0/pwm1/period
  100
  # echo 101 > /sys/class/pwm/pwmchip0/pwm1/duty_cycle
  -bash: echo: write error: Invalid argument

This patch reintroduces some bounds checks in both pwm_config() (for its
signed parameters; we don't want to convert negative values into large
unsigned values) and in pwm_apply_state() (which fix the above described
behavior, as well as other potential API misuses).

Fixes: 5ec803edcb ("pwm: Add core infrastructure to allow atomic updates")
Signed-off-by: Brian Norris <briannorris@chromium.org>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-06-10 14:21:00 +02:00
Linus Torvalds
ecc5fbd5ef pwm: Changes for v4.7-rc1 
This set of changes introduces an atomic API to the PWM subsystem. This
 is influenced by the DRM atomic API that was introduced a while back,
 though it is obviously a lot simpler. The fundamental idea remains the
 same, though: drivers provide a single callback to implement the atomic
 configuration of a PWM channel.
 
 As a side-effect the PWM subsystem gains the ability for initial state
 retrieval, so that the logical state mirrors that of the hardware. Many
 use-cases don't care about this, but for others it is essential.
 
 These new features require changes in all users, which these patches
 take care of. The core is transitioned to use the atomic callback if
 available and provides a fallback mechanism for other drivers.
 
 Changes to transition users and drivers to the atomic API are postponed
 to v4.8.
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Merge tag 'pwm/for-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm

Pull pwm updates from Thierry Reding:
 "This set of changes introduces an atomic API to the PWM subsystem.
  This is influenced by the DRM atomic API that was introduced a while
  back, though it is obviously a lot simpler.  The fundamental idea
  remains the same, though: drivers provide a single callback to
  implement the atomic configuration of a PWM channel.

  As a side-effect the PWM subsystem gains the ability for initial state
  retrieval, so that the logical state mirrors that of the hardware.
  Many use-cases don't care about this, but for others it is essential.

  These new features require changes in all users, which these patches
  take care of.  The core is transitioned to use the atomic callback if
  available and provides a fallback mechanism for other drivers.

  Changes to transition users and drivers to the atomic API are
  postponed to v4.8"

* tag 'pwm/for-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (30 commits)
  pwm: Add information about polarity, duty cycle and period to debugfs
  pwm: Switch to the atomic API
  pwm: Update documentation
  pwm: Add core infrastructure to allow atomic updates
  pwm: Add hardware readout infrastructure
  pwm: Move the enabled/disabled info into pwm_state
  pwm: Introduce the pwm_state concept
  pwm: Keep PWM state in sync with hardware state
  ARM: Explicitly apply PWM config extracted from pwm_args
  drm: i915: Explicitly apply PWM config extracted from pwm_args
  input: misc: pwm-beeper: Explicitly apply PWM config extracted from pwm_args
  input: misc: max8997: Explicitly apply PWM config extracted from pwm_args
  backlight: lm3630a: explicitly apply PWM config extracted from pwm_args
  backlight: lp855x: Explicitly apply PWM config extracted from pwm_args
  backlight: lp8788: Explicitly apply PWM config extracted from pwm_args
  backlight: pwm_bl: Use pwm_get_args() where appropriate
  fbdev: ssd1307fb: Use pwm_get_args() where appropriate
  regulator: pwm: Use pwm_get_args() where appropriate
  leds: pwm: Use pwm_get_args() where appropriate
  input: misc: max77693: Use pwm_get_args() where appropriate
  ...
 2016-05-25 10:40:15 -07:00
Thierry Reding
18c588786c Merge branch 'for-4.7/pwm-atomic' into for-next 2016-05-17 14:57:58 +02:00
Thierry Reding
bf5dd9abcb Merge branch 'for-4.7/pwm-args' into for-next 2016-05-17 14:57:47 +02:00
Heiko Stübner
23e3523f5d pwm: Add information about polarity, duty cycle and period to debugfs 
The PWM states make it possible to also output the polarity, duty cycle
and period information in the debugfs summary output. This simplifies
gathering information about PWMs without needing to walk through the
sysfs attributes of every PWM.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[thierry.reding@gmail.com: use more spaces in debugfs output]
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-05-17 14:48:05 +02:00
Boris Brezillon
39100ceea7 pwm: Switch to the atomic API 
Replace legacy pwm_get/set_xxx() and pwm_config/enable/disable() calls
by pwm_get/apply_state().

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-05-17 14:48:04 +02:00
Boris Brezillon
5ec803edcb pwm: Add core infrastructure to allow atomic updates 
Add an ->apply() method to the pwm_ops struct to allow PWM drivers to
implement atomic updates. This method is preferred over the ->enable(),
->disable() and ->config() methods if available.

Add the pwm_apply_state() function to the PWM user API.

Note that the pwm_apply_state() does not guarantee the atomicity of the
update operation, it all depends on the availability and implementation
of the ->apply() method.

pwm_enable/disable/set_polarity/config() are now implemented as wrappers
around the pwm_apply_state() function.

pwm_adjust_config() is allowing smooth handover between the bootloader
and the kernel. This function tries to adapt the current PWM state to
the PWM arguments coming from a PWM lookup table or a DT definition
without changing the duty_cycle/period proportion.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[thierry.reding@gmail.com: fix a couple of typos]
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-05-17 14:48:03 +02:00
Boris Brezillon
15fa8a43c1 pwm: Add hardware readout infrastructure 
Add a ->get_state() function to the pwm_ops struct to let PWM drivers
initialize the PWM state attached to a PWM device.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-05-17 14:48:03 +02:00
Boris Brezillon
09a7e4a3d9 pwm: Move the enabled/disabled info into pwm_state 
Prepare the transition to PWM atomic update by moving the enabled and
disabled state into the pwm_state struct. This way we can easily update
the whole PWM state by copying the new state in the ->state field.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-05-17 14:48:02 +02:00
Boris Brezillon
43a276b003 pwm: Introduce the pwm_state concept 
The PWM state, represented by its period, duty_cycle and polarity is
currently directly stored in the PWM device. Declare a pwm_state
structure embedding those field so that we can later use this struct
to atomically update all the PWM parameters at once.

All pwm_get_xxx() helpers are now implemented as wrappers around
pwm_get_state().

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-05-17 14:48:02 +02:00
Boris Brezillon
a8c3862551 pwm: Keep PWM state in sync with hardware state 
Before the introduction of pwm_args, the core was resetting the PWM
period and polarity states to the reference values (those provided
through the DT, a PWM lookup table or hardcoded in the driver).

Now that all PWM users are correctly using pwm_args to configure their
PWM device, we can safely remove the pwm_apply_args() call in pwm_get()
and of_pwm_get().

We can also get rid of the pwm_set_period() call in pwm_apply_args(),
because PWM users are now directly using pargs->period instead of
pwm_get_period(). By doing that we avoid messing with the current PWM
period.

The only remaining bit in pwm_apply_args() is the initial polarity
setting, and it should go away when all PWM users have been patched to
use the atomic API (with this API the polarity will be set along with
other PWM arguments when configuring the PWM).

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-05-17 14:47:30 +02:00
Boris Brezillon
4b58896f72 pwm: Use pwm_get/set_xxx() helpers where appropriate 
Use pwm_get/set_xxx() helpers instead of directly accessing the pwm->xxx
field. Doing that will ease adaptation of the PWM framework to support
atomic update.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-05-17 14:44:59 +02:00
Boris BREZILLON
459a25afe9 pwm: Get rid of pwm->lock 
PWM devices are not protected against concurrent accesses. The lock in
struct pwm_device might let PWM users think it is, but it's actually
only protecting the enabled state.

Removing this lock should be fine as long as all PWM users are aware
that accesses to the PWM device have to be serialized, which seems to be
the case for all of them except the sysfs interface. Patch the sysfs
code by adding a lock to the pwm_export struct and making sure it's
taken for all relevant accesses to the exported PWM device.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-05-17 14:44:59 +02:00
Boris BREZILLON
3587c26090 pwm: rcar: Make use of pwm_is_enabled() 
Commit 5c31252c4a ("pwm: Add the pwm_is_enabled() helper") introduced
a new function to test whether a PWM device is enabled or not without
manipulating PWM internal fields.

Hiding this is necessary if we want to smoothly move to the atomic PWM
config approach without impacting PWM drivers. Fix this driver to use
pwm_is_enabled() instead of directly accessing the ->flags field.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-05-17 14:44:57 +02:00
Boris Brezillon
fbd45a1298 pwm: Fix pwm_apply_args() call sites 
pwm_apply_args() is supposed to initialize a PWM device according to the
arguments provided by the DT or the PWM lookup, but this function was
called inside pwm_device_request(), which in turn was called before the
core had a chance to initialize the pwm->args fields.

Fix that by calling pwm_apply_args directly in pwm_get() and of_pwm_get()
after initializing pwm->args field.

This commit also fixes an invalid pointer dereference introduced by
commit e39c0df1be ("pwm: Introduce the pwm_args concept").

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes: e39c0df1be ("pwm: Introduce the pwm_args concept")
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-05-17 14:41:18 +02:00
Mark Brown
39d652e066 Merge remote-tracking branches 'regulator/topic/pwm', 'regulator/topic/qcom-spmi', 'regulator/topic/rk808' and 'regulator/topic/s2mps11' into regulator-next 2016-05-13 14:23:46 +01:00
Thierry Reding
2907f8abb7 pwm: Use kcalloc() instead of kzalloc() 
kcalloc() should be preferred for allocations of arrays over kzalloc()
with multiplication.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-05-03 13:57:05 +02:00
Thierry Reding
83a98864ff pwm: Add missing newline 
checkpatch requires that declarations be separated from code by a blank
line. Add one for readability and to silence the warning.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-05-03 13:57:03 +02:00
Boris Brezillon
e39c0df1be pwm: Introduce the pwm_args concept 
Currently the PWM core mixes the current PWM state with the per-platform
reference config (specified through the PWM lookup table, DT definition
or directly hardcoded in PWM drivers).

Create a struct pwm_args to store this reference configuration, so that
PWM users can differentiate between the current and reference
configurations.

Patch all places where pwm->args should be initialized. We keep the
pwm_set_polarity/period() calls until all PWM users are patched to use
pwm_args instead of pwm_get_period/polarity().

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[thierry.reding@gmail.com: reword kerneldoc comments]
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-05-03 13:44:37 +02:00
Stefan Agner
ad06fdeeef pwm: fsl-ftm: Use flat regmap cache 
Use flat regmap cache to avoid lockdep warning at probe:

[    0.697285] WARNING: CPU: 0 PID: 1 at kernel/locking/lockdep.c:2755 lockdep_trace_alloc+0x15c/0x160()
[    0.697449] DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags))

The RB-tree regmap cache needs to allocate new space on first writes.
However, allocations in an atomic context (e.g. when a spinlock is held)
are not allowed. The function regmap_write calls map->lock, which
acquires a spinlock in the fast_io case. Since the pwm-fsl-ftm driver
uses MMIO, the regmap bus of type regmap_mmio is being used which has
fast_io set to true.

The MMIO space of the pwm-fsl-ftm driver is reasonable condense, hence
using the much faster flat regmap cache is anyway the better choice.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-04-14 16:54:00 +02:00
David Rivshin
922201d129 pwm: omap-dmtimer: Add debug message for effective period and duty cycle 
After going through the math and constraints checking to compute load
and match values, it is helpful to know what the resultant period and
duty cycle are.

Signed-off-by: David Rivshin <drivshin@allworx.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-03-23 17:11:48 +01:00
David Rivshin
7b0883f338 pwm: omap-dmtimer: Round load and match values rather than truncate 
When converting period and duty_cycle from nanoseconds to fclk cycles,
the error introduced by the integer division can be appreciable, especially
in the case of slow fclk or short period. Use DIV_ROUND_CLOSEST_ULL() so
that the error is kept to +/- 0.5 clock cycles.

Fixes: 6604c6556d ("pwm: Add PWM driver for OMAP using dual-mode timers")
Signed-off-by: David Rivshin <drivshin@allworx.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-03-23 17:11:47 +01:00
David Rivshin
cd37888142 pwm: omap-dmtimer: Add sanity checking for load and match values 
Add sanity checking to ensure that we do not program load or match values
that are out of range if a user requests period or duty_cycle values which
are not achievable. The match value cannot be less than the load value (but
can be equal), and neither can be 0xffffffff. This means that there must be
at least one fclk cycle between load and match, and another between match
and overflow.

Fixes: 6604c6556d ("pwm: Add PWM driver for OMAP using dual-mode timers")
Signed-off-by: David Rivshin <drivshin@allworx.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
[thierry.reding@gmail.com: minor coding style cleanups]
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-03-23 17:11:46 +01:00
David Rivshin
f8caa79226 pwm: omap-dmtimer: Fix inaccurate period and duty cycle calculations 
Fix the calculation of load_value and match_value. Currently they
are slightly too low, which produces a noticeably wrong PWM rate with
sufficiently short periods (i.e. when 1/period approaches clk_rate/2).

Example:
 clk_rate=32768Hz, period=122070ns, duty_cycle=61035ns (8192Hz/50% PWM)
 Correct values: load = 0xfffffffc, match = 0xfffffffd
 Current values: load = 0xfffffffa, match = 0xfffffffc
 effective PWM: period=183105ns, duty_cycle=91553ns (5461Hz/50% PWM)

Fixes: 6604c6556d ("pwm: Add PWM driver for OMAP using dual-mode timers")
Signed-off-by: David Rivshin <drivshin@allworx.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-03-23 17:11:45 +01:00
Vladimir Zapolskiy
c5857e3f94 pwm: brcmstb: Fix check of devm_ioremap_resource() return code 
The change fixes potential oops while accessing iomem on invalid address
if devm_ioremap_resource() fails due to some reason.

The devm_ioremap_resource() function returns ERR_PTR() and never returns
NULL, which makes useless a following check for NULL.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Fixes: 3a9f595702 ("pwm: Add Broadcom BCM7038 PWM controller support")
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-03-23 17:11:45 +01:00
Simon Horman
03d99531ae pwm: rcar: Depend on ARCH_RENESAS instead of ARCH_SHMOBILE 
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a
more appropriate name than SHMOBILE for the majority of Renesas ARM
based SoCs.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-03-23 17:11:44 +01:00
Wolfram Sang
0e47b5981a pwm: lpc18xx-sct: Test clock rate to avoid division by 0 
The clk API may return 0 on clk_get_rate(), so we should check the
result before using it as a divisor.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-03-23 17:11:29 +01:00
Wolfram Sang
bea307c16a pwm: img: Test clock rate to avoid division by 0 
The clk API may return 0 on clk_get_rate(), so we should check the
result before using it as a divisor.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-03-23 17:11:02 +01:00
Thierry Reding
ff01c944cf pwm: Mark all devices as "might sleep" 
Commit d1cd214277 ("pwm: Set enable state properly on failed call to
enable") introduced a mutex that is needed to protect internal state of
PWM devices. Since that mutex is acquired in pwm_set_polarity() and in
pwm_enable() and might potentially block, all PWM devices effectively
become "might sleep".

It's rather pointless to keep the .can_sleep field around, but given
that there are external users let's postpone the removal for the next
release cycle.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-01-21 15:04:59 +01:00
Dan Carpenter
074726402b pwm: omap-dmtimer: Potential NULL dereference on error 
"omap" is NULL so we can't dereference it.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-01-04 08:58:33 +01:00
Vegard Nossum
36d5be4bc9 pwm: add HAS_IOMEM dependency to PWM_FSL_FTM 
Ran into this on UML:

drivers/built-in.o: In function `fsl_pwm_probe':
linux/drivers/pwm/pwm-fsl-ftm.c:436: undefined reference to `devm_ioremap_resource'
collect2: error: ld returned 1 exit status

devm_ioremap_resource() is defined only when HAS_IOMEM is selected.

Signed-off-by: Vegard Nossum <vegard.nossum@oracle.com>
Cc: Xiubo Li <Li.Xiubo@freescale.com>
Cc: Alison Wang <b18965@freescale.com>
Cc: Jingchang Lu <b35083@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Yuan Yao <yao.yuan@freescale.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2016-01-04 08:55:03 +01:00
Neil Armstrong
6604c6556d pwm: Add PWM driver for OMAP using dual-mode timers 
Adds support for using a OMAP dual-mode timer with PWM capability
as a Linux PWM device. The driver controls the timer by using the
dmtimer API.

Add a platform_data structure for each pwm-omap-dmtimer nodes containing
the dmtimers functions in order to get driver not rely on platform
specific functions.

Cc: Grant Erickson <marathon96@gmail.com>
Cc: NeilBrown <neilb@suse.de>
Cc: Joachim Eastwood <manabian@gmail.com>
Suggested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Tony Lindgren <tony@atomide.com>
[thierry.reding@gmail.com: coding style bikeshed, fix timer leak]
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2015-12-16 17:25:37 +01:00
Ryo Kodama
72c16a9f98 pwm: rcar: Improve accuracy of frequency division setting 
From: Ryo Kodama <ryo.kodama.vz@renesas.com>

When period_ns is set to the same value of RCAR_PWM_MAX_CYCLE in
rcar_pwm_get_clock_division(), this function should allow such value
for improving accuracy of frequency division setting.

Signed-off-by: Ryo Kodama <ryo.kodama.vz@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2015-12-16 17:02:14 +01:00
Vladimir Zapolskiy
d6dbdf0dde pwm: lpc32xx: return ERANGE, if requested period is not supported 
Instead of silent acceptance of unsupported requested configuration
for PWM period and setting the boundary supported value, return
-ERANGE to a caller.

Duty period value equal to 0 or period is still accepted to allow
configuration by PWM sysfs interface, when it is set to 0 by default.

For reference this is a list of restrictions on period_ns == 1/freq:

  | PWM parent clock | parent clock divisor | max freq | min freq |
  +------------------+----------------------+----------+----------+
  |   HCLK == 13 MHz |      1 (min)         | 50.7 KHz | 198.3 Hz |
  |   HCLK == 13 MHz |     15 (max)         | 3.38 KHz | 13.22 Hz |
  |  RTC == 32.7 KHz |      1 (min)         |   128 Hz |   0.5 Hz |
  |  RTC == 32.7 KHz |     15 (max)         | 8.533 Hz | 0.033 Hz |

Note that PWM sysfs interface does not support setting of period more
than NSEC_PER_SEC / MAX_INT32 ~ 2 seconds, however this PWM controller
supports a period up to 30 seconds.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2015-12-16 17:01:06 +01:00
Vladimir Zapolskiy
5a9fc9c666 pwm: lpc32xx: fix and simplify duty cycle and period calculations 
The change fixes a problem, if duty_ns is too small in comparison
to period_ns (as a valid corner case duty_ns is 0 ns), then due to
PWM_DUTY() macro applied on a value the result is overflowed over 8
bits, and instead of the highest bitfield duty cycle value 0xff the
invalid duty cycle bitfield value 0x00 is written.

For reference the LPC32xx spec defines PWMx_DUTY bitfield description
is this way and it seems to be correct:

 [Low]/[High] = [PWM_DUTY]/[256-PWM_DUTY], where 0 < PWM_DUTY <= 255.

In addition according to my oscilloscope measurements LPC32xx PWM is
"tristate" in sense that it produces a wave with floating min/max
voltage levels for different duty cycle values, for corner cases:

  PWM_DUTY == 0x01 => signal is in range from -1.05v to 0v
  ....
  PWM_DUTY == 0x80 => signal is in range from -0.75v to +0.75v
  ....
  PWM_DUTY == 0xff => signal is in range from 0v to +1.05v

  PWM_DUTY == 0x00 => signal is around 0v, PWM is off

Due to this peculiarity on very long period ranges (less than 1KHz)
and odd pre-divider values PWM generated wave does not remind a
clock shape signal, but rather a heartbit shape signal with positive
and negative peaks, so I would recommend to use high-speed HCLK clock
as a PWM parent clock and avoid using RTC clock as a parent.

The change corrects PWM output in corner cases and prevents any
possible overflows in calculation of values for PWM_DUTY and
PWM_RELOADV bitfields, thus helper macro definitions may be removed.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2015-12-16 17:00:49 +01:00
Vladimir Zapolskiy
82aff048dd pwm: lpc32xx: make device usable with common clock framework 
As a preparatory change for switching LPC32xx mach support to common
clock framework fix clk_enable/clk_disable calls without matching
clk_prepare/clk_unprepare.

The driver can not be used on a platform with common clock framework
until clk_prepare/clk_unprepare calls are added, otherwise clk_enable
calls will fail and a WARN is generated:

    # echo 1 > /sys/bus/platform/drivers/lpc32xx-pwm/4005c000.pwm/pwm/pwmchip0/pwm0/enable
    ------------[ cut here ]------------
    WARNING: CPU: 0 PID: 701 at drivers/clk/clk.c:727 clk_core_enable+0x2c/0xa4()
    Modules linked in: sc16is7xx
    CPU: 0 PID: 701 Comm: sh Tainted: G        W       4.3.0-rc2+ #171
    Hardware name: LPC32XX SoC (Flattened Device Tree)
    Backtrace:
    [<>] (dump_backtrace) from [<>] (show_stack+0x18/0x1c)
    [<>] (show_stack) from [<>] (dump_stack+0x20/0x28)
    [<>] (dump_stack) from [<>] (warn_slowpath_common+0x90/0xb8)
    [<>] (warn_slowpath_common) from [<>] (warn_slowpath_null+0x24/0x2c)
    [<>] (warn_slowpath_null) from [<>] (clk_core_enable+0x2c/0xa4)
    [<>] (clk_core_enable) from [<>] (clk_enable+0x24/0x38)
    [<>] (clk_enable) from [<>] (lpc32xx_pwm_enable+0x1c/0x40)
    [<>] (lpc32xx_pwm_enable) from [<>] (pwm_enable+0x48/0x5c)
    [<>] (pwm_enable) from [<>] (pwm_enable_store+0x5c/0x78)
    [<>] (pwm_enable_store) from [<>] (dev_attr_store+0x20/0x2c)
    [<>] (dev_attr_store) from [<>] (sysfs_kf_write+0x44/0x50)
    [<>] (sysfs_kf_write) from [<>] (kernfs_fop_write+0x134/0x194)
    [<>] (kernfs_fop_write) from [<>] (__vfs_write+0x34/0xdc)
    [<>] (__vfs_write) from [<>] (vfs_write+0xb8/0x140)
    [<>] (vfs_write) from [<>] (SyS_write+0x50/0x90)
    [<>] (SyS_write) from [<>] (ret_fast_syscall+0x0/0x38)

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2015-12-16 17:00:33 +01:00
Vladimir Zapolskiy
ebe1fca350 pwm: lpc32xx: correct number of PWM channels from 2 to 1 
LPC32xx SoC has two independent PWM controllers, they have different
clock parents, clock gates and even slightly different controls, and
each of these two PWM controllers has one output channel. Due to
almost similar controls arranged in a row it is incorrectly set that
there is one PWM controller with two channels, fix this problem, which
at the moment prevents separate configuration of different clock
parents and gates for both PWM controllers.

The change makes previous PWM device node description incompatible
with this update.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2015-12-16 17:00:01 +01:00
Stefan Agner
816aec2325 pwm: fsl-ftm: Fix clock enable/disable when using PM 
A FTM PWM instance enables/disables three clocks: The bus clock, the
counter clock and the PWM clock. The bus clock gets enabled on
pwm_request, whereas the counter and PWM clocks will be enabled upon
pwm_enable.

The driver has three closesly related issues when enabling/disabling
clocks during suspend/resume:
- The three clocks are not treated differently in regards to the
  individual PWM state enabled/requested. This can lead to clocks
  getting disabled which have not been enabled in the first place
  (a PWM channel which only has been requested going through
  suspend/resume).

- When entering suspend, the current behavior relies on the
  FTM_OUTMASK register: If a PWM output is unmasked, the driver
  assumes the clocks are enabled. However, some PWM instances
  have only 2 channels connected (e.g. Vybrid's FTM1). In that case,
  the FTM_OUTMASK reads 0x3 if all channels are disabled, even if
  the code wrote 0xff to it before. For those PWM instances, the
  current approach to detect enabled PWM signals does not work.

- A third issue applies to the bus clock only, which can get enabled
  multiple times (once for each PWM channel of a PWM chip). This is
  fine, however when entering suspend mode, the clock only gets
  disabled once.

This change introduces a different approach by relying on the enable
and prepared counters of the clock framework and using the frameworks
PWM signal states to address all three issues.

Clocks get disabled during suspend and back enabled on resume
regarding to the PWM channels individual state (requested/enabled).

Since we do not count the clock enables in the driver, this change no
longer clears the Status and Control registers Clock Source Selection
(FTM_SC[CLKS]). However, since we disable the selected clock anyway,
and we explicitly select the clock source on reenabling a PWM channel
this approach should not make a difference in practice.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2015-12-16 16:54:32 +01:00
Mika Westerberg
37670676a1 pwm: lpss: Rework the sequence of programming PWM_SW_UPDATE 
Setting of PWM_SW_UPDATE is bit different in Intel Broxton compared to the
previous generation SoCs. Previously it was OK to set the bit many times
(from userspace via sysfs for example) before the PWM is actually enabled.

Starting from Intel Broxton it seems that we must set PWM_SW_UPDATE only
once before the PWM is enabled. Otherwise it is possible that the PWM does
not start properly.

Change the sequence of how PWM_SW_UPDATE is programmed so that we only set
it in pwm_lpss_config() when the PWM is already enabled. The initial
setting of PWM_SW_UPDATE will be done when PWM gets enabled. This should
make the driver work with the previous generation Intel SoCs and Broxton.

Add also small delay after the bit is set to let the hardware propagate it
properly.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2015-12-16 16:52:09 +01:00
Andy Shevchenko
6f90a00c66 pwm: lpss: Select core part automatically 
We have two users of core part right now. Let them to select core part
automatically.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2015-12-16 16:50:31 +01:00
qipeng.zha
883e4d070f pwm: lpss: Update PWM setting for Broxton 
For Broxton PWM controller, base unit is defined as 8-bit integer
and 14-bit fraction, so need to update base unit setting to output
wave with right frequency.

Signed-off-by: Qipeng Zha <qipeng.zha@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2015-12-16 16:45:38 +01:00
Stefan Wahren
6ef7d1c46f pwm: bcm2835: Fix email address specification 
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2015-12-16 16:45:32 +01:00
Stefan Wahren
fd13c14426 pwm: bcm2835: Prevent division by zero 
It's possible that the PWM clock becomes an orphan. So better check the
result of clk_get_rate() in order to prevent a division by zero.

Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2015-12-16 16:45:10 +01:00
Stefan Wahren
ebe88b6ae4 pwm: bcm2835: Calculate scaler in ->config() 
Currently pwm-bcm2835 assumes a fixed clock rate and stores the
resulting scaler in the driver structure. But with the upcoming
PWM clock support for clk-bcm2835 the rate could change, so
calculate the scaler in the ->config() callback.

Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
 2015-12-16 16:44:36 +01:00