-----BEGIN PGP SIGNATURE-----
iQEcBAABAgAGBQJYoM2fAAoJEHm+PkMAQRiGr9MH/izEAMri7rJ0QMc3ejt+WmD0
8pkZw3+MVn71z6cIEgpzk4QkEWJd5rfhkETCeCp7qQ9V6cDW1FDE9+0OmPjiphDt
nnzKs7t7skEBwH5Mq5xygmIfkv+Z0QGHZ20gfQWY3F56Uxo+ARF88OBHBLKhqx3v
98C7YbMFLKBslKClA78NUEIdx0UfBaRqerlERx0Lfl9aoOrbBS6WI3iuREiylpih
9o7HTrwaGKkU4Kd6NdgJP2EyWPsd1LGalxBBjeDSpm5uokX6ALTdNXDZqcQscHjE
RmTqJTGRdhSThXOpNnvUJvk9L442yuNRrVme/IqLpxMdHPyjaXR3FGSIDb2SfjY=
=VMy8
-----END PGP SIGNATURE-----
Merge tag 'v4.10-rc8' into drm-next
Linux 4.10-rc8
Backmerge Linus rc8 to fix some conflicts, but also
to avoid pulling it in via a fixes pull from someone.
Add driver to support the Multi-Inno MI0283QT display panel.
It has an ILI9341 MIPI DBI compatible display controller.
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Display panels can be oriented many ways, especially in the embedded
world. The rotation property is a way to describe this orientation.
The counter clockwise direction is chosen because that's what fbdev
and drm use.
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Multi-Inno Technology Co.,Ltd is a Hong Kong based company offering
LCD, LCD module products and complete panel solutions.
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
Acked-by: Rob Herring <robh@kernel.org>
Add support for MIPI DBI compatible controllers.
Interface type C option 1 and 3 are supported (SPI).
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Add common functionality needed by many tinydrm drivers.
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Thierry Reding <treding@nvidia.com>
tinydrm provides helpers for very simple displays that can use
CMA backed framebuffers and need flushing on changes.
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Thierry Reding <treding@nvidia.com>
i915 and GVT fixes for v4.11 merge window
* tag 'drm-intel-next-fixes-2017-02-17' of git://anongit.freedesktop.org/git/drm-intel: (32 commits)
drm/i915: Fix not finding the VBT when it overlaps with OPREGION_ASLE_EXT
drm/i915: Pass timeout==0 on to i915_gem_object_wait_fence()
drm/i915/gvt: Disable access to stolen memory as a guest
drm/i915: Avoid spurious WARNs about the wrong pipe in the PPS code
drm/i915: Check for timeout completion when waiting for the rq to submitted
drm/i915: A hotfix for making aliasing PPGTT work for GVT-g
drm/i915: Restore context and pd for ringbuffer submission after reset
drm/i915: Let execlist_update_context() cover !FULL_PPGTT mode.
drm/i915/lspcon: Fix resume time initialization due to unasserted HPD
drm/i915/gen9+: Enable hotplug detection early
drm/i915: Reject set-tiling-ioctl with stride==0 and a tiling mode
drm/i915: Recreate internal objects with single page segments if dmar fails
drm/i915/gvt: return error code if dma map iova failed
drm/i915/gvt: optimize the inhibit context mmio load
drm/i915/gvt: add sprite plane flip done support.
drm/i915/gvt: add missing display part reset for vGPU reset
drm/i915/gvt: Fix shadow context descriptor
drm/i915/gvt: Fix alignment for GTT allocation
drm/i915/gvt: fix crash at function release_shadow_wa_ctx
drm/i915/gvt: enable IOMMU for gvt
...
- Rework of the secure boot code, in preparation for GP10x secure boot.
- Improvements to channel recovery
- Initial power budget code
- Some preparation for an upcoming MMU rework (probably 4.12)
- Misc other fixes.
* 'linux-4.11' of git://github.com/skeggsb/linux: (88 commits)
drm/nouveau/tmr: provide backtrace when a timeout is hit
drm/nouveau/pci/g92: Fix rearm
drm/nouveau/drm/therm/fan: add a fallback if no fan control is specified in the vbios
drm/nouveau/hwmon: expose power_max and power_crit
drm/nouveau/iccsense: Parse max and crit power level
drm/nouveau/bios/power_budget: Add basic power budget parsing
drm/nouveau/fifo/gk104-: preempt recovery
drm/nouveau/fifo/gk104-: trigger mmu fault before attempting engine recovery
drm/nouveau/fifo/gk104-: ACK SCHED_ERROR before attempting CTXSW_TIMEOUT recovery
drm/nouveau/fifo/gk104-: directly use new recovery code for ctxsw timeout
drm/nouveau/fifo/gk104-: directly use new recovery code for mmu faults
drm/nouveau/fifo/gk104-: reset all engines a killed channel is still active on
drm/nouveau/fifo/gk104-: refactor recovery code
drm/nouveau/fifo/gk104-: better detection of chid when parsing engine status
drm/nouveau/fifo/gk104-: separate out engine status parsing
drm/nouveau/fifo: add an api for initiating channel recovery
drm/nouveau/top: add function to translate subdev index to mmu fault id
drm/nouveau/gr/gf100-: implement chsw_load() method
drm/nouveau/gr: implement chsw_load() method
drm/nouveau/core: add engine method to assist in determining chsw direction
...
704a6c008b7942bb7f30bb43d2a6bcad7f543662 broke pci msi rearm for g92 GPUs.
g92 needs the nv46_pci_msi_rearm, where g94+ gpus used nv40_pci_msi_rearm.
Reported-by: Andrew Randrianasulu <randrianasulu@gmail.com>
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
This seems to be absolutely necessary for a lot of NV40.
Reported-by: gsgf on IRC/freenode
Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
v2: Set entry to 0xff if not found
Add cap entry for ver 0x30 tables
Rework to fix memory leak
v3: More error checks
Simplify check for invalid entries
v4: disable for ver 0x10 for now
move assignments after the second last return
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Greatly improves the chances of recovering the GPU from a CTXSW_TIMEOUT.
Tested with piglit's arb_shader_image_load_store-atomicity, which causes
GR to hang in such a way that recovery failed (CTXSW_TIMEOUT continually
re-triggers).
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This will serve as a basis for implementing some improvements to how
we recover the GPU from channel errors.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
The previous commit simply changes the interface, but should result in
the same behaviour as previously. This commit has been split out from
it as it can result in a different channel being selected.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
FIFO gives us load/save/switch status, and we need to be able to determine
which direction a "switch" is failing during channel recovery.
In order to do this, we apparently need to query the engine itself.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
There are instances (such as non-recoverable GPU page faults) where
NVKM decides that a channel's context is no longer viable, and will
be removed from the runlist.
This commit notifies the owner of the channel when this happens, so
it has the opportunity to take some kind of recovery action instead
of hanging.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
If the led class registration fails, we free drm->led but do not reset
it to NULL, which means that the suspend/resume/fini function will act
as if everything went well in init() and will likely crash the kernel.
This patch adds the missing drm->led = NULL.
Reported-by: Emmanuel Pescosta <emmanuelpescosta099@gmail.com>
Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Tested on a G92, seems to work. Confirmed by 8 mmiotraces.
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This will allow the DRM to share memory objects between clients later
down the track.
For the moment, the only immediate benefit is less logic required to
handle suspend/resume.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
