Commit Graph

104702 Commits

Author SHA1 Message Date
Markos Chandras
938c12824b MIPS: kernel: genex: Set correct ISA level
The jr instruction opcode has changed in R6 so make sure
the correct ISA level is set prior using that instruction.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:28 +00:00
Leonid Yegoshin
8d5b9b771e MIPS: kernel: r4k_fpu: Add support for MIPS R6
Add the MIPS R6 related preprocessor definitions for FPU signal
related functions. MIPS R6 only has FR=1 so avoid checking that
bit on the C0/Status register.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:27 +00:00
Leonid Yegoshin
207083b1da MIPS: kernel: r4k_switch: Add support for MIPS R6
Add the MIPS R6 related preprocessor definitions for save/restore
FPU related functions. We also set the appropriate ISA level
so the final return instruction "jr ra" will produce the correct
opcode on R6.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:27 +00:00
Leonid Yegoshin
9c7d576868 MIPS: kernel: traps: Add MIPS R6 related definitions
Add MIPS R6 support to cache and ftlb exceptions, as well as
to the hwrena and ebase register configuration.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:27 +00:00
Markos Chandras
515a6393db MIPS: kernel: proc: Add MIPS R6 support to /proc/cpuinfo
Print 'mips64r6' and/or 'mips32r6' if the kernel is running on
a MIPS R6 core.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:26 +00:00
Markos Chandras
6ebb496ffc MIPS: kernel: entry.S: Add MIPS R6 related definitions
The instruction hazard barrier in the form of:

jr.hb	ra
nop

is valid on MIPS R6 as well.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:26 +00:00
Leonid Yegoshin
8b8aa636f0 MIPS: kernel: cpu-probe.c: Add support for MIPS R6
Add MIPS R6 support when decoding the config0 c0 register.
Also add MIPS R6 support when examining the ebase c0 register
to get the core number and when getting the shadow set number
from the srsctl c0 register.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:25 +00:00
Leonid Yegoshin
54dac95083 MIPS: kernel: cevt-r4k: Add MIPS R6 to the c0_compare_interrupt handler
Just like MIPS R2, in MIPS R6 it is possible to determine if a
timer interrupt has happened or not.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:25 +00:00
Leonid Yegoshin
180b1e3bfe MIPS: kernel: cpu-bugs64: Do not check R6 cores for existing 64-bit bugs
The current HW bugs checked in cpu-bugs64, do not apply to R6 cores
and they cause compilation problems due to removed <R6 instructions,
so do not check for them for the time being.

Reviewed-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:24 +00:00
Markos Chandras
82e7ce8149 MIPS: asm: local: Set the appropriate ISA level for MIPS R6
MIPS R6 changed the opcodes for LL/SC instructions so we need to set
the appropriate ISA level.

Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:24 +00:00
Markos Chandras
5753762cbd MIPS: asm: spinlock: Replace "sub" instruction with "addiu"
"sub $reg, imm" is not a real MIPS instruction. The assembler can
replace that with "addi $reg, -imm". However, addi has been removed
from R6, so we replace the "sub" instruction with the "addiu" one.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:23 +00:00
Markos Chandras
1922c356ab MIPS: asm: futex: Set the appropriate ISA level for MIPS R6
MIPS R6 changed the opcodes for LL/SC instructions so we need to set
the appropriate ISA level.

Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:23 +00:00
Markos Chandras
87a927eff4 MIPS: asm: bitops: Update ISA constraints for MIPS R6 support
MIPS R6 changed the opcodes for LL/SC instructions so we need to set
the correct ISA level.

Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:22 +00:00
Markos Chandras
0038df2240 MIPS: asm: atomic: Update ISA constraints for MIPS R6 support
MIPS R6 changed the opcodes for LL/SC instructions so we need to
set the correct ISA level.

Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:22 +00:00
Markos Chandras
fa998ebbc0 MIPS: asm: cmpxchg: Update ISA constraints for MIPS R6 support
MIPS R6 changed the opcodes for LL/SC instructions so we need to set
the correct ISA.

Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:22 +00:00
Markos Chandras
123e4b3bbc MIPS: Use the new "ZC" constraint for MIPS R6
GCC versions supporting MIPS R6 use the ZC constraint to enforce a
9-bit offset for MIPS R6. We will use that for all MIPS R6 LL/SC
instructions.

Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:21 +00:00
Markos Chandras
94bfb75ace MIPS: asm: Rename GCC_OFF12_ASM to GCC_OFF_SMALL_ASM
The GCC_OFF12_ASM macro is used for 12-bit immediate constrains
but we will also use it for 9-bit constrains on MIPS R6 so we
rename it to something more appropriate.

Cc: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:21 +00:00
Markos Chandras
a7e07b1ae5 MIPS: asm: spram: Add new symbol for MIPS scratch pad storage
MIPS R6, just like MIPS R2, have scratch pad storage, so add a new
symbol which is selected by MIPS R2 and R6.

Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00389.html
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:20 +00:00
Markos Chandras
934c79231c MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions
MIPS R6 changed the 'cache' instruction opcode and reduced the
offset field to 8 bits. This means we now have to adjust the
base register every 256 bytes and as a result of which we can
no longer use the previous cache functions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:20 +00:00
Markos Chandras
8716a76356 MIPS: asm: irqflags: Add MIPS R6 related definitions
Add the MIPS R6 related definitions to the IRQ related macros

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:20 +00:00
Markos Chandras
f52fca9713 MIPS: asm: hazards: Add MIPSR6 definitions
Add the MIPSR6 related definitions to MIPS hazards

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:19 +00:00
Leonid Yegoshin
34c56fc1c1 MIPS: asm: cpu: Add MIPSR6 ISA definitions
Add MIPS R6 to the ISA definitions

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:19 +00:00
Markos Chandras
4e0748f5be MIPS: Use generic checksum functions for MIPS R6
The following instructions have been removed from MIPS R6

ulw, ulh, swl, lwr, lwl, swr.

However, all of them are used in the MIPS specific checksum implementation.
As a result of which, we will use the generic checksum on MIPS R6

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:19 +00:00
Markos Chandras
98a833c1fa MIPS: asm: asmmacro: Replace "add" instructions with "addu"
The "add" instruction is actually a macro in binutils and depending on
the size of the immediate it can expand to an "addi" instruction.
However, the "addi" instruction traps on overflows which is not
something we want on address calculation.

Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00121.html
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: <stable@vger.kernel.org> # v3.15+
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:18 +00:00
Leonid Yegoshin
226da55f48 MIPS: asm: asmmacro: Add MIPS R6 support to the simple EI/DI variants
EI/DI instructions are available in MIPS R6 so add the needed
definitions.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:18 +00:00
Leonid Yegoshin
6a0e9865b9 MIPS: asm: stackframe: Do not preserve the HI/LO registers on MIPS R6
The HI/LO registers have been removed from MIPS R6. Instructions
such as MULT and DIV have been replaced with a new pair of
instructions for the HI/LO operations for example:

MULT -> MUL, MUH
DIV -> DIV, MOD

So we avoid preserving the pre-R6 HI/LO registers in MIPS R6

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:17 +00:00
Leonid Yegoshin
b840a82c54 MIPS: asm: module: define MODULE_PROC_FAMILY for MIPS R6
Define the MODULE_PROC_FAMILY for the MIPS R6 ISA.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:17 +00:00
Markos Chandras
be5136988e MIPS: asm: compiler: Add new macros to set ISA and arch asm annotations
There are certain places where the code uses .set mips32 or .set mips64
or .set arch=r4000. In preparation of MIPS R6 support, and in order to
use as less #ifdefs as possible, we define new macros to set similar
annotations for MIPS R6.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:14 +00:00
Leonid Yegoshin
a168b8f1cd MIPS: mm: Add MIPS R6 instruction encodings
MIPS R6 defines new opcodes for ll, sc, cache and pref instructions
so we need to take these into consideration in the micro-assembler.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-16 14:02:50 +00:00
Leonid Yegoshin
51eec48e12 MIPS: mm: uasm: Add signed 9-bit immediate related macros
MIPS R6 redefines several instructions and reduces the immediate
field to 9-bits so add related macros for the microassembler.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-16 10:01:25 +00:00
Leonid Yegoshin
7fd08ca58a MIPS: Add build support for the MIPS R6 ISA
Add build support for the latest revision (R6) of the MIPS ISA.
microMIPS is not yet supported.

Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00386.html
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-16 10:01:25 +00:00
Leonid Yegoshin
b2498af56a MIPS: Add MIPS generic QEMU probe support
Add a case in cpu_probe_mips for the MIPS generic QEMU processor ID.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-16 10:01:24 +00:00
Leonid Yegoshin
4695089f03 MIPS: Add cases for CPU_QEMU_GENERIC
Add a CPU_QEMU_GENERIC case to various switch statements.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-16 10:01:24 +00:00
Leonid Yegoshin
aca5721e95 MIPS: Add generic QEMU PRid and cpu type identifiers
Latest versions of QEMU added support for mips32r6-generic and
mips64r6-generic cpu types so add related definitions in preparation
of MIPS R6 support. This is also used for QEMU R2 generic cpus.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-16 10:01:24 +00:00
Markos Chandras
b3e76c44a5 MIPS: Makefile: Move the ASEs checks after setting the core's CFLAGS
We need to check the ASEs support against the core's CFLAGS instead
of depending to the default -march option from the toolchain.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9180/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-02-16 10:55:26 +01:00
Markos Chandras
ed4cbc81ad MIPS: HTW: Prevent accidental HTW start due to nested htw_{start, stop}
activate_mm() and switch_mm() call get_new_mmu_context() which in turn
can enable the HTW before the entryhi is changed with the new ASID.
Since the latter will enable the HTW in local_flush_tlb_all(),
then there is a small timing window where the HTW is running with the
new ASID but with an old pgd since the TLBMISS_HANDLER_SETUP_PGD
hasn't assigned a new one yet. In order to prevent that, we introduce a
simple htw counter to avoid starting HTW accidentally due to nested
htw_{start,stop}() sequences. Moreover, since various IPI calls can
enforce TLB flushing operations on a different core, such an operation
may interrupt another htw_{stop,start} in progress leading inconsistent
updates of the htw_seq variable. In order to avoid that, we disable the
interrupts whenever we update that variable.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # 3.17+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9118/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-02-16 10:55:26 +01:00
Markos Chandras
fde3538a8a MIPS: asm: pgtable: Prevent HTW race when updating PTEs
Whenever we modify a page table entry, we need to ensure that the HTW
will not fetch a stable entry. And for that to happen we need to ensure
that HTW is stopped before we modify the said entry otherwise the HTW
may already be in the process of reading that entry and fetching the
old information. As a result of which, we replace the htw_reset() calls
with htw_{stop,start} in more appropriate places. This also removes the
remaining users of htw_reset() and as a result we drop that macro

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # 3.17+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9116/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-02-16 10:55:26 +01:00
Markos Chandras
461d1597ff MIPS: asm: pgtable: Add c0 hazards on HTW start/stop sequences
When we use htw_{start,stop}() outside of htw_reset(), we need
to ensure that c0 changes have been propagated properly before
we attempt to continue with subsequence memory operations.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # 3.17+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9114/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-02-16 10:55:26 +01:00
Markos Chandras
d79d853df1 MIPS: mm: Add debug information for userland SIGSEGV signals.
Commit 41c594ab65 ("[MIPS] MT: Improved multithreading support.")
removed useful debug information for userland segmentation faults.
This patch bring this back along with the ability to determine the
name of the object file where the EPC and RA registers point at.
Furthermore, we select the SYSCTL_EXCEPTION_TRACE symbol for MIPS
which is the de facto solution to turn userland exception logging
on and off via the /proc/sys/debug/exception-trace file.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9089/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-02-16 10:55:26 +01:00
Paul Burton
9791554b45 MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS
Userland code may be built using an ABI which permits linking to objects
that have more restrictive floating point requirements. For example,
userland code may be built to target the O32 FPXX ABI. Such code may be
linked with other FPXX code, or code built for either one of the more
restrictive FP32 or FP64. When linking with more restrictive code, the
overall requirement of the process becomes that of the more restrictive
code. The kernel has no way to know in advance which mode the process
will need to be executed in, and indeed it may need to change during
execution. The dynamic loader is the only code which will know the
overall required mode, and so it needs to have a means to instruct the
kernel to switch the FP mode of the process.

This patch introduces 2 new options to the prctl syscall which provide
such a capability. The FP mode of the process is represented as a
simple bitmask combining a number of mode bits mirroring those present
in the hardware. Userland can either retrieve the current FP mode of
the process:

  mode = prctl(PR_GET_FP_MODE);

or modify the current FP mode of the process:

  err = prctl(PR_SET_FP_MODE, new_mode);

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Matthew Fortune <matthew.fortune@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8899/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-02-12 12:30:29 +01:00
James Hogan
ae58d882bf MIPS: cevt-r4k: Drop GIC special case
The cevt-r4k driver used to call into the GIC driver to find whether the
timer was pending, but only with External Interrupt Controller (EIC)
mode, where the Cause.IP bits can't be used as they encode the interrupt
priority level (Cause.RIPL) instead.

However commit e9de688dac ("irqchip: mips-gic: Support local
interrupts") changed the condition from cpu_has_veic to gic_present.
This fails on cores such as P5600 which have a GIC but the local
interrupts aren't routable by the GIC, causing c0_compare_int_usable()
to consider the interrupt unusable so r4k_clockevent_init() fails.

The previous behaviour, added in commit 98b67c37db ("MIPS: Add EIC
support for GIC."), wasn't really correct either as far as I can tell,
since P5600 apparently supports EIC mode too, and in any case the use of
Cause.TI with r2 should have been sufficient anyway since commit
010c108d7a ("MIPS: PowerTV: Fix support for timer interrupts with > 64
external IRQs").

Therefore drop the call into the gic driver altogether, and add a
comment in c0_compare_int_pending() to clarify that Cause.TI does get
checked since MIPS r2.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Fixes: e9de688dac ("irqchip: mips-gic: Support local interrupts")
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Steven J. Hill <steven.hill@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9077/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-02-05 14:56:53 +01:00
Ralf Baechle
2d76e9633b MIPS: elf2ecoff: Fix warning due to dead code.
HOSTCC  arch/mips/boot/elf2ecoff
arch/mips/boot/elf2ecoff.c: In function ‘main’:
arch/mips/boot/elf2ecoff.c:271:8: warning: variable ‘shstrtab’ set but not used [-Wunused-but-set-variable]
  char *shstrtab;

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-02-04 14:42:27 +01:00
Rob Herring
7b09777c18 MIPS: Add struct pci_ops member names to initialization
Some instances of pci_ops initialization rely on the read/write members'
location in the struct. This is fragile and may break when adding new
members to the beginning of the struct.

[ralf@linux-mips.org: indent = with tabs for consistency.]

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: linux-pci@vger.kernel.org
Cc: Bjorn Helgaas <bhelgaas@google.com>
Patchwork: https://patchwork.linux-mips.org/patch/8915/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-16 15:04:38 +01:00
Geert Uytterhoeven
250215ccf6 MIPS: Remove unused dt_setup_arch()
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8928/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-16 13:10:42 +01:00
Ralf Baechle
e9503246a2 MIPS: ARC: Add declarations for a few missing ARC firmware functions.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-13 16:04:28 +01:00
Ralf Baechle
bb03006ec9 MIPS: ARC: Use __noreturn instead of open coded attributes in declarations.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-13 16:04:28 +01:00
Ralf Baechle
dd6e2db13f MIPS: IP27: Use __noreturn instead of open coded attributes in declarations.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-13 16:04:28 +01:00
Ralf Baechle
efc46d136f MIPS: IP32: Use __noreturn instead of open coded attributes in declarations.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-13 16:04:28 +01:00
Ralf Baechle
7f84c0a24a MIPS: ARC: Use __noreturn / unreachable in ARC termination functions.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-13 16:04:27 +01:00
Ralf Baechle
2f26c48824 MIPS: Use generic csum_tcpudp_magic for MIPS.
Its implementation is identical to MIPS.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-13 16:04:27 +01:00