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MIPS: Add cases for CPU_QEMU_GENERIC
Add a CPU_QEMU_GENERIC case to various switch statements. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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@ -54,6 +54,13 @@ static inline int __pure __get_cpu_type(const int cpu_type)
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case CPU_M5150:
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#endif
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#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R2) || \
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defined(CONFIG_SYS_HAS_CPU_MIPS32_R6) || \
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defined(CONFIG_SYS_HAS_CPU_MIPS64_R2) || \
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defined(CONFIG_SYS_HAS_CPU_MIPS64_R6)
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case CPU_QEMU_GENERIC:
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#endif
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#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
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case CPU_5KC:
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case CPU_5KE:
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@ -186,6 +186,7 @@ void __init check_wait(void)
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case CPU_PROAPTIV:
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case CPU_P5600:
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case CPU_M5150:
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case CPU_QEMU_GENERIC:
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cpu_wait = r4k_wait;
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if (read_c0_config7() & MIPS_CONF7_WII)
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cpu_wait = r4k_wait_irqoff;
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@ -208,6 +208,7 @@ void spram_config(void)
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case CPU_INTERAPTIV:
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case CPU_PROAPTIV:
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case CPU_P5600:
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case CPU_QEMU_GENERIC:
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config0 = read_c0_config();
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/* FIXME: addresses are Malta specific */
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if (config0 & (1<<24)) {
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@ -1559,6 +1559,7 @@ static inline void parity_protection_init(void)
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case CPU_INTERAPTIV:
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case CPU_PROAPTIV:
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case CPU_P5600:
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case CPU_QEMU_GENERIC:
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{
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#define ERRCTL_PE 0x80000000
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#define ERRCTL_L2P 0x00800000
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@ -1255,6 +1255,7 @@ static void probe_pcache(void)
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case CPU_P5600:
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case CPU_PROAPTIV:
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case CPU_M5150:
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case CPU_QEMU_GENERIC:
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if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
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(c->icache.waysize > PAGE_SIZE))
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c->icache.flags |= MIPS_CACHE_ALIASES;
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@ -81,6 +81,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
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case CPU_PROAPTIV:
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case CPU_P5600:
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case CPU_BMIPS5000:
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case CPU_QEMU_GENERIC:
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if (config2 & (1 << 12))
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return 0;
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}
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@ -514,6 +514,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
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case CPU_PROAPTIV:
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case CPU_P5600:
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case CPU_M5150:
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case CPU_QEMU_GENERIC:
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break;
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default:
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