We have no in tree or out of tree users of this function, remove it and
the header providing its prototype.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
PMB originally comes from BCM63138 but can be also found on many other
chipsets (e.g. BCM4908). It's needed to power on and off SoC blocks like
PCIe, SATA, USB.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
brcmstb_pm_s3_finish() cannot be made static because it is referenced
from brcmstb_pm_s3(), so let's provide a prototype for it instead.
Fixes the following W=1 kernel build warning(s):
drivers/soc/bcm/brcmstb/pm/pm-arm.c:395:14: warning: no previous prototype for ‘brcmstb_pm_s3_finish’ [-Wmissing-prototypes]
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Change the RACPREFDATA(x) setting to prefetch the next 256-byte line
after 4 consecutive lines have been used, instead of after 2 consecutive
lines. This does improve the synthetic memcpy benchmark by an additional
+0.5% on top of the previous change for Cortex-A72 CPUs.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Change the RAC prefetch distance from +/- 1 to +/- 2 for Cortex-A72 CPUs
since this provides an average of a 3.8% performance increase for
synthetic memcpy benchmarks.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
72165 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it
according to the existing values we have.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
72164 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it
according to the existing values we have.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
BCM6318, BCM6328, BCM6362 and BCM63268 SoCs have a power domain controller
to enable/disable certain components in order to save power.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Florian Fainelli <F.fainelli@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Brahma-B53 and Cortex-A72 CPUs integrated on Broadcom STB SoCs feature a
read-ahead cache that performs cache line size adaptation between the
bus interface unit and the memory controller.
On 32-bit ARM kernels we have to resort to a full featured read-ahead
cache driver under arch/arm/mm/cache-b15-rac.c (CONFIG_CACHE_B15_RAC)
because there are still cache maintenance operations by set/ways/index
that cannot be transparently handled by the ARM Coherency Extension that
the read-ahead cache interfaces to.
The 64-bit ARM kernel however has long deprecated all of those, so this
is simply a one time configuration.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add a matching entry for 7211 which can be programmed with the same
BIUCTRL settings as other Brahma-B53 based SoCs. While at it, rename the
function to include a72 in the name to reflect this applies to both
types of 64-bit capable CPUs that we support (Brahma-B53 and
Cortex-A72).
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The BIUCTRL layout is a little different on 7211 which is equipped with
a Cortex-A72, account for those register offset differences. We will
match 7211 specifically in a subsequent commit.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
7255 and 7216 are some of the latest chips that were produced and
support the full register range configuration for the BIU, add the two
entries to get the expected programming.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
7260A0 and B0 are both supported, and 7260A0 has a small difference in
that it does not support the write-back control register, which is why
we have a different array of registers. Update the comment above
b53_cpubiuctrl_no_wb_regs to denote that difference.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
fixes for 5.2-rc1, please pull the following:
- Florian fixes the biuctrl driver not to create an error condition/path
upon unsupported CPU and also fixes the biuctrl driver writes to used
a data barrier which is necessary given the HW block design
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Merge tag 'arm-soc/for-5.2/drivers-fixes' of https://github.com/Broadcom/stblinux into fixes
This pull request contains Broadcom ARM/ARM64/MIPS SoCs device drivers
fixes for 5.2-rc1, please pull the following:
- Florian fixes the biuctrl driver not to create an error condition/path
upon unsupported CPU and also fixes the biuctrl driver writes to used
a data barrier which is necessary given the HW block design
* tag 'arm-soc/for-5.2/drivers-fixes' of https://github.com/Broadcom/stblinux:
soc: bcm: brcmstb: biuctrl: Register writes require a barrier
soc: brcmstb: Fix error path for unsupported CPUs
Signed-off-by: Olof Johansson <olof@lixom.net>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation this program is
distributed in the hope that it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 655 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add SPDX license identifiers to all Make/Kconfig files which:
- Have no license information of any form
These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:
GPL-2.0-only
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The BIUCTRL register writes require that a data barrier be inserted
after comitting the write to the register for the block to latch in the
recently written values. Reads have no such requirement and are not
changed.
Fixes: 34642650e5 ("soc: Move brcmstb to bcm/brcmstb")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
In case setup_hifcpubiuctrl_regs() returns an error, because of e.g:
an unsupported CPU type, just catch that error and return instead of
blindly continuing with the initialization. This fixes a NULL pointer
de-reference with the code continuing without having a proper array of
registers to use.
Fixes: 22f7a9116e ("soc: brcmstb: Correct CPU_CREDIT_REG offset for Brahma-B53 CPUs")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
enabled, and fixes the driver in the presence of -EPROBE_DEFER.
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Merge tag 'tags/bcm2835-drivers-next-2019-03-12' into soc/fixes
This pull request brings in a build fix for arm64 with bcm2835
enabled, and fixes the driver in the presence of -EPROBE_DEFER.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The clock driver may probe after ours and so we need to pass the
-EPROBE_DEFER out. Fix the other error path while we're here.
v2: Use dom->name instead of dom->gov as the flag for initialized
domains, since we aren't setting up a governor. Make sure to
clear ->clk when no clk is present in the DT.
Signed-off-by: Eric Anholt <eric@anholt.net>
Fixes: 670c672608 ("soc: bcm: bcm2835-pm: Add support for power domains under a new binding.")
We don't have ASB master/slave regs for this domain, so just skip that
step.
Signed-off-by: Eric Anholt <eric@anholt.net>
Fixes: 670c672608 ("soc: bcm: bcm2835-pm: Add support for power domains under a new binding.")
Fixes the following sparse warning:
drivers/soc/bcm/bcm2835-power.c:556:32: warning:
symbol 'bcm2835_reset_ops' was not declared. Should it be static?
Fixes: 670c672608 ("soc: bcm: bcm2835-pm: Add support for power domains under a new binding.")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Since commit 52a4adbaebcc ("ARM: bcm283x: Switch V3D over to using the
PM driver instead of firmware.") VC4 on BCM2835 requires the power driver.
Otherwise the driver won't probe and HDMI output stays black:
vc4_v3d 20c00000.v3d: ignoring dependency for device, assuming no driver
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
This provides a free software alternative to raspberrypi-power.c's
firmware calls to manage power domains. It also exposes a reset line,
where previously the vc4 driver had to try to force power off the
domain in order to trigger a reset.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
of_find_node_by_path() acquires a reference to the node returned by it
and that reference needs to be dropped by its caller. soc_is_brcmstb()
doesn't do that, so fix it.
[treding: slightly rewrite to avoid inline comparison]
Fixes: d52fad2620 ("soc: add stubs for brcmstb SoC's")
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
the firmware driver (silently hanging if the VPU doesn't respond to a
mailbox transaction, and undersized buffers in the firmware property
transactions for tags that aren't used yet in the upstream).
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Merge tag 'tags/bcm2835-drivers-next-2018-11-27' into drivers/next
This pull request adds SPDX to BCM2835 drivers, and fixes some bugs in
the firmware driver (silently hanging if the VPU doesn't respond to a
mailbox transaction, and undersized buffers in the firmware property
transactions for tags that aren't used yet in the upstream).
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Adopt the SPDX license identifier headers to ease license compliance
management.
Cc: Alexander Aring <aring@mojatatu.com>
Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
When the kernel is built with CONFIG_THUMB2_KERNEL we would set the
kernel's resume entry point to be a function that is already built as
Thumb-2 code while the boot agent doing the resume is in ARM mode, so
this does not work. There is a header label defined: cpu_resume_arm
which we can use to do the switching for us.
Fixes: 0b741b8234 ("soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
We would not be matching the following chip/compatible strings
combinations, which would lead to not setting the warm boot flag
correctly, fix that:
7260A0/B0: brcm,brcmstb-memc-ddr-rev-b.2.1
7255A0: brcm,brcmstb-memc-ddr-rev-b.2.3
7278Bx: brcm,brcmstb-memc-ddr-rev-b.3.1
The B2.1 core (which is in 7260 A0 and B0) doesn't have the
SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL setup in the memsys init code, nor
does it have the warm boot flag re-definition on entry. Those changes
were for B2.2 and later MEMSYS cores. Fall back to the previous S2/S3
entry method for these specific chips.
Fixes: 0b741b8234 ("soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)")
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Update the Device Tree binding document and add a matching entry for the
MEMC DDR controller revision B3.0 which is found on chips like 7278A0
and newer.
Signed-off-by: Doug Berger <opendmb@gmail.com>
[florian: tweak commit message, make it apply to upstream kernel]
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Commit a09cd35658 ("ARM: bcm2835: add rpi power domain driver")
attempted to annotate the structure rpi_power_domain_packet with
__packed but introduced a typo and made it named __packet instead. Just
drop the annotation since the structure is naturally aligned already.
Fixes: a09cd35658 ("ARM: bcm2835: add rpi power domain driver")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
We were making a bunch of wrong assumptions that turned out to blow out
on non-Broadcom STB platforms:
- we would return -ENODEV from brcmstb_soc_device_early_init() if we
could not find the sun_top_ctrl device node, this is not an error
in the context of a multi-platform kernel
- we would still try to register the Broadcom STB SoC device, even if we
are not running on such a platform
While at it, also fix the sun_top_ctrl device_node leaks while we change
the flow of brcmstb_soc_device_init() and
brcmstb_soc_device_early_init().
Fixes: f780429adf ("soc: brcmstb: biuctrl: Move to early_initcall")
Signed-off-by: Thierry Reding <treding@nvidia.com>
[florian: Combine all of Thierry's patch in one go for easier review]
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Currently if this driver is included, we get the following warning
on any platforms irrespective of whether it's brcmstb platform or not.
"
brcmstb: biuctrl: missing BIU control node
brcmstb: biuctrl: MCP: Unable to disable write pairing!
"
This patch allows to exit early without any warning messages on non
brcmstb platforms as it's meaningless for them.
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Gregory Fong <gregory.0xf0@gmail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Fixes: f780429adf ("soc: brcmstb: biuctrl: Move to early_initcall")
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
[florian: Add fixes tag, make initcall non fatal]
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This reverts commit 23a0d84799.
Patch has issues that's being addressed by the Florian and he will
follow up with a new patch to address the original issue.
Signed-off-by: Olof Johansson <olof@lixom.net>
After moving the SoC device initialization to an early initcall in
commit f780429adf ("soc: brcmstb: biuctrl: Move to early_initcall"),
the Broadcom STB SoC device is registered on all platforms if support
for the device is enabled in the kernel configuration.
This causes an additional SoC device to appear on platforms that already
register a native one. In case of Tegra the STB SoC device is registered
as soc0 (with totally meaningless content in the sysfs attributes) and
causes various scripts and programs to fail because they don't know how
to parse that data.
To fix this, duplicate the check from brcmstb_soc_device_early_init()
that already prevents the code from doing anything nonsensical on non-
STB platforms.
Fixes: f780429adf ("soc: brcmstb: biuctrl: Move to early_initcall")
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Being called during early_initcall() is early enough that it occurs
before SMP initialization, which is all we care about for the Bus
Interface Unit configuration.
This solves lack of BIU initialization on ARM64 platforms where we do
not have an anchor where to put the BIU initialization (since there are
no machine descriptors).
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
We may need access to family_id and product_id fairly early on boot for
other parts of the code (e.g: biuctrl.c), so split the initialization
between an early_init() and an arch_initcall() which allows us to do
that.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
In order to achieve expected MCP bus throughput on 3 particular chips:
7268, 7271 and 7278, do the appropriate programming of the MCP
interface: increase number of MCP write credits, turn on write-back
throttling when present.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add definitions for B53 systems register: CPU_MCP_FLOW_REG and
CPU_WRITEBACK_CTRL_REG. These register will be saved and restored
accordingly.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
In preparation for saving/restoring additional registers required on
some newer platforms (7268, 7271, 7278), migrate the code to use enums
and helper functions to access registers.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
On Broadcom Brahma-B53 CPUs, the CPU_CREDIT_REG offset got moved to
0x0b0 instead of 0x184, correct this such that we correcty
enable/disable write-pairing for these chips.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
In preparation for fixing and changing values in the CPU_CREDIT_REG
register for B53-based systems, make the offset parameterized.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This branch contains platform-related driver updates for ARM and ARM64,
these are the areas that bring the changes:
New drivers:
- Driver support for Renesas R-Car V3M (R8A77970)
- Power management support for Amlogic GX
- A new driver for the Tegra BPMP thermal sensor
- A new bus driver for Technologic Systems NBUS
Changes for subsystems that prefer to merge through arm-soc:
- The usual updates for reset controller drivers from Philipp Zabel,
with five added drivers for SoCs in the arc, meson, socfpa, uniphier
and mediatek families.
- Updates to the ARM SCPI and PSCI frameworks, from Sudeep Holla,
Heiner Kallweit and Lorenzo Pieralisi.
Changes specific to some ARM-based SoC
- The Freescale/NXP DPAA QBMan drivers from PowerPC can now work
on ARM as well.
- Several changes for power management on Broadcom SoCs
- Various improvements on Qualcomm, Broadcom, Amlogic, Atmel, Mediatek
- Minor Cleanups for Samsung, TI OMAP SoCs
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"This branch contains platform-related driver updates for ARM and
ARM64, these are the areas that bring the changes:
New drivers:
- driver support for Renesas R-Car V3M (R8A77970)
- power management support for Amlogic GX
- a new driver for the Tegra BPMP thermal sensor
- a new bus driver for Technologic Systems NBUS
Changes for subsystems that prefer to merge through arm-soc:
- the usual updates for reset controller drivers from Philipp Zabel,
with five added drivers for SoCs in the arc, meson, socfpa,
uniphier and mediatek families
- updates to the ARM SCPI and PSCI frameworks, from Sudeep Holla,
Heiner Kallweit and Lorenzo Pieralisi
Changes specific to some ARM-based SoC
- the Freescale/NXP DPAA QBMan drivers from PowerPC can now work on
ARM as well
- several changes for power management on Broadcom SoCs
- various improvements on Qualcomm, Broadcom, Amlogic, Atmel,
Mediatek
- minor Cleanups for Samsung, TI OMAP SoCs"
[ NOTE! This doesn't work without the previous ARM SoC device-tree pull,
because the R8A77970 driver is missing a header file that came from
that pull.
The fact that this got merged afterwards only fixes it at this point,
and bisection of that driver will fail if/when you walk into the
history of that driver. - Linus ]
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (96 commits)
soc: amlogic: meson-gx-pwrc-vpu: fix power-off when powered by bootloader
bus: add driver for the Technologic Systems NBUS
memory: omap-gpmc: Remove deprecated gpmc_update_nand_reg()
soc: qcom: remove unused label
soc: amlogic: gx pm domain: add PM and OF dependencies
drivers/firmware: psci_checker: Add missing destroy_timer_on_stack()
dt-bindings: power: add amlogic meson power domain bindings
soc: amlogic: add Meson GX VPU Domains driver
soc: qcom: Remote filesystem memory driver
dt-binding: soc: qcom: Add binding for rmtfs memory
of: reserved_mem: Accessor for acquiring reserved_mem
of/platform: Generalize /reserved-memory handling
soc: mediatek: pwrap: fix fatal compiler error
soc: mediatek: pwrap: fix compiler errors
arm64: mediatek: cleanup message for platform selection
soc: Allow test-building of MediaTek drivers
soc: mediatek: place Kconfig for all SoC drivers under menu
soc: mediatek: pwrap: add support for MT7622 SoC
soc: mediatek: pwrap: add common way for setup CS timing extenstion
soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap
..
Add Product ID and Family ID helper functions for brcmstb soc.
Signed-off-by: Al Cooper <alcooperx@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit adds support for the Broadcom STB S2/S3/S5 suspend
states on MIPS based SoCs.
This requires quite a lot of code in order to deal with the
different HW blocks that need to be quiesced during suspend:
- DDR PHY
- DDR memory controller and arbiter
- control processor
The final steps of the suspend execute in cache and there is is a little
bit of assembly code in order to shut down the DDR PHY PLL and then go
into a wait loop until a wake-up even occurs. Conversely the resume part
involves waiting for the DDR PHY PLL to come back up and resume
executions where we left.
Signed-off-by: Justin Chen <justinpopo6@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This commit adds support for the Broadcom STB S2/S3/S5 suspend states on
ARM based SoCs.
This requires quite a lot of code in order to deal with the different HW
blocks that need to be quiesced during suspend:
- DDR PHY SHIM
- DDR memory controller and sequencer
- control processor
The final steps of the suspend execute in an on-chip SRAM and there is a
little bit of assembly code in order to shut down the DDR PHY PLL and
then go into a wfi loop until a wake-up even occurs. Conversely the
resume part involves waiting for the DDR PHY PLL to come back up and
resume executions where we left.
For S3, because of our memory hashing (actual hashing code not included
for simplicity, and is bypassed) we need to relocate the writable
variables (stack) into SRAM shortly before suspending in order to leave
the DRAM untouched and create a reliable hash of its contents.
This code has been contributed by Brian Norris initially and has been
incrementally fixed and updated to support new chips by a lot of people.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Markus Mayer <mmayer@broadcom.com>
Signed-off-by: Justin Chen <justinpopo6@gmail.com>
Signed-off-by: Gareth Powell <gpowell@broadcom.com>
Signed-off-by: Doug Berger <opendmb@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
4.13, please pull the following:
- Doug adds support for the latest generation GISB bus arbiter (v7), he starts by
fixing two issues in how registers are written, and how 64-bit addresses are captured
and then he simplifies the error interception by using notifiers, which allows him
to add support for ARM64
- Markus updates the SOC_BRCMSTB Kconfig depends to cover ARM64 and BMIPS_GENERIC
systems where this code is now also used
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Merge tag 'arm-soc/for-4.13/drivers' of http://github.com/Broadcom/stblinux into next/drivers
This pull request contains Broadcom ARM/ARM64 SoCs specific driver changes for
4.13, please pull the following:
- Doug adds support for the latest generation GISB bus arbiter (v7), he starts by
fixing two issues in how registers are written, and how 64-bit addresses are captured
and then he simplifies the error interception by using notifiers, which allows him
to add support for ARM64
- Markus updates the SOC_BRCMSTB Kconfig depends to cover ARM64 and BMIPS_GENERIC
systems where this code is now also used
* tag 'arm-soc/for-4.13/drivers' of http://github.com/Broadcom/stblinux:
soc: brcmstb: enable drivers for ARM64 and BMIPS
bus: brcmstb_gisb: update to support new revision
bus: brcmstb_gisb: enable driver for ARM64 architecture
bus: brcmstb_gisb: remove low-level ARM hooks
bus: brcmstb_gisb: add notifier handling
bus: brcmstb_gisb: correct support for 64-bit address output
bus: brcmstb_gisb: Use register offsets with writes too
Signed-off-by: Olof Johansson <olof@lixom.net>
We enable the BRCMSTB SoC drivers not only for ARM, but also ARM64 and
BMIPS.
Signed-off-by: Markus Mayer <mmayer@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Remove the duplicate brcm,bcm7425-sun-top-ctrl compatible string and
replace it with brcm,bcm7435-sun-top-ctrl which was intended.
Fixes: bd0faf08dc ("soc: bcm: brcmstb: Match additional compatible strings")
Reported-by: Andreas Oberritter <obi@saftware.de>
Acked-by: Gregory Fong <gregory.0xf0@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
