Commit Graph

667 Commits

Author SHA1 Message Date
David S. Miller
9b4006dcf6 [SPARC64]: Use SLAB caches for TSB tables.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:16:39 -08:00
David S. Miller
b52439c22c [SPARC64]: Don't kill the page allocator when growing a TSB.
Try only lightly on > 1 order allocations.

If a grow fails, we are under memory pressure, so do not try
to grow the TSB for this address space any more.

If a > 0 order TSB allocation fails on a new fork, retry using
a 0 order allocation.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:16:38 -08:00
David S. Miller
05f9ca8359 [SPARC64]: Randomize mm->mmap_base when PF_RANDOMIZE is set.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:16:37 -08:00
David S. Miller
d61e16df94 [SPARC64]: Increase top of 32-bit process stack.
Put it one page below the top of the 32-bit address space.
This gives us ~16MB more address space to work with.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:16:36 -08:00
David S. Miller
a91690ddd0 [SPARC64]: Top-down address space allocation for 32-bit tasks.
Currently allocations are very constrained for 32-bit processes.
It grows down-up from 0x70000000 to 0xf0000000 which gives about
2GB of stack + dynamic mmap() space.

So support the top-down method, and we need to override the
generic helper function in order to deal with D-cache coloring.

With these changes I was able to squeeze out a mmap() just over
3.6GB in size in a 32-bit process.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:16:35 -08:00
David S. Miller
7a1ac52641 [SPARC64]: Fix and re-enable dynamic TSB sizing.
This is good for up to %50 performance improvement of some test cases.
The problem has been the race conditions, and hopefully I've plugged
them all up here.

1) There was a serious race in switch_mm() wrt. lazy TLB
   switching to and from kernel threads.

   We could erroneously skip a tsb_context_switch() and thus
   use a stale TSB across a TSB grow event.

   There is a big comment now in that function describing
   exactly how it can happen.

2) All code paths that do something with the TSB need to be
   guarded with the mm->context.lock spinlock.  This makes
   page table flushing paths properly synchronize with both
   TSB growing and TLB context changes.

3) TSB growing events are moved to the end of successful fault
   processing.  Previously it was in update_mmu_cache() but
   that is deadlock prone.  At the end of do_sparc64_fault()
   we hold no spinlocks that could deadlock the TSB grow
   sequence.  We also have dropped the address space semaphore.

While we're here, add prefetching to the copy_tsb() routine
and put it in assembler into the tsb.S file.  This piece of
code is quite time critical.

There are some small negative side effects to this code which
can be improved upon.  In particular we grab the mm->context.lock
even for the tsb insert done by update_mmu_cache() now and that's
a bit excessive.  We can get rid of that locking, and the same
lock taking in flush_tsb_user(), by disabling PSTATE_IE around
the whole operation including the capturing of the tsb pointer
and tsb_nentries value.  That would work because anyone growing
the TSB won't free up the old TSB until all cpus respond to the
TSB change cross call.

I'm not quite so confident in that optimization to put it in
right now, but eventually we might be able to and the description
is here for reference.

This code seems very solid now.  It passes several parallel GCC
bootstrap builds, and our favorite "nut cruncher" stress test which is
a full "make -j8192" build of a "make allmodconfig" kernel.  That puts
about 256 processes on each cpu's run queue, makes lots of process cpu
migrations occur, causes lots of page table and TLB flushing activity,
incurs many context version number changes, and it swaps the machine
real far out to disk even though there is 16GB of ram on this test
system. :-)

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:16:33 -08:00
David S. Miller
0c51ed93ca [SPARC64]: First cut at VIS simulator for Niagara.
Niagara does not implement some of the VIS instructions in
hardware, so we have to emulate them.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:26 -08:00
David S. Miller
90a6646bf6 [SPARC64]: Fix system type in /proc/cpuinfo and remove bogus OBP check.
Report 'sun4v' when appropriate in /proc/cpuinfo

Remove all the verifications of the OBP version string.  Just
make sure it's there, and report it raw in the bootup logs and
via /proc/cpuinfo.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:25 -08:00
David S. Miller
8935dced54 [SPARC64]: Add SMT scheduling support for Niagara.
The mapping is a simple "(cpuid >> 2) == core" for now.
Later we'll add more sophisticated code that will walk
the sun4v machine description and figure this out from
there.

We should also add core mappings for jaguar and panther
processors.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:24 -08:00
David S. Miller
17b0e199a1 [SPARC64]: Fix 32-bit truncation which broke sparsemem.
The page->flags manipulations done by the D-cache dirty
state tracking was broken because the constants were not
marked with "UL" to make them 64-bit, which means we were
clobbering the upper 32-bits of page->flags all the time.

This doesn't jive well with sparsemem which stores the
section and indexing information in the top 32-bits of
page->flags.

This is yet another sparc64 bug which has been with us
forever.

While we're here, tidy up some things in bootmem_init()
and paginig_init():

1) Pass min_low_pfn to init_bootmem_node(), it's identical
   to (phys_base >> PAGE_SHIFT) but we should use consistent
   with the variable names we print in CONFIG_BOOTMEM_DEBUG

2) max_mapnr, although no longer used, was being set
   inaccurately, we shouldn't subtract pfn_base any more.

3) All the games with phys_base in the zones_*[] arrays
   we pass to free_area_init_node() are no longer necessary.

Thanks to Josh Grebe and Fabbione for the bug reports
and testing.  Fix also verified locally on an SB2500
which had a memory layout that triggered the same problem.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:23 -08:00
David S. Miller
d1112018b4 [SPARC64]: Move over to sparsemem.
This has been pending for a long time, and the fact
that we waste a ton of ram on some configurations
kind of pushed things over the edge.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:22 -08:00
David S. Miller
ee29074d3b [SPARC64]: Fix new context version SMP handling.
Don't piggy back the SMP receive signal code to do the
context version change handling.

Instead allocate another fixed PIL number for this
asynchronous cross-call.  We can't use smp_call_function()
because this thing is invoked with interrupts disabled
and a few spinlocks held.

Also, fix smp_call_function_mask() to count "cpus" correctly.
There is no guarentee that the local cpu is in the mask
yet that is exactly what this code was assuming.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:21 -08:00
David S. Miller
a77754b4d0 [SPARC64]: Bulletproof MMU context locking.
1) Always spin_lock_init() in init_context().  The caller essentially
   clears it out, or copies the mm info from the parent.  In both
   cases we need to explicitly initialize the spinlock.

2) Always do explicit IRQ disabling while taking mm->context.lock
   and ctx_alloc_lock.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:20 -08:00
Eric Sesterhenn
9132983ae1 [SPARC64]: kzalloc() conversion
this patch converts arch/sparc64 to kzalloc usage.
Crosscompile tested with allyesconfig.

Signed-off-by: Eric Sesterhenn <snakebyte@gmx.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:19 -08:00
David S. Miller
f7c00338cf [SPARC64]: Fix loop termination in mark_kpte_bitmap()
If we were aligned, but didn't have at least 256MB left
to process, we would loop forever.

Thanks to fabbione for the report and testing the fix.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:19 -08:00
David S. Miller
74ae998772 [SPARC64]: Simplify TSB insert checks.
Don't try to avoid putting non-base page sized entries
into the user TSB.  It actually costs us more to check
this than it helps.

Eventually we'll have a multiple TSB scheme for user
processes.  Once a process starts using larger pages,
we'll allocate and use such a TSB.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:18 -08:00
David S. Miller
3cab0c3e86 [SPARC64]: More SUN4V cpu mondo bug fixing.
This cpu mondo sending interface isn't all that easy to
use correctly...

We were clearing out the wrong bits from the "mask" after getting
something other than EOK from the hypervisor.

It turns out the hypervisor can just be resent the same cpu_list[]
array, with the 0xffff "done" entries still in there, and it will do
the right thing.

So don't update or try to rebuild the cpu_list[] array to condense it.

This requires the "forward_progress" check to be done slightly
differently, but this new scheme is less bug prone than what we were
doing before.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:17 -08:00
David S. Miller
bcc28ee0bf [SPARC64]: Fix sun4v mna winfixup handling.
We were clobbering a base register before we were done
using it.  Fix a comment typo while we're here.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:16 -08:00
David S. Miller
c4f8ef77f9 [SPARC64]: Fix mini RTC driver reading.
Need to subtract 1900 from year and 1 from month before
giving it back to userspace.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:15 -08:00
David S. Miller
8bcd174116 [SPARC64]: Do not allow mapping pages within 4GB of 64-bit VA hole.
The UltraSPARC T1 manual recommends this because the chip
could instruction prefetch into the VA hole, and this would
also make decoding  certain kinds of memory access traps
more difficult (because the chip sign extends certain pieces
of trap state).

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:14 -08:00
David S. Miller
45f791eb0f [SPARC64]: Fix _PAGE_EXEC handling.
First of all, use the known _PAGE_EXEC_{4U,4V} value instead
of loading _PAGE_EXEC from memory.  We either know which one
to use by context, or we can code patch the test.

Next, we need to check executability of a PTE in the generic
TSB miss handler.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:13 -08:00
David S. Miller
92daa77e9a [SPARC64]: Fix typo in SUN4V D-TLB miss handler.
Should put FAULT_CODE_DTLB into %g3 not FAULT_CODE_ITLB.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:12 -08:00
David S. Miller
8ba706a95b [SPARC64]: Add mini-RTC driver for Starfire and SUN4V.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:10 -08:00
David S. Miller
b830ab665a [SPARC64]: Fix bugs in SUN4V cpu mondo dispatch.
There were several bugs in the SUN4V cpu mondo dispatch code.

In fact, if we ever got a EWOULDBLOCK or other error from
the hypervisor call, we'd potentially send a cpu mondo multiple
times to the same cpu and even worse we could loop until the
timeout resending the same mondo over and over to such cpus.

So let's bulletproof this thing as follows:

1) Implement cpu_mondo_send() and cpu_state() hypervisor calls
   in arch/sparc64/kernel/entry.S, add prototypes to asm/hypervisor.h

2) Don't build and update the cpulist using inline functions, this
   was causing the cpu mask to not get updated in the caller.

3) Disable interrupts during the entire mondo send, otherwise our
   cpu list and/or mondo block could get overwritten if we take
   an interrupt and do a cpu mondo send on the current cpu.

4) Check for all possible error return types from the cpu_mondo_send()
   hypervisor call.  In particular:

   HV_EOK) Our work is done, all cpus have received the mondo.
   HV_CPUERROR) One or more of the cpus in the cpu list we passed
                to the hypervisor are in error state.  Use cpu_state()
                calls over the entries in the cpu list to see which
		ones.  Record them in "error_mask" and report this
		after we are done sending the mondo to cpus which are
		not in error state.
   HV_EWOULDBLOCK) We need to keep trying.

   Any other error we consider fatal, we report the event and exit
   immediately.

5) We only timeout if forward progress is not made.  Forward progress
   is defined as having at least one cpu get the mondo successfully
   in a given cpu_mondo_send() call.  Otherwise we bump a counter
   and delay a little.  If the counter hits a limit, we signal an
   error and report the event.

Also, smp_call_function_mask() error handling reports the number
of cpus incorrectly.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:09 -08:00
David S. Miller
aac0aadf09 [SPARC64]: Fix bugs in SMP TLB context version expiration handling.
1) We must flush the TLB, duh.

2) Even if the sw context was seen to be valid, the local cpu's
   hw context can be out of date, so reload it unconditionally.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:08 -08:00
David S. Miller
6889331a12 [SPARC64]: Fix indexing into kpte_linear_bitmap.
Need to shift back up by 3 bits to get 8-byte entry
index.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:07 -08:00
David S. Miller
7a591cfe4e [SPARC64]: Avoid dcache-dirty page state management on sun4v.
It is totally wasted work, since we have no D-cache aliasing
issues on sun4v.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:06 -08:00
David S. Miller
2a3a5f5ddb [SPARC64]: Bulletproof hypervisor TLB flushing.
Check TLB flush hypervisor calls for errors and report them.

Pass HV_MMU_ALL always for now, we can add back the optimization
to avoid the I-TLB flush later.

Always explicitly page align the virtual address arguments.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:05 -08:00
David S. Miller
6cc80cfab8 [SPARC64]: Report mondo error correctly in hypervisor_xcall_deliver().
It's in "arg0" not "func".

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:04 -08:00
David S. Miller
3634476239 [SPARC64]: Niagara optimized XOR functions for RAID.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:03 -08:00
Andrew Morton
c4e9249b19 [SPARC64]: Fix binfmt_aout32.c build.
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:02 -08:00
David S. Miller
77b838fa1e [SPARC64]: destroy_context() needs to disable interrupts.
get_new_mmu_context() can be invoked from interrupt context
now for the new SMP version wrap handling.

So disable interrupt while taking ctx_alloc_lock in destroy_context()
so we don't deadlock.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:01 -08:00
David S. Miller
a0663a79ad [SPARC64]: Fix TLB context allocation with SMT style shared TLBs.
The context allocation scheme we use depends upon there being a 1<-->1
mapping from cpu to physical TLB for correctness.  Chips like Niagara
break this assumption.

So what we do is notify all cpus with a cross call when the context
version number changes, and if necessary this makes them allocate
a valid context for the address space they are running at the time.

Stress tested with make -j1024, make -j2048, and make -j4096 kernel
builds on a 32-strand, 8 core, T2000 with 16GB of ram.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:00 -08:00
David S. Miller
074d82cf68 [SPARC64]: Put syscall tables after trap table.
Otherwise with too much stuff enabled in the kernel config
we can end up with an unaligned trap table.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:59 -08:00
David S. Miller
b2bef4424c [SPARC64]: Export _PAGE_E and _PAGE_CACHE to modules.
SBUS flash driver needs it.

Noticed by Fabbione.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:58 -08:00
David S. Miller
fc50492867 [SPARC64]: Drop %gl to 0 before re-enabling PSTATE_IE in rtrap
If we take a window fault, on SUN4V set %gl to zero before we
turn PSTATE_IE back on in %pstate.  Otherwise if we take an
interrupt we'll end up with corrupt register state.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:57 -08:00
David S. Miller
d7744a0950 [SPARC64]: Create a seperate kernel TSB for 4MB/256MB mappings.
It can map all of the linear kernel mappings with zero TSB hash
conflicts for systems with 16GB or less ram.  In such cases, on
SUN4V, once we load up this TSB the first time with all the
mappings, we never take a linear kernel mapping TLB miss ever
again, the hypervisor handles them all.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:56 -08:00
David S. Miller
9cc3a1ac9a [SPARC64]: Make use of Niagara 256MB PTEs for kernel mappings.
We use a bitmap, one bit for every 256MB of memory.  If the
bit is set we can use a 256MB PTE for linear mappings, else
we have to use a 4MB PTE.

SUN4V support is there, and we can very easily add support
for Panther cpu 256MB PTEs in the future.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:55 -08:00
David S. Miller
30c91d576e [SPARC64]: Use sun4v_cpu_idle() in cpu_idle() on SUN4V.
We have to turn off the "polling nrflag" bit when we sleep
the cpu like this, so that we'll get a cross-cpu interrupt
to wake the processor up from the yield.

We also have to disable PSTATE_IE in %pstate around the yield
call and recheck need_resched() in order to avoid any races.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:54 -08:00
David S. Miller
689126a48a [SPARC64] math-emu: Delete debugging printk left by previous commit.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:53 -08:00
David S. Miller
6f5374c91f [SPARC64]: Add sun4v_cpu_yield().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:52 -08:00
David S. Miller
1bd0cd74d1 [SPARC64]: Kill cpudata->idle_volume.
Set, but never used.

We used to use this for dynamic IRQ retargetting, but that
code died a long time ago.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:51 -08:00
David S. Miller
8ca2557c48 [SPARC64]: Niagara optimized memset/bzero/clear_user.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:50 -08:00
David S. Miller
d371c0c174 [SPARC64]: Pass multiple CPUs at once to hypervisor cross-call API.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:49 -08:00
David S. Miller
c79f76777d [SPARC64]: Args to SUNW,set-trap-table are 64-bit.
They were getting truncated to 32-bit and this is very bad
when your MMU fault status area is in physical memory above
4GB on SUN4V.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:48 -08:00
David S. Miller
4e74ae800b [SPARC64]: Handle unimplemented FPU square-root on Niagara.
The math-emu code only expects unfinished fpop traps when
emulating FPU sqrt instructions on pre-Niagara chips.
On Niagara we can get unimplemented fpop, so handle that.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:48 -08:00
David S. Miller
55555633bd [SPARC64]: Typo in sun4v_data_access_exception log message.
Should be "Dax" not "Iax".

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:46 -08:00
David S. Miller
d82965c167 [SPARC64]: Handle zero-length map requests in pci_sun4v.c
By simply changing the do-while loop into a plain
while loop.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:45 -08:00
David S. Miller
abf3b7bd89 [SPARC64]: Kill stray PGLIST_NENTS check in pci_sun4v.c
I forgot to remove the one in pci_4v_map_sg() during the
iommu batching commit.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:44 -08:00
David S. Miller
39334a4b2c [SPARC64]: Fix typo in dump_tl1_traplog()
Actually make use of the 'limit' we compute.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:43 -08:00
David S. Miller
37133c006c [SPARC64]: Disable smp_report_regs() for now.
It's extremely noisy and causes much grief on slow
consoles with large numbers of cpus.

We'll have to provide this some saner way in order
to re-enable this.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:42 -08:00
David S. Miller
6a32fd4d0d [SPARC64]: Remove PGLIST_NENTS PCI IOMMU mapping limitation on SUN4V.
Use a batching queue system for IOMMU mapping setup,
with a page sized batch.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:41 -08:00
David S. Miller
04d74758eb [SPARC64]: Use KERN_EMERG in dump_tl1_traplog() and sun4v TLB errors.
We're about to seriously die in these cases so it is important
that the messages make it to the console.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:40 -08:00
David S. Miller
24c523ecc6 [SPARC64]: Fix unaligned access winfxup handling on SUN4V.
Another case where we have to force ourselves into global register
level one.  Also make sure the arguments passed to sun4v_do_mna() are
correct.

This area actually needs some more work, for example spill fixup is
not necessarily going to do the right thing for this case.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:39 -08:00
David S. Miller
6cc200db95 [SPARC64]: Set %gl to 1 in kvmap_itlb_longpath on SUN4V.
Just like kvmap_dtlb_longpath we have to force the
global register level to one in order to mimick the
PSTATE_MG --> PSTATE_AG trasition done on SUN4U.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:39 -08:00
David S. Miller
0f15952ac8 [SPARC64]: Export a PAGE_SHARED symbol.
For drivers/media/*, noticed by Fabbione.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:36 -08:00
David S. Miller
8b23427441 [SPARC64]: More TLB/TSB handling fixes.
The SUN4V convention with non-shared TSBs is that the context
bit of the TAG is clear.  So we have to choose an "invalid"
bit and initialize new TSBs appropriately.  Otherwise a zero
TAG looks "valid".

Make sure, for the window fixup cases, that we use the right
global registers and that we don't potentially trample on
the live global registers in etrap/rtrap handling (%g2 and
%g6) and that we put the missing virtual address properly
in %g5.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:34 -08:00
David S. Miller
7adb37fe80 [SPARC64]: Don't do anything in flush_ptrace_access() on SUN4V.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:33 -08:00
David S. Miller
6c8927c963 [SPARC64]: Fix some SUN4V TLB handling bugs.
1) Add error return checking for TLB load hypervisor
   calls.

2) Don't fallthru to dtlb tsb miss handler from itlb tsb
   miss handler, oops.

3) On window fixups, propagate fault information to fixup
   handler correctly.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:32 -08:00
David S. Miller
12e126ad22 [SPARC64]: Check for errors in hypervisor_tlb_lock().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:31 -08:00
David S. Miller
52845cdb3b [SPARC64]: Init boot cpu's trap_block[] before paging_init()
It must be ready when we take over the trap table.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:30 -08:00
David S. Miller
3763be32d5 [SPARC64]: Define ARCH_HAS_READ_CURRENT_TIMER.
This gives more consistent bogomips and delay() semantics,
especially on sun4v.  It gives weird looking values though...

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:29 -08:00
David S. Miller
3f19a84e39 [SPARC64]: Set associativity of kernel TSB descriptor correctly.
It should be 1, not 0.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:29 -08:00
David S. Miller
c857e3fdbc [SPARC64]: __bzero_noasi --> __clear_user
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:28 -08:00
David S. Miller
46f8604714 [SPARC64]: Put SUN4V ITSB miss into correct trap table entry.
It's 0x9 not 0xb.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:27 -08:00
David S. Miller
3b3ab2eb9c [SPARC64]: Use phys tsb address in tsb_insert() in SUN4V.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:25 -08:00
David S. Miller
ebd8c56c5a [SPARC64]: Fix uniprocessor IRQ targetting on SUN4V.
We need to use the real hardware processor ID when
targetting interrupts, not the "define to 0" thing
the uniprocessor build gives us.

Also, fill in the Node-ID and Agent-ID fields properly
on sun4u/Safari.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:24 -08:00
David S. Miller
101d5c18a9 [SPARC64]: Fix PCI IRQ probing regression.
If the top-level cnode had multi entries in it's "reg"
property, we'd fail.  The buffer wasn't large enough in
such cases.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:23 -08:00
David S. Miller
72aff53f1f [SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile.  We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.

This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.

In order to achieve this:

1) Change sun4v_init_mondo_queues() so that it can operate in
   several modes.

   It can allocate the queues, or install them in the current
   processor, or both.

   The boot cpu does both in it's call early on.

   Later, the boot cpu allocates the sibling cpu queue, starts
   the sibling cpu, then the sibling cpu loads them in.

2) init_cur_cpu_trap() is changed to take the current_thread_info()
   as an argument instead of reading %g6 directly on the current
   cpu.

3) Create a trampoline stack for the sibling cpus.  We do our basic
   kernel calls using this stack, which is locked into the kernel
   image, then go to our proper thread stack after taking over the
   trap table.

4) While we are in this delicate startup state, we put 0xdeadbeef
   into %g4/%g5/%g6 in order to catch accidental accesses.

5) On the final prom_set_trap_table*() call, we put &init_thread_union
   into %g6.  This is a hack to make prom_world(0) work.  All that
   wants to do is restore the %asi register using
   get_thread_current_ds().

Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else.  This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:22 -08:00
David S. Miller
19a0d585e8 [SPARC64]: Disable smp_report_regs() for now.
For 32 cpus and a slow console, it just wedges the
machine especially with DETECT_SOFTLOCKUP enabled.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:21 -08:00
David S. Miller
6154f94f0e [SPARC64]: Rewrite pci_intmap_match().
The whole algorithm was wrong.  What we need to do is:

1) Walk each PCI bus above this device on the path to the
   PCI controller nexus, and for each:
      a) If interrupt-map exists, apply it, record IRQ controller node
      b) Else, swivel interrupt number using PCI_SLOT(), use PCI bus
	 parent OBP node as controller node
      c) Walk up to "controller node" until we hit the first PCI bus
	 in this domain, or "controller node" is the PCI controller
	 OBP node
2) If we walked to PCI controller OBP node, we're done.
3) Else, apply PCI controller interrupt-map to interrupt.

There is some stuff that needs to be checked out for ebus and
isa, but the PCI part is good to go.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:20 -08:00
David S. Miller
14f6689cbb [SPARC64]: Don't set interrupt state to IDLE in enable_irq().
We'll lose events that way.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:20 -08:00
David S. Miller
af02bec662 [SPARC64]: Fix return from trap on SUN4V.
We need to set the global register set _AND_ disable
PSTATE_IE in %pstate.  The original patch sequence was
leaving PSTATE_IE enabled when returning to kernel mode,
oops.

This fixes the random register corruption being seen
on SUN4V.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:19 -08:00
David S. Miller
22780e23c6 [SPARC64]: Set dummy bucket->{imap,iclr} unique on SUN4V.
So that free_irq() disable's the IRQ correctly.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:17 -08:00
David S. Miller
94f8762db9 [SPARC64]: Add sun4v_cpu_qconf() hypervisor call.
Call it from register_one_mondo().

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:16 -08:00
David S. Miller
8e42550c68 [SPARC64]: do_fptrap needs to load the thread reg into %g6.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:14 -08:00
David S. Miller
9b6b46470c [SPARC64]: Fix bogus call to sun4v_mna in winfixup code.
The C function is named sun4v_do_mna not sun4v_mna.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:13 -08:00
David S. Miller
3d6395cb77 [SPARC64]: Fix tl1 trap state capture/dump on SUN4V.
No trap levels above 2 in privileged mode on SUN4V.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:12 -08:00
David S. Miller
e7a0453ef8 [SPARC64] PCI: Size TSB correctly on SUN4V.
Forgot to multiply by 8 * 1024, oops.  Correct the size constant when
the virtual-dma arena is 2GB in size, it should bet 256 not 128.

Finally, log some info about the TSB at probe time.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:10 -08:00
David S. Miller
c7f81d42d3 [SPARC64]: Don't use ASI_QUAD_LDD_PHYS on SUN4V.
Need to use ASI_QUAD_LDD_PHYS_4V instead.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:09 -08:00
David S. Miller
a7b31bac69 [SPARC64]: Do not write garbage into %pstate in tsb_context_switch().
For SUN4V, we were clobbering %o5 to do the hypervisor call.
This clobbers the saved %pstate value and we end up writing
garbage into that register as a result.  Oops.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:08 -08:00
David S. Miller
de635d833f [SPARC64]: Fix flush_tsb_user() on SUN4V.
Needs to use physical addressing just like cheetah_plus.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:07 -08:00
David S. Miller
1daef08a12 [SPARC64]: Fix comment typo in __flush_tlb_kernel_range.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:06 -08:00
David S. Miller
9d29a3fafd [SPARC64]: Decode virtual-devices interrupts correctly.
Need to translate through the interrupt-map{,-mask] properties.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:05 -08:00
David S. Miller
7890f794e0 [SPARC64]: Add prom_{start,stop}cpu_cpuid().
Use prom_startcpu_cpuid() on SUN4V instead of prom_startcpu().

We should really test for "SUNW,start-cpu-by-cpuid" presence
and use it if present even on SUN4U.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:04 -08:00
David S. Miller
63c2a0e598 [SPARC64]: Fix pci_intmap_match().
When crawling up the PCI bus chain, stop at the first node
that has an interrupt-map property before we hit the root.

Also, if we use a bus interrupt-{map,mask} do not forget to
update the 'intmask' pointer as we do for the 'intmap' pointer.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:03 -08:00
David S. Miller
ab66a50e31 [SPARC64]: Two IRQ handling fixes.
On SUN4V, force IRQ state to idle in enable_irq().  However,
I'm still not sure this is %100 correct.

Call add_interrupt_randomness() on SUN4V too.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:02 -08:00
David S. Miller
f03b8a5468 [SPARC64]: Use different cache sizing defaults on SUN4V.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:01 -08:00
David S. Miller
329c68b218 [SPARC64]: Make lack of interrupt-map-* a fatal error on SUN4V.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:00 -08:00
David S. Miller
abd92b2d21 [SPARC64]: Fix sun4v_intr_setenabled() return value check in enable_irq().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:59 -08:00
David S. Miller
355db99860 [SPARC64]: Explicitly init *nregs to 0 in find_device_prom_node().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:58 -08:00
David S. Miller
987b6de710 [SPARC64]: Restrict PCI bus scanning on SUN4V.
On the PBM's first bus number, only allow device 0, function 0, to be
poked at with PCI config space accesses.

For some reason, this single device responds to all device numbers.

Also, reduce the verbiage of the debugging log printk's for PCI cfg
space accesses in the SUN4V PCI controller driver, so that it doesn't
overwhelm the slow SUN4V hypervisor console.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:57 -08:00
David S. Miller
9f8a5b843f [SPARC64]: Fix C-function name called by sun4v_mna trap code.
The trap code was calling itself :-)

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:56 -08:00
David S. Miller
fbf1c68eaf [SPARC64]: Don't printk() any messaages in sun4v_build_irq().
It just clutters up the log.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:55 -08:00
David S. Miller
e7093703d9 [SPARC64]: INO is never fully specified already on SUN4V.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:54 -08:00
David S. Miller
4a07e646c5 [SPARC64]: Kill sun4v_register_fault_status() on SMP.
That now gets done as a side effect of taking over the
trap table from OBP.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:54 -08:00
David S. Miller
3af6e01e9a [SPARC64]: arch/sparc64/kernel/trampoline.S needs asm/cpudata.h
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:52 -08:00
David S. Miller
c4bea28839 [SPARC64]: Make error codes available from sun4v_intr_get*().
And check for errors at call sites.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:51 -08:00
David S. Miller
4bf447d6f7 [SPARC64]: Pass correct ino to sun4v_intr_*().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:50 -08:00
David S. Miller
a615fea48b [SPARC64]: Use TRAP_LOAD_IRQ_WORK() in sun4v device mondo handler.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:49 -08:00
David S. Miller
7c8f486ae7 [SPARC64]: Fix IOMMU mapping on sun4v.
We should dynamically allocate the per-cpu pglist not use
an in-kernel-image datum, since __pa() does not work on
such addresses.

Also, consistently use "u32" for devhandle.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:48 -08:00
David S. Miller
87bdc367ca [SPARC64]: Trim down sun4v IRQ translation kernel log message.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:47 -08:00
David S. Miller
d5a2aa241a [SPARC64] sunhv: Bug fixes.
Add udelay to polling console write loop, and increment
the loop limit.

Name the device "ttyHV" and pass that to add_preferred_console()
when we're using hypervisor console.

Kill sunhv_console_setup(), it's empty.

Handle the case where we don't want to use hypervisor console.
(ie. we have a head attached to a sun4v machine)

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:46 -08:00
David S. Miller
e77227eb4e [SPARC64]: Probe virtual-devices root node on sun4v.
This is where we learn how to get the interrupts
for things like the hypervisor console device.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:44 -08:00
David S. Miller
d5eb400430 [SPARC64]: Kill spurious semicolon in sun4v_pci_init().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:43 -08:00
David S. Miller
10951ee610 [SPARC64]: Program IRQ registers correctly on sun4v.
Need to use hypervisor calls instead of direct register
accesses.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:41 -08:00
David S. Miller
e3999574b4 [SPARC64]: Generic sun4v_build_irq().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:40 -08:00
David S. Miller
10804828fd [SPARC64]: More SUN4V PCI work.
Get bus range from child of PCI controller root nexus.
This is actually a hack, but the PCI-E bridge sitting
at the top of the PCI tree responds to PCI config cycles
for every device number, so best to just ignore it for now.

Preliminary PCI irq routing, needs lots of work.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:39 -08:00
David S. Miller
bf941d6cd6 [SPARC64]: Log faulting vaddr when bogus kernel PC detected.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:38 -08:00
David S. Miller
6c0f402f6c [SPARC64]: Implement rest of generic interrupt hypervisor calls.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:37 -08:00
David S. Miller
85dfa19ba9 [SPARC64]: Move devino_to_sysino out of pci_sun4v_asm.S
It is not PCI specific, it is for all system interrupts.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:36 -08:00
David S. Miller
059833eb81 [SPARC64]: Range check bus number in SUN4V PCI controller driver.
It has to be somewhere in the range from pbm->pci_first_busno to
pbm->pci_last_busno, inclusive.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:36 -08:00
David S. Miller
0b522497a1 [SPARC64]: Missing 'return' statement in sun4v_pci_init().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:35 -08:00
David S. Miller
c260926750 [SPARC64]: Implement basic pci_sun4v_scan_bus().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:34 -08:00
David S. Miller
3833789bb2 [SPARC64]: PCI-SUN4V fixes.
Clear top 8-bits of physical addresses in "ranges" property.
This gives the actual physical address.

Detect PBM-A vs. PBM-B by checking bit 0x40 of the devhandle.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:33 -08:00
David S. Miller
cf627156c4 [SPARC64]: Use inline patching for critical PTE operations.
This handles the SUN4U vs SUN4V PTE layout differences
with near zero performance cost.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:32 -08:00
David S. Miller
ff02e0d26f [SPARC64]: Move PTE field definitions back into asm/pgtable.h
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:31 -08:00
David S. Miller
221b2fb818 [SPARC64]: Don't expect cfg space in PCI PBM ranges on SUN4V.
PCI cfg space is accessed transparently through the Hypervisor and not
through direct cpu PIO operations.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:30 -08:00
David S. Miller
6241e5cc6a [SPARC64]: Fix branch signedness bug in all code patching.
The bug that hit SUN4V TLB patching exists elsewhere.
Make sure we cure all such cases.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:29 -08:00
David S. Miller
1a7a242c89 [SPARC64]: Recognize "virtual-console" as input and output console device.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:28 -08:00
David S. Miller
02fead7505 [SPARC64]: Do not try to synchronize %stick registers on SUN4V.
Writes by privileged code are not allowed.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:27 -08:00
David S. Miller
7aa6264543 [SPARC64]: Do not try to write to %tick or %stick on SUN4V.
Writes by privileged code are disallowed.  The hypervisor manages
the non-privileged bit.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:27 -08:00
David S. Miller
b5a37e96b8 [SPARC64]: Fix mondo queue allocations.
We have to use bootmem during init_IRQ and page alloc
for sibling cpu calls.

Also, fix incorrect hypervisor call return value
checks in the hypervisor SMP cpu mondo send code.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:26 -08:00
David S. Miller
c4bce90ea2 [SPARC64]: Deal with PTE layout differences in SUN4V.
Yes, you heard it right, they changed the PTE layout for
SUN4V.  Ho hum...

This is the simple and inefficient way to support this.
It'll get optimized, don't worry.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:25 -08:00
David S. Miller
490384e752 [SPARC64]: Register kernel TSB with hypervisor.
We do this right after we take over the trap table from OBP.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:23 -08:00
David S. Miller
459b6e621e [SPARC64]: Fix some SUN4V TLB miss bugs.
Code patching did not sign extend negative branch
offsets correctly.

Kernel TLB miss path needs patching and %g4 register
preservation in order to handle SUN4V correctly.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:23 -08:00
David S. Miller
fd05068d7b [SPARC64]: Fix typo in sun4v_patch().
Second instruction offset is '4' not '3'.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:22 -08:00
David S. Miller
6cebb52094 [SPARC64]: Fix sun4v early bootup.
prom_sun4v_name should be "sun4v" not "SUNW,sun4v"

Also, this is too early to make use of the
.sun4v_Xinsn_patch code patching, so just check
things manually.

This gets us at least to prom_init() on Niagara.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:21 -08:00
David S. Miller
0d4bc95b9c [SPARC64]: Fix some Niagara memcpy() bugs.
We need to restore the %asi register properly.
For the kernel this means get_fs(), for user this
means ASI_PNF.

Also, NGcopy_to_user.S was including U3memcpy.S instead
of NGmemcpy.S, oops :-)

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:20 -08:00
David S. Miller
e92b92571c [SPARC64]: Handle hypervisor case correctly in copy_tsb().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:19 -08:00
David S. Miller
4bdff41464 [SPARC64]: Fetch bootup time of day from Hypervisor.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:17 -08:00
David S. Miller
36a68e77c5 [SPARC64]: Simplify sun4v TLB handling using macros.
There was also a bug in sun4v_itlb_miss, it loaded the
MMU Fault Status base into %g3 instead of %g2.

This pointed out a fast path for TSB miss processing,
since we have %g2 with the MMU Fault Status base, we
can use that to quickly load up the PGD phys address.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:16 -08:00
David S. Miller
12eaa328f9 [SPARC64]: Use ASI_SCRATCHPAD address 0x0 properly.
This is where the virtual address of the fault status
area belongs.

To set it up we don't make a hypervisor call, instead
we call OBP's SUNW,set-trap-table with the real address
of the fault status area as the second argument.  And
right before that call we write the virtual address into
ASI_SCRATCHPAD vaddr 0x0.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:15 -08:00
David S. Miller
1839794464 [SPARC64]: First cut at SUN4V PCI IOMMU handling.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:15 -08:00
David S. Miller
164c220fa3 [SPARC64]: Fix hypervisor call arg passing.
Function goes in %o5, args go in %o0 --> %o5.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:14 -08:00
David S. Miller
7eae642f75 [SPARC64]: Implement SUN4V PCI config space access.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:12 -08:00
David S. Miller
bade562216 [SPARC64]: More SUN4V PCI controller work.
Add assembler file for PCI hypervisor calls.
Setup basic skeleton of SUN4V PCI controller driver.

Add 32-bit devhandle to PBM struct, as this is needed for
hypervisor calls.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:11 -08:00
David S. Miller
8f6a93a196 [SPARC64]: Beginnings of SUN4V PCI controller support.
Abstract out IOMMU operations so that we can have a different
set of calls on sun4v, which needs to do things through
hypervisor calls.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:10 -08:00
David S. Miller
4cce4b7cc5 [SPARC64]: Fetch cpu mid properly on sun4v.
If there is a "cpuid" property, use that.  Else suck
it out of the top bits of the "reg" property.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:09 -08:00
David S. Miller
ed6b0b4543 [SPARC64]: SUN4V memory exception trap handlers.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:07 -08:00
David S. Miller
618e9ed98a [SPARC64]: Hypervisor TSB context switching.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:06 -08:00
David S. Miller
aa9143b971 [SPARC64]: Implement sun4v TSB miss handlers.
When we register a TSB with the hypervisor, so that it or hardware can
handle TLB misses and do the TSB walk for us, the hypervisor traps
down to these trap when it incurs a TSB miss.

Processing is simple, we load the missing virtual address and context,
and do a full page table walk.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:05 -08:00
David S. Miller
12816ab38a [SPARC64]: kernel/cpu.c needs asm/spitfire.h
For 'tlb_type'.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:05 -08:00
David S. Miller
3a8c069d0e [SPARC64]: Print ARCH as SUN4V when tlb_type is hypervisor.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:04 -08:00
David S. Miller
d82ace7dc4 [SPARC64]: Detect sun4v early in boot process.
We look for "SUNW,sun4v" in the 'compatible' property
of the root OBP device tree node.

Protect every %ver register access, to make sure it is
not touched on sun4v, as %ver is hyperprivileged there.

Lock kernel TLB entries using hypervisor calls instead of
calls into OBP.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:03 -08:00
David S. Miller
1d2f1f90a1 [SPARC64]: Sun4v cross-call sending support.
Technically the hypervisor call supports sending in a list
of all cpus to get the cross-call, but I only pass in one
cpu at a time for now.

The multi-cpu support is there, just ifdef'd out so it's easy to
enable or delete it later.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:02 -08:00
David S. Miller
5b0c0572fc [SPARC64]: Sun4v interrupt handling.
Sun4v has 4 interrupt queues: cpu, device, resumable errors,
and non-resumable errors.  A set of head/tail offset pointers
help maintain a work queue in physical memory.  The entries
are 64-bytes in size.

Each queue is allocated then registered with the hypervisor
as we bring cpus up.

The two error queues each get a kernel side buffer that we
use to quickly empty the main interrupt queue before we
call up to C code to log the event and possibly take evasive
action.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:01 -08:00
David S. Miller
ac29c11d4c [SPARC64]: Allocate and register the 4 sun4v mondo queues at bootup.
Needs to occur before we enable PSTATE_IE in %pstate.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:00 -08:00
David S. Miller
e088ad7ca3 [SPARC64]: Verify all trap_per_cpu assembler offsets in trap_init()
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:59 -08:00
David S. Miller
8b11bd12af [SPARC64]: Patch up mmu context register writes for sun4v.
sun4v uses ASI_MMU instead of ASI_DMMU

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:56 -08:00
David S. Miller
481295f982 [SPARC64]: Register per-cpu fault status area with sun4v hypervisor.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:55 -08:00
David S. Miller
8591e30272 [SPARC64]: Niagara copy/clear page.
Happily we have no D-cache aliasing issues on these
chips, so the implementation is very straightforward.

Add a stub in bootup which will be where the patching
calls will be made for niagara/sun4v/hypervisor.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:54 -08:00
David S. Miller
df7d6aec96 [SPARC64]: Rename gl_{1,2}insn_patch --> sun4v_{1,2}insn_patch
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:53 -08:00
David S. Miller
d257d5da39 [SPARC64]: Initial sun4v TLB miss handling infrastructure.
Things are a little tricky because, unlike sun4u, we have
to:

1) do a hypervisor trap to do the TLB load.
2) do the TSB lookup calculations by hand

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:52 -08:00
David S. Miller
840aaef8db [SPARC64]: Add missing memory barriers to instruction patching functions.
V9 requires a write memory barrier before the instruction flush.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:51 -08:00
David S. Miller
45fec05f80 [SPARC64]: Sanitize %pstate writes for sun4v.
If we're just switching between different alternate global
sets, nop it out on sun4v.  Also, get rid of all of the
alternate global save/restore in the OBP CIF trampoline code.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:50 -08:00
David S. Miller
314981ac71 [SPARC64]: Kill all %pstate changes in context switch code.
They are totally unnecessary because:

1) Interrupts are already disabled when switch_to()
   runs.

2) We don't use hard-coded alternate globals any longer.

This found a case in rtrap, which still assumed alternate
global %g6 was current_thread_info(), and that is fixed
by this changeset as well.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:49 -08:00
David S. Miller
936f482af1 [SPARC64]: Add initial code to twiddle %gl on trap entry/exit.
Instead of setting/clearing PSTATE_AG we have to change
the %gl register value on sun4v.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:48 -08:00
David S. Miller
6e02493a7f [SPARC64]: Fill dead cycles on trap entry with real work.
As we save trap state onto the stack, the store buffer fills up
mid-way through and we stall for several cycles as the store buffer
trickles out to the L2 cache.  Meanwhile we can do some privileged
register reads and other calculations, essentially for free.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:47 -08:00
David S. Miller
d96b81533b [SPARC64]: Add sun4v case to __GET_CPUID() patch tables.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:45 -08:00
David S. Miller
398d108308 [SPARC64]: Niagara optimized memcpy() and copy_{to,from}_user().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:42 -08:00
David S. Miller
a43fe0e789 [SPARC64]: Add some hypervisor tlb_type checks.
And more consistently check cheetah{,_plus} instead
of assuming anything not spitfire is cheetah{,_plus}.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:40 -08:00
David S. Miller
52bf082f0a [SPARC64]: SUN4V hypervisor TLB flush support code.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:38 -08:00
David S. Miller
314ef68597 [SPARC64]: Refine register window trap handling.
When saving and restoing trap state, do the window spill/fill
handling inline so that we never trap deeper than 2 trap levels.
This is important for chips like Niagara.

The window fixup code is massively simplified, and many more
improvements are now possible.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:36 -08:00
David S. Miller
ffe483d552 [SPARC64]: Add explicit register args to trap state loading macros.
This, as well as making the code cleaner, allows a simplification in
the TSB miss handling path.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:35 -08:00
David S. Miller
92704a1c63 [SPARC64]: Refine code sequences to get the cpu id.
On uniprocessor, it's always zero for optimize that.

On SMP, the jmpl to the stub kills the return address stack in the cpu
branch prediction logic, so expand the code sequence inline and use a
code patching section to fix things up.  This also always better and
explicit register selection, which will be taken advantage of in a
future changeset.

The hard_smp_processor_id() function is big, so do not inline it.

Fix up tests for Jalapeno to also test for Serrano chips too.  These
tests want "jbus Ultra-IIIi" cases to match, so that is what we should
test for.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:35 -08:00
David S. Miller
f4e841da30 [SPARC64]: Turn off TSB growing for now.
There are several tricky races involved with growing the TSB.  So just
use base-size TSBs for user contexts and we can revisit enabling this
later.

One part of the SMP problems is that tsb_context_switch() can see
partially updated TSB configuration state if tsb_grow() is running in
parallel.  That's easily solved with a seqlock taken as a writer by
tsb_grow() and taken as a reader to capture all the TSB config state
in tsb_context_switch().

Then there is flush_tsb_user() running in parallel with a tsb_grow().
In theory we could take the seqlock as a reader there too, and just
resample the TSB pointer and reflush but that looks really ugly.

Lastly, I believe there is a case with threads that results in a TSB
entry lock bit being set spuriously which will cause the next access
to that TSB entry to wedge the cpu (since the TSB entry lock bit will
never clear).  It's either copy_tsb() or some bug elsewhere in the TSB
assembly.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:34 -08:00
David S. Miller
7bec08e38a [SPARC64]: Correctable ECC errors cannot occur at trap level > 0.
The are distrupting, which by the sparc v9 definition means they
can only occur when interrupts are enabled in the %pstate register.
This never occurs in any of the trap handling code running at
trap levels > 0.

So just mark it as an unexpected trap.

This allows us to kill off the cee_stuff member of struct thread_info.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:33 -08:00
David S. Miller
517af33237 [SPARC64]: Access TSB with physical addresses when possible.
This way we don't need to lock the TSB into the TLB.
The trick is that every TSB load/store is registered into
a special instruction patch section.  The default uses
virtual addresses, and the patch instructions use physical
address load/stores.

We can't do this on all chips because only cheetah+ and later
have the physical variant of the atomic quad load.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:32 -08:00
David S. Miller
30a6ecad96 [SPARC64]: Don't clobber alt-global %g4 on window fixups.
If we are returning back to kernel mode, %g4 could be live
(for example, in the case where we window spill in the etrap
code).  So do not change it's value if going back to kernel.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:30 -08:00
David S. Miller
86b818687d [SPARC64]: Fix race in LOAD_PER_CPU_BASE()
Since we use %g5 itself as a temporary, it can get clobbered
if we take an interrupt mid-stream and thus cause end up with
the final %g5 value too early as a result of rtrap processing.

Set %g5 at the very end, atomically, to avoid this problem.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:29 -08:00
David S. Miller
9954863975 [SPARC64]: Kill swapper_pgd_zero, totally unused.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:28 -08:00
David S. Miller
9bc657b28e [SPARC64]: Fix too early reference to %g6
%g6 is not necessarily set to current_thread_info()
at sparc64_realfault_common.  So store the fault
code and address after we invoke etrap and %g6 is
properly set up.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:27 -08:00
David S. Miller
764afe2edb [SPARC64]: Kill hard-coded %pstate setting in sparc_exit.
Just flip the bit off of whatever it's currently set to.
PSTATE_IE is guarenteed to be enabled when we get here.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:26 -08:00
David S. Miller
2f7ee7c63f [SPARC64]: Increase swapper_tsb size to 32K.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:26 -08:00
David S. Miller
a8b900d801 [SPARC64]: Kill sole argument passed to setup_tba().
No longer used, and move extern declaration to a header file.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:25 -08:00
David S. Miller
3487d1d441 [SPARC64]: Kill PROM locked TLB entry preservation code.
It is totally unnecessary complexity.  After we take over
the trap table, we handle all PROM tlb misses fully.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:24 -08:00
David S. Miller
6b6d017235 [SPARC64]: Use sparc64_highest_unlocked_tlb_ent in __tsb_context_switch()
Instead of ugly hard-coded value.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:23 -08:00
David S. Miller
4da808c352 [SPARC64]: Fix bogus flush instruction usage.
Some of the trap code was still assuming that alternate
global %g6 was hard coded with current_thread_info().
Let's just consistently flush at KERNBASE when we need
a pipeline synchronization.  That's locked into the TLB
and will always work.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:22 -08:00
David S. Miller
4753eb2ac7 [SPARC64]: Fix incorrect TSB lock bit handling.
The TSB_LOCK_BIT define is actually a special
value shifted down by 32-bits for the assembler
code macros.

In C code, this isn't what we want.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:21 -08:00
David S. Miller
96c6e0d8e2 [SPARC64]: Kill {save,restore}_alternate_globals()
No longer needed now that we no longer have hard-coded
alternate global register usage.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:20 -08:00
David S. Miller
b70c0fa161 [SPARC64]: Preload TSB entries from update_mmu_cache().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:19 -08:00
David S. Miller
bd40791e1d [SPARC64]: Dynamically grow TSB in response to RSS growth.
As the RSS grows, grow the TSB in order to reduce the likelyhood
of hash collisions and thus poor hit rates in the TSB.

This definitely needs some serious tuning.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:18 -08:00
David S. Miller
98c5584cfc [SPARC64]: Add infrastructure for dynamic TSB sizing.
This also cleans up tsb_context_switch().  The assembler
routine is now __tsb_context_switch() and the former is
an inline function that picks out the bits from the mm_struct
and passes it into the assembler code as arguments.

setup_tsb_parms() computes the locked TLB entry to map the
TSB.  Later when we support using the physical address quad
load instructions of Cheetah+ and later, we'll simply use
the physical address for the TSB register value and set
the map virtual and PTE both to zero.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:17 -08:00
David S. Miller
09f94287f7 [SPARC64]: TSB refinements.
Move {init_new,destroy}_context() out of line.

Do not put huge pages into the TSB, only base page size translations.
There are some clever things we could do here, but for now let's be
correct instead of fancy.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:16 -08:00
David S. Miller
56fb4df6da [SPARC64]: Elminate all usage of hard-coded trap globals.
UltraSPARC has special sets of global registers which are switched to
for certain trap types.  There is one set for MMU related traps, one
set of Interrupt Vector processing, and another set (called the
Alternate globals) for all other trap types.

For what seems like forever we've hard coded the values in some of
these trap registers.  Some examples include:

1) Interrupt Vector global %g6 holds current processors interrupt
   work struct where received interrupts are managed for IRQ handler
   dispatch.

2) MMU global %g7 holds the base of the page tables of the currently
   active address space.

3) Alternate global %g6 held the current_thread_info() value.

Such hardcoding has resulted in some serious issues in many areas.
There are some code sequences where having another register available
would help clean up the implementation.  Taking traps such as
cross-calls from the OBP firmware requires some trick code sequences
wherein we have to save away and restore all of the special sets of
global registers when we enter/exit OBP.

We were also using the IMMU TSB register on SMP to hold the per-cpu
area base address, which doesn't work any longer now that we actually
use the TSB facility of the cpu.

The implementation is pretty straight forward.  One tricky bit is
getting the current processor ID as that is different on different cpu
variants.  We use a stub with a fancy calling convention which we
patch at boot time.  The calling convention is that the stub is
branched to and the (PC - 4) to return to is in register %g1.  The cpu
number is left in %g6.  This stub can be invoked by using the
__GET_CPUID macro.

We use an array of per-cpu trap state to store the current thread and
physical address of the current address space's page tables.  The
TRAP_LOAD_THREAD_REG loads %g6 with the current thread from this
table, it uses __GET_CPUID and also clobbers %g1.

TRAP_LOAD_IRQ_WORK is used by the interrupt vector processing to load
the current processor's IRQ software state into %g6.  It also uses
__GET_CPUID and clobbers %g1.

Finally, TRAP_LOAD_PGD_PHYS loads the physical address base of the
current address space's page tables into %g7, it clobbers %g1 and uses
__GET_CPUID.

Many refinements are possible, as well as some tuning, with this stuff
in place.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:16 -08:00
David S. Miller
3c93646524 [SPARC64]: Kill pgtable quicklists and use SLAB.
Taking a nod from the powerpc port.

With the per-cpu caching of both the page allocator and SLAB, the
pgtable quicklist scheme becomes relatively silly and primitive.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:14 -08:00
David S. Miller
05e28f9de6 [SPARC64]: No need to D-cache color page tables any longer.
Unlike the virtual page tables, the new TSB scheme does not
require this ugly hack.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:13 -08:00
David S. Miller
74bf4312ff [SPARC64]: Move away from virtual page tables, part 1.
We now use the TSB hardware assist features of the UltraSPARC
MMUs.

SMP is currently knowingly broken, we need to find another place
to store the per-cpu base pointers.  We hid them away in the TSB
base register, and that obviously will not work any more :-)

Another known broken case is non-8KB base page size.

Also noticed that flush_tlb_all() is not referenced anywhere, only
the internal __flush_tlb_all() (local cpu only) is used by the
sparc64 port, so we can get rid of flush_tlb_all().

The kernel gets it's own 8KB TSB (swapper_tsb) and each address space
gets it's own private 8K TSB.  Later we can add code to dynamically
increase the size of per-process TSB as the RSS grows.  An 8KB TSB is
good enough for up to about a 4MB RSS, after which the TSB starts to
incur many capacity and conflict misses.

We even accumulate OBP translations into the kernel TSB.

Another area for refinement is large page size support.  We could use
a secondary address space TSB to handle those.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:13 -08:00
Bernhard R Link
94bbc1763b [SPARC64]: fix sparc_floppy_irq's auxio_register reseting
The patch "[SPARC64]: Get rid of fast IRQ feature"
moved the the code from arch/sparc64/kernel/entry.S:
      lduba           [%g7] ASI_PHYS_BYPASS_EC_E, %g5
      or              %g5, AUXIO_AUX1_FTCNT, %g5
      stba            %g5, [%g7] ASI_PHYS_BYPASS_EC_E
      andn            %g5, AUXIO_AUX1_FTCNT, %g5
      stba            %g5, [%g7] ASI_PHYS_BYPASS_EC_E
to arch/sparc64/kernel/irq.c:
              val = readb(auxio_register);
              val |= AUXIO_AUX1_FTCNT;
              writeb(val, auxio_register);
              val &= AUXIO_AUX1_FTCNT;
              writeb(val, auxio_register);
This looks like it it missing a bitwise not, which is reintroduced
by this patch.

Due to lack of a floppy device, I could not test it, but it looks
evident.

Signed-off-by: Bernhard R Link <brlink@debian.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:10:34 -08:00
David S. Miller
4d000d5b96 [SPARC64]: Mark __ex_table section correctly.
We must use the "a" (allocate) attribute every time we
emit an entry into the __ex_table section.

For consistency, use "a" instead of #alloc which is some
Solaris compat cruft GNU as provides on Sparc.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-04 23:23:56 -08:00
Linus Torvalds
13f939b5d3 Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6 2006-02-26 20:27:11 -08:00
Linus Torvalds
add2b6fdae Make Kprobes depend on modules
Commit 9ec4b1f356 made kprobes not compile
without module support, so just make that clear in the Kconfig file.

Also, since it's marked EXPERIMENTAL, make that dependency explicit too.

Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-26 20:24:40 -08:00
David S. Miller
7abea92145 [SPARC64]: Make cpu_present_map available earlier.
The change to kernel/sched.c's init code to use for_each_cpu()
requires that the cpu_possible_map be setup much earlier.

Set it up via setup_arch(), constrained to NR_CPUS, and later
constrain it to max_cpus in smp_prepare_cpus().

This fixes SMP booting on sparc64.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-26 19:36:00 -08:00
David S. Miller
40ad7a6afc [SPARC]: sys_newfstatat --> sys_fstatat64
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-12 23:30:11 -08:00
Heiko Carstens
642fe301c3 [SPARC64]: Fix sys_newfstatat syscall table entry for 64-bit.
The sparc64 64 bit syscall table seems to be broken as it has
compat_sys_newfstatat in its syscall table instead of sys_newfstatat.

Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-09 15:09:15 -08:00
David S. Miller
0fc9b55606 [SPARC64]: Update defconfig.
Do not enable CONFIG_LOCALVERSION_AUTO by default.
When doing kernel development it just leaves a ton
of crap around.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-07 18:12:34 -08:00
David S. Miller
1b9a428901 [SPARC]: Wire up sys_unshare().
Also, the Solaris syscall table is sized differrently,
and does not go beyond entry 255, so trim off the excess
entries.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-07 18:11:24 -08:00
David S. Miller
7f7ff6bf02 [SPARC64]: Update defconfig.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-05 00:15:12 -08:00
David S. Miller
3794689dba [SPARC64]: Add .gitignore file for sparc64 boot images.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-05 00:15:11 -08:00
David S. Miller
cddfc12e25 [SPARC64]: Kill compat_sys_clock_settime sign extension stub.
It's wrong and totally unneeded.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-30 01:31:09 -08:00
David S. Miller
4415863773 [SPARC]: Increase NR_SYSCALLS to 299
To let new syscalls through.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-22 12:12:01 -08:00
David S. Miller
3ee68c4af3 [SPARC64]: Use compat_sys_futimesat in 32-bit syscall table.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-20 01:49:15 -08:00
David S. Miller
2d7d5f0511 [SPARC]: Add support for *at(), ppoll, and pselect syscalls.
This also includes by necessity _TIF_RESTORE_SIGMASK support,
which actually resulted in a lot of cleanups.

The sparc signal handling code is quite a mess and I should
clean it up some day.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-19 02:42:49 -08:00
Ulrich Drepper
5590ff0d55 [PATCH] vfs: *at functions: core
Here is a series of patches which introduce in total 13 new system calls
which take a file descriptor/filename pair instead of a single file
name.  These functions, openat etc, have been discussed on numerous
occasions.  They are needed to implement race-free filesystem traversal,
they are necessary to implement a virtual per-thread current working
directory (think multi-threaded backup software), etc.

We have in glibc today implementations of the interfaces which use the
/proc/self/fd magic.  But this code is rather expensive.  Here are some
results (similar to what Jim Meyering posted before).

The test creates a deep directory hierarchy on a tmpfs filesystem.  Then
rm -fr is used to remove all directories.  Without syscall support I get
this:

real    0m31.921s
user    0m0.688s
sys     0m31.234s

With syscall support the results are much better:

real    0m20.699s
user    0m0.536s
sys     0m20.149s

The interfaces are for obvious reasons currently not much used.  But they'll
be used.  coreutils (and Jeff's posixutils) are already using them.
Furthermore, code like ftw/fts in libc (maybe even glob) will also start using
them.  I expect a patch to make follow soon.  Every program which is walking
the filesystem tree will benefit.

Signed-off-by: Ulrich Drepper <drepper@redhat.com>
Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Al Viro <viro@ftp.linux.org.uk>
Acked-by: Ingo Molnar <mingo@elte.hu>
Cc: Michael Kerrisk <mtk-manpages@gmx.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-18 19:20:29 -08:00
Linus Torvalds
3da38566df Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6 2006-01-18 15:08:02 -08:00
David S. Miller
959a85ada5 [SPARC64]: Fix build with CONFIG_COMPAT disabled.
Based upon a report and preliminary patch from Jim Gifford.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-18 14:58:05 -08:00
Eddie C. Dost
c126cf80d4 [SPARC64]: Serial Console for E250 Patch
From: Eddie C. Dost <ecd@brainaid.de>

I have the following patch for serial console over the RSC
(remote system controller) on my E250 machine. It basically adds
support for input-device=rsc and output-device=rsc from OBP, and
allows 115200,8,n,1,- serial mode setting.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-18 14:54:31 -08:00
David S. Miller
c07a8475dd [SPARC64]: Update defconfig.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-18 13:41:36 -08:00
Jesse Brandeburg
35ec56bb78 [PATCH] e1000: Added disable packet split capability
Adds the ability to disability packet split at compile time and use the legacy receive path on PCI express hardware.  Made this a CONFIG option and modified the Kconfig, to reflect the new option.

Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: John Ronciak <john.ronciak@intel.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2006-01-18 16:17:57 -05:00
Richard Mortimer
9eb3394bf2 [SPARC64]: Eliminate race condition reading Hummingbird STICK register
Ensure a consistent value is read from the STICK register by ensuring
that both high and low are read without high changing due to a roll
over of the low register.

Various Debian/SPARC users (myself include) have noticed problems with
Hummingbird based systems. The symptoms are that the system time is
seen to jump forward 3 days, 6 hours, 11 minutes give or take a few
seconds. In many cases the system then hangs some time afterwards.

I've spotted a race condition in the code to read the STICK register.
I could not work out why 3d, 6h, 11m is important but guess that it is
due to the 2^32 jump of STICK (forwards on one read and then the next
read will seem to be backwards) during a timer interrupt. I'm guessing
that a change of -2^32 will get converted to a large unsigned
increment after the arithmetic manipulation between STICK,
nanoseconds, jiffies etc.

I did a test where I modified __hbird_read_stick to artificially
inject rollover faults forcefully every few seconds. With this I saw
the clock jump over 6 times in 12 hours compared to once every month
or so.

Signed-off-by: Richard Mortimer <richm@oldelvet.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-17 15:21:01 -08:00
Al Viro
26ecbdea4b [PATCH] sparc64: task_pt_regs()
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-12 09:08:52 -08:00
Al Viro
ee3eea165e [PATCH] sparc64: task_stack_page()
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-12 09:08:52 -08:00
Al Viro
f3169641c1 [PATCH] sparc64: task_thread_info()
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-12 09:08:52 -08:00
Randy Dunlap
a941564458 [PATCH] capable/capability.h (arch/)
arch: Use <linux/capability.h> where capable() is used.

Signed-off-by: Randy Dunlap <rdunlap@xenotime.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-11 18:42:14 -08:00
Keshavamurthy Anil S
eb3a72921c [PATCH] kprobes: fix race in recovery of reentrant probe
There is a window where a probe gets removed right after the probe is hit
on some different cpu.  In this case probe handlers can't find a matching
probe instance related to break address.  In this case we need to read the
original instruction at break address to see if that is not a break/int3
instruction and recover safely.

Previous code had a bug where we were not checking for the above race in
case of reentrant probes and the below patch fixes this race.

Tested on IA64, Powerpc, x86_64.

Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-11 18:42:12 -08:00
Adrian Bunk
61943c5015 [SPARC64] arch/sparc64/Kconfig: fix HUGETLB_PAGE_SIZE_64K dependencies
This patch fixes a typo in the dependencies of HUGETLB_PAGE_SIZE_64K.

It might be more logical to rename the HUGETLB_PAGE_SIZE_*K
dependencies to HUGETLB_PAGE_SIZE_*KB, but let's fix this bug first.

This bug was reported by Jean-Luc Leger <reiga@dspnet.fr.eu.org>.

Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-11 15:55:23 -08:00
Linus Torvalds
dd49f96777 Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6 2006-01-10 08:28:53 -08:00
Anil S Keshavamurthy
e597c2984c [PATCH] kprobes: arch_remove_kprobe
Currently arch_remove_kprobes() is only implemented/required for x86_64 and
powerpc.  All other architecture like IA64, i386 and sparc64 implementes a
dummy function which is being called from arch independent kprobes.c file.

This patch removes the dummy functions and replaces it with
#define arch_remove_kprobe(p, s)	do { } while(0)

Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-10 08:01:40 -08:00
Anil S Keshavamurthy
49a2a1b83b [PATCH] kprobes: changed from using spinlock to mutex
Since Kprobes runtime exception handlers is now lock free as this code path is
now using RCU to walk through the list, there is no need for the
register/unregister{_kprobe} to use spin_{lock/unlock}_isr{save/restore}.  The
serialization during registration/unregistration is now possible using just a
mutex.

In the above process, this patch also fixes a minor memory leak for x86_64 and
powerpc.

Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-10 08:01:40 -08:00
Christoph Hellwig
e6a6d2efcb [PATCH] sanitize building of fs/compat_ioctl.c
Now that all these entries in the arch ioctl32.c files are gone [1], we can
build fs/compat_ioctl.c as a normal object and kill tons of cruft.  We need a
special do_ioctl32_pointer handler for s390 so the compat_ptr call is done.
This is not needed but harmless on all other architectures.  Also remove some
superflous includes in fs/compat_ioctl.c

Tested on ppc64.

[1] parisc still had it's PPP handler left, which is not fully correct
    for ppp and besides that ppp uses the generic SIOCPRIV ioctl so it'd
    kick in for all netdevice users.  We can introduce a proper handler
    in one of the next patch series by adding a compat_ioctl method to
    struct net_device but for now let's just kill it - parisc doesn't
    compile in mainline anyway and I don't want this to block this
    patchset.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Cc: Matthew Wilcox <willy@debian.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-10 08:01:33 -08:00
Christoph Hellwig
3a0f69d59b [PATCH] common compat_sys_timer_create
The comment in compat.c is wrong, every architecture provides a
get_compat_sigevent() for the IPC compat code already.

This basically moves the x86_64 version to common code and removes all the
others.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Paul Mackerras <paulus@samba.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Acked-by: Andi Kleen <ak@muc.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-10 08:01:32 -08:00
akpm@osdl.org
df2e71fb91 [PATCH] dump_thread() cleanup
)

From: Adrian Bunk <bunk@stusta.de>

- create one common dump_thread() prototype in kernel.h

- dump_thread() is only used in fs/binfmt_aout.c and can therefore be
  removed on all architectures where CONFIG_BINFMT_AOUT is not
  available

Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-10 08:01:25 -08:00
David S. Miller
cdade109d3 [SPARC64]: Fix sys_fstat64() entry in 64-bit syscall table.
Noticed by Jakub Jelinek.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-09 20:43:57 -08:00
Linus Torvalds
977127174a Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6 2006-01-09 18:41:42 -08:00
David S. Miller
3ebc284d52 [SPARC64]: Update defconfig.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-09 14:36:49 -08:00
Richard Mortimer
695ca07bf1 [SPARC64]: Fix ptrace/strace
Don't clobber register %l0 while checking TI_SYS_NOERROR value in
syscall return path.  This bug was introduced by:

db7d9a4eb7

Problem narrowed down by Luis F. Ortiz and Richard Mortimer.

I tried using %l2 as suggested by Luis and that works for me.

Looking at the code I wonder if it makes sense to simplify the code
a little bit. The following works for me but I'm not sure how to
exercise the "NOERROR" codepath.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-09 14:35:50 -08:00
David S. Miller
90bf811664 [SPARC64]: Add needed pm_power_off symbol.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-09 14:12:50 -08:00
Jiri Slaby
d08fa1a22e [PATCH] PCI: pci_find_device remove (sparc64/kernel/ebus.c)
Signed-off-by: Jiri Slaby <xslaby@fi.muni.cz>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-01-09 12:13:15 -08:00
Matt Mackall
e585e47031 [PATCH] tiny: Make *[ug]id16 support optional
Configurable 16-bit UID and friends support

This allows turning off the legacy 16 bit UID interfaces on embedded platforms.

   text    data     bss     dec     hex filename
3330172  529036  190556 4049764  3dcb64 vmlinux-baseline
3328268  529040  190556 4047864  3dc3f8 vmlinux

From: Adrian Bunk <bunk@stusta.de>

    UID16 was accidentially disabled for !EMBEDDED.

Signed-off-by: Matt Mackall <mpm@selenic.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-08 20:14:11 -08:00
Christoph Hellwig
6b9c7ed848 [PATCH] use ptrace_get_task_struct in various places
The ptrace_get_task_struct() helper that I added as part of the ptrace
consolidation is useful in variety of places that currently opencode it.
Switch them to the common helpers.

Add a ptrace_traceme() helper that needs to be explicitly called, and simplify
the ptrace_get_task_struct() interface.  We don't need the request argument
now, and we return the task_struct directly, using ERR_PTR() for error
returns.  It's a bit more code in the callers, but we have two sane routines
that do one thing well now.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-08 20:13:51 -08:00
David S. Miller
d5784b57d2 [SPARC]: Use STABS_DEBUG and DWARF_DEBUG macros in vmlinux.lds.S
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-12-28 13:22:54 -08:00
David S. Miller
597d1f0622 [SPARC]: Kill CHILD_MAX.
It's definition is wrong (-1 means "no limit" not 999),
only the Sparc SunOS/Solaris compat code uses it, so
let's just kill it off completely from limits.h and
all referencing code.

Noticed by Ulrich Drepper.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-12-22 23:10:03 -08:00
Adrian Bunk
0b57ee9e55 [SPARC]: introduce a SPARC Kconfig symbol
Introduce a Kconfig symbol SPARC that is defined on both the sparc and
sparc64 architectures.

This symbol makes some dependencies more readable.

Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-12-22 23:09:54 -08:00
David S. Miller
a9c9dff1bc [SPARC64]: Stop putting -finline-limit=XXX into CFLAGS
It was a stupid workaround for the "static inline" vs.
"extern inline" issues of long ago, and it is what causes
schedule() to be inlined like crazy into kernel/sched.c
when -Os is specified.

MIPS and S390 should probably do the same.

Now CC_OPTIMIZE_FOR_SIZE can be safely used on sparc64
once more.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-12-20 14:53:05 -08:00
Keshavamurthy Anil S
bf8d5c52c3 [PATCH] kprobes: increment kprobe missed count for multiprobes
When multiple probes are registered at the same address and if due to some
recursion (probe getting triggered within a probe handler), we skip calling
pre_handlers and just increment nmissed field.

The below patch make sure it walks the list for multiple probes case.
Without the below patch we get incorrect results of nmissed count for
multiple probe case.

Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-12-12 08:57:45 -08:00
David S. Miller
cab3f16feb [SPARC64]: Fix >8K I/O mappings.
Increment the PFN field of the PTE so that the tests
on vm_pfn in mm/memory.c match up.  The TLB ignores these
lower bits for larger page sizes, so it's OK to set things
like this.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-29 13:59:03 -08:00
David S. Miller
5cd9194a1b [PATCH] sparc: convert IO remapping to VM_PFNMAP
Here are the Sparc bits.

Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-28 14:35:36 -08:00
Hugh Dickins
f3d48f0373 [PATCH] unpaged: fix sound Bad page states
Earlier I unifdefed PageCompound, so that snd_pcm_mmap_control_nopage and
others can give out a 0-order component of a higher-order page, which won't
be mistakenly freed when zap_pte_range unmaps it.  But many Bad page states
reported a PG_reserved was freed after all: I had missed that we need to
say __GFP_COMP to get compound page behaviour.

Some of these higher-order pages are allocated by snd_malloc_pages, some by
snd_malloc_dev_pages; or if SBUS, by sbus_alloc_consistent - but that has
no gfp arg, so add __GFP_COMP into its sparc32/64 implementations.

I'm still rather puzzled that DRM seems not to need a similar change.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-22 09:13:43 -08:00
Hugh Dickins
0b14c179a4 [PATCH] unpaged: VM_UNPAGED
Although we tend to associate VM_RESERVED with remap_pfn_range, quite a few
drivers set VM_RESERVED on areas which are then populated by nopage.  The
PageReserved removal in 2.6.15-rc1 changed VM_RESERVED not to free pages in
zap_pte_range, without changing those drivers not to set it: so their pages
just leak away.

Let's not change miscellaneous drivers now: introduce VM_UNPAGED at the core,
to flag the special areas where the ptes may have no struct page, or if they
have then it's not to be touched.  Replace most instances of VM_RESERVED in
core mm by VM_UNPAGED.  Force it on in remap_pfn_range, and the sparc and
sparc64 io_remap_pfn_range.

Revert addition of VM_RESERVED to powerpc vdso, it's not needed there.  Is it
needed anywhere?  It still governs the mm->reserved_vm statistic, and special
vmas not to be merged, and areas not to be core dumped; but could probably be
eliminated later (the drivers are probably specifying it because in 2.4 it
kept swapout off the vma, but in 2.6 we work from the LRU, which these pages
don't get on).

Use the VM_SHM slot for VM_UNPAGED, and define VM_SHM to 0: it serves no
purpose whatsoever, and should be removed from drivers when we clean up.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Acked-by: William Irwin <wli@holomorphy.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-22 09:13:42 -08:00
Christoph Hellwig
9ffb83bcc5 [SBUSFB]: implement ->compat_ioctl
This patch adds a new function, sbusfb_compat_ioctl() to
drivers/video/sbuslib.c and uses it as compat_ioctl in all sbus fb
drivers

This remove the last per-arch compat ioctl bits in
arch/sparc64/kernel/ioctl32.c so it would be nice if people could test
if this actually copiles and works and if yes apply it :)

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-12 12:11:12 -08:00
David S. Miller
4d45cbacb8 [SPARC64]: Restore 2.4.x /proc/cpuinfo behavior for "ncpus probed" field.
Noticed by Tom 'spot' Callaway.

Even on uniprocessor we always reported the number of physical
cpus in the system via /proc/cpuinfo.  But when this got changed
to use num_possible_cpus() it always reads as "1" on uniprocessor.
This change was unintentional.

So scan the firmware device tree and count the number of cpu
nodes, and report that, as we always did.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-11 12:48:56 -08:00
Christoph Hellwig
8ca2bdc7a9 [SPARC] sbus rtc: implement ->compat_ioctl
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-09 12:07:18 -08:00
Tobias Klauser
84c1a13a30 [SPARC64]: Use ARRAY_SIZE macro
Use ARRAY_SIZE macro instead of sizeof(x)/sizeof(x[0]) and remove a
duplicate of ARRAY_SIZE which is never used anyways.

Signed-off-by: Tobias Klauser <tklauser@nuerscht.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-09 12:03:42 -08:00
Nick Piggin
64c7c8f885 [PATCH] sched: resched and cpu_idle rework
Make some changes to the NEED_RESCHED and POLLING_NRFLAG to reduce
confusion, and make their semantics rigid.  Improves efficiency of
resched_task and some cpu_idle routines.

* In resched_task:
- TIF_NEED_RESCHED is only cleared with the task's runqueue lock held,
  and as we hold it during resched_task, then there is no need for an
  atomic test and set there. The only other time this should be set is
  when the task's quantum expires, in the timer interrupt - this is
  protected against because the rq lock is irq-safe.

- If TIF_NEED_RESCHED is set, then we don't need to do anything. It
  won't get unset until the task get's schedule()d off.

- If we are running on the same CPU as the task we resched, then set
  TIF_NEED_RESCHED and no further action is required.

- If we are running on another CPU, and TIF_POLLING_NRFLAG is *not* set
  after TIF_NEED_RESCHED has been set, then we need to send an IPI.

Using these rules, we are able to remove the test and set operation in
resched_task, and make clear the previously vague semantics of
POLLING_NRFLAG.

* In idle routines:
- Enter cpu_idle with preempt disabled. When the need_resched() condition
  becomes true, explicitly call schedule(). This makes things a bit clearer
  (IMO), but haven't updated all architectures yet.

- Many do a test and clear of TIF_NEED_RESCHED for some reason. According
  to the resched_task rules, this isn't needed (and actually breaks the
  assumption that TIF_NEED_RESCHED is only cleared with the runqueue lock
  held). So remove that. Generally one less locked memory op when switching
  to the idle thread.

- Many idle routines clear TIF_POLLING_NRFLAG, and only set it in the inner
  most polling idle loops. The above resched_task semantics allow it to be
  set until before the last time need_resched() is checked before going into
  a halt requiring interrupt wakeup.

  Many idle routines simply never enter such a halt, and so POLLING_NRFLAG
  can be always left set, completely eliminating resched IPIs when rescheduling
  the idle task.

  POLLING_NRFLAG width can be increased, to reduce the chance of resched IPIs.

Signed-off-by: Nick Piggin <npiggin@suse.de>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Con Kolivas <kernel@kolivas.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-09 07:56:33 -08:00
Nick Piggin
5bfb5d690f [PATCH] sched: disable preempt in idle tasks
Run idle threads with preempt disabled.

Also corrected a bugs in arm26's cpu_idle (make it actually call schedule()).
How did it ever work before?

Might fix the CPU hotplugging hang which Nigel Cunningham noted.

We think the bug hits if the idle thread is preempted after checking
need_resched() and before going to sleep, then the CPU offlined.

After calling stop_machine_run, the CPU eventually returns from preemption and
into the idle thread and goes to sleep.  The CPU will continue executing
previous idle and have no chance to call play_dead.

By disabling preemption until we are ready to explicitly schedule, this bug is
fixed and the idle threads generally become more robust.

From: alexs <ashepard@u.washington.edu>

  PPC build fix

From: Yoichi Yuasa <yuasa@hh.iij4u.or.jp>

  MIPS build fix

Signed-off-by: Nick Piggin <npiggin@suse.de>
Signed-off-by: Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-09 07:56:33 -08:00
Christoph Hellwig
7e4c54a2a4 [PATCH] remove ioctl32_handler_t
Some architectures define and use this type in their compat_ioctl code, but
all of them can easily use the identical ioctl_trans_handler_t type that is
defined in common code.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Cc: Andi Kleen <ak@muc.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-09 07:56:00 -08:00
Hugh Dickins
da1605465e [SPARC64] mm: update get_user_insn comment
Update comment on get_user_insn to the more general "pte lock", which may
or may not be the page_table_lock.  Note vmtruncate handled like kswapd.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-08 10:00:55 -08:00
David S. Miller
dd3e2dcf34 [SPARC64]: Kill some unnecessary includes from ioctl32.c
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-07 14:13:46 -08:00
Christoph Hellwig
f48497e383 [SPARC64]: remove drm compat ioctl handling
drivers/drm/ now implements proper ->compat_ioctl methods, so this isn't
needed anymore.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-07 14:13:27 -08:00
Christoph Hellwig
b66621fef3 [SPARC] cpwatchdog: implement ->compat_ioctl
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-07 14:13:14 -08:00
Christoph Hellwig
1d5d00bd9c [SPARC] display7seg: implement ->unlocked_ioctl and ->compat_ioctl
all ioctls are 32bit compat clean, so the driver can use ->compat_ioctl
and ->unlocked_ioctl easily.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-07 14:13:01 -08:00
Christoph Hellwig
b31023fc24 [SPARC] openprom: implement ->compat_ioctl
implement a compat_ioctl handle in the driver instead of having table
entries in sparc64 ioctl32.c (I plan to get rid of the arch ioctl32.c
file eventually)

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-07 14:12:47 -08:00
Christoph Hellwig
1928f8e541 [SPARC] envctrl: implement ->unlocked_ioctl and ->compat_ioctl
all the ioctls in the driver are 32bit compat clean and don't need BKL,
so we can switch it to ->unlocked_ioctl and ->compat_ioctl trivially.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-07 14:12:34 -08:00
Christoph Hellwig
16cf0d8165 [SPARC]: Kill remaining kbio.h references.
Would you mind applying the following patch that kills those two + the
m68k and Documentation/ references?

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-07 14:12:21 -08:00
Christoph Hellwig
261b033afc [SPARC64]: remove duplicated compat ioctl entries
all these are handled by fs/compat_ioctls.c already.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-07 14:11:49 -08:00
Christoph Hellwig
59f85dc95e [SPARC]: remove vuid_event.h
I don't know if we ever implemented this, but the only user in any 2.6
tree are the compat ioctls.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-07 14:11:38 -08:00
Christoph Hellwig
e1413315b8 [SPARC]: remove kbio.h
The old keyboard driver is gone in 2.6, so the only user left are the
compat ioctls.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-07 14:11:25 -08:00
Christoph Hellwig
9d3c7d1bfd [SPARC]: remove audioio.h
The old sound drivers are gone in 2.6, so the only user left are the
compat ioctls.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-07 14:11:14 -08:00
Christoph Hellwig
e0436b3164 [SPARC64]: remove alloc_user_space()
this inline routine in arch/sparc64/kernel/ioctl32.c is completely
unused and superceeded by compat_alloc_user_space()

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-07 14:11:02 -08:00
David S. Miller
fc3214952f [SPARC64]: Kill off dummy_tick_ops.
It only serves to generate false-positive buildcheck warnings.
Just set it initially to tick_operations which uses the v9
%tick register which every sparc64 processor has.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-07 14:10:10 -08:00
David S. Miller
62dbec78be [SPARC64] mm: Do not flush TLB mm in tlb_finish_mmu()
It isn't needed any longer, as noted by Hugh Dickins.

We still need the flush routines, due to the one remaining
call site in hugetlb_prefault_arch_hook().  That can be
eliminated at some later point, however.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-07 14:09:58 -08:00
Hugh Dickins
dedeb0029b [SPARC64] mm: context switch ptlock
sparc64 is unique among architectures in taking the page_table_lock in
its context switch (well, cris does too, but erroneously, and it's not
yet SMP anyway).

This seems to be a private affair between switch_mm and activate_mm,
using page_table_lock as a per-mm lock, without any relation to its uses
elsewhere.  That's fine, but comment it as such; and unlock sooner in
switch_mm, more like in activate_mm (preemption is disabled here).

There is a block of "if (0)"ed code in smp_flush_tlb_pending which would
have liked to rely on the page_table_lock, in switch_mm and elsewhere;
but its comment explains how dup_mmap's flush_tlb_mm defeated it.  And
though that could have been changed at any time over the past few years,
now the chance vanishes as we push the page_table_lock downwards, and
perhaps split it per page table page.  Just delete that block of code.

Which leaves the mysterious spin_unlock_wait(&oldmm->page_table_lock)
in kernel/fork.c copy_mm.  Textual analysis (supported by Nick Piggin)
suggests that the comment was written by DaveM, and that it relates to
the defeated approach in the sparc64 smp_flush_tlb_pending.  Just delete
this block too.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-07 14:09:01 -08:00
Hugh Dickins
b8ae48656d [SPARC64] mm: don't re-evaluate *ptep
sparc64 prom_callback and new_setup_frame32 each operates on a user page
table without holding lock, and no doubt they've good reason.  But I'd
feel more confident if they were to do a "pte = *ptep" and then operate
on pte, rather than re-evaluating *ptep.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-11-07 14:08:46 -08:00
Jesper Juhl
b2325fe1b7 [PATCH] kfree cleanup: arch
This is the arch/ part of the big kfree cleanup patch.

Remove pointless checks for NULL prior to calling kfree() in arch/.

Signed-off-by: Jesper Juhl <jesper.juhl@gmail.com>
Acked-by: Grant Grundler <grundler@parisc-linux.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-07 07:54:06 -08:00
Ananth N Mavinakayanahalli
d217d5450f [PATCH] Kprobes: preempt_disable/enable() simplification
Reorganize the preempt_disable/enable calls to eliminate the extra preempt
depth.  Changes based on Paul McKenney's review suggestions for the kprobes
RCU changeset.

Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-07 07:53:46 -08:00
Ananth N Mavinakayanahalli
991a51d83a [PATCH] Kprobes: Use RCU for (un)register synchronization - arch changes
Changes to the arch kprobes infrastructure to take advantage of the locking
changes introduced by usage of RCU for synchronization.  All handlers are now
run without any locks held, so they have to be re-entrant or provide their own
synchronization.

Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-07 07:53:46 -08:00
Ananth N Mavinakayanahalli
f215d985e9 [PATCH] Kprobes: Track kprobe on a per_cpu basis - sparc64 changes
Sparc64 changes to track kprobe execution on a per-cpu basis.  We now track
the kprobe state machine independently on each cpu using an arch specific
kprobe control block.

Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Cc: "David S. Miller" <davem@davemloft.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-07 07:53:46 -08:00
Ananth N Mavinakayanahalli
66ff2d0691 [PATCH] Kprobes: rearrange preempt_disable/enable() calls
The following set of patches are aimed at improving kprobes scalability.  We
currently serialize kprobe registration, unregistration and handler execution
using a single spinlock - kprobe_lock.

With these changes, kprobe handlers can run without any locks held.  It also
allows for simultaneous kprobe handler executions on different processors as
we now track kprobe execution on a per processor basis.  It is now necessary
that the handlers be re-entrant since handlers can run concurrently on
multiple processors.

All changes have been tested on i386, ia64, ppc64 and x86_64, while sparc64
has been compile tested only.

The patches can be viewed as 3 logical chunks:

patch 1: 	Reorder preempt_(dis/en)able calls
patches 2-7: 	Introduce per_cpu data areas to track kprobe execution
patches 8-9: 	Use RCU to synchronize kprobe (un)registration and handler
		execution.

Thanks to Maneesh Soni, James Keniston and Anil Keshavamurthy for their
review and suggestions. Thanks again to Anil, Hien Nguyen and Kevin Stafford
for testing the patches.

This patch:

Reorder preempt_disable/enable() calls in arch kprobes files in preparation to
introduce locking changes.  No functional changes introduced by this patch.

Signed-off-by: Ananth N Mavinakayahanalli <ananth@in.ibm.com>
Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-07 07:53:45 -08:00
Prasanna S Panchamukhi
cd6b0762a0 [PATCH] Move Kprobes and Oprofile to "Instrumentation Support" menu
Andrew Morton suggested to move kprobes from kernel hacking menu, since
kernel hacking menu is in-appropriate for the Kprobes.  This patch moves
Kprobes and Oprofile under instrumentation menu.

(akpm: it's not a natural fit, but things like djprobes and the s390 guys'
statistics library need a home)

Signed-of-by: Prasanna S Panchamukhi <prasanna@in.ibm.com>
Cc: Philippe Elie <phil.el@wanadoo.fr>
Cc: John Levon <levon@movementarian.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-07 07:53:35 -08:00
Thomas Gleixner
ecea8d19c9 [PATCH] jiffies_64 cleanup
Define jiffies_64 in kernel/timer.c rather than having 24 duplicated
defines in each architecture.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-30 17:37:25 -08:00
Christoph Hellwig
9c0cbd54ce [PATCH] TIOC* compat ioctl handling
TIOCSTART and TIOCSTOP are defined in asm/ioctls.h and asm/termios.h by
various architectures but not actually implemented anywhere but in the IRIX
compatibility layer, so remove their COMPATIBLE_IOCTL from parisc, ppc64
and sparc64.

Move the TIOCSLTC COMPATIBLE_IOCTL to common code, guided by an ifdef to
only show up on architectures that support it (same as the code handling it
in tty_ioctl.c), aswell as it's brother TIOCGLTC that wasn't handled so
far.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-30 17:37:17 -08:00
Hugh Dickins
b462705ac6 [PATCH] mm: arches skip ptlock
Convert those few architectures which are calling pud_alloc, pmd_alloc,
pte_alloc_map on a user mm, not to take the page_table_lock first, nor drop it
after.  Each of these can continue to use pte_alloc_map, no need to change
over to pte_alloc_map_lock, they're neither racy nor swappable.

In the sparc64 io_remap_pfn_range, flush_tlb_range then falls outside of the
page_table_lock: that's okay, on sparc64 it's like flush_tlb_mm, and that has
always been called from outside of page_table_lock in dup_mmap.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29 21:40:40 -07:00
Nick Piggin
b5810039a5 [PATCH] core remove PageReserved
Remove PageReserved() calls from core code by tightening VM_RESERVED
handling in mm/ to cover PageReserved functionality.

PageReserved special casing is removed from get_page and put_page.

All setting and clearing of PageReserved is retained, and it is now flagged
in the page_alloc checks to help ensure we don't introduce any refcount
based freeing of Reserved pages.

MAP_PRIVATE, PROT_WRITE of VM_RESERVED regions is tentatively being
deprecated.  We never completely handled it correctly anyway, and is be
reintroduced in future if required (Hugh has a proof of concept).

Once PageReserved() calls are removed from kernel/power/swsusp.c, and all
arch/ and driver code, the Set and Clear calls, and the PG_reserved bit can
be trivially removed.

Last real user of PageReserved is swsusp, which uses PageReserved to
determine whether a struct page points to valid memory or not.  This still
needs to be addressed (a generic page_is_ram() should work).

A last caveat: the ZERO_PAGE is now refcounted and managed with rmap (and
thus mapcounted and count towards shared rss).  These writes to the struct
page could cause excessive cacheline bouncing on big systems.  There are a
number of ways this could be addressed if it is an issue.

Signed-off-by: Nick Piggin <npiggin@suse.de>

Refcount bug fix for filemap_xip.c

Signed-off-by: Carsten Otte <cotte@de.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29 21:40:39 -07:00
Hugh Dickins
404351e67a [PATCH] mm: mm_init set_mm_counters
How is anon_rss initialized?  In dup_mmap, and by mm_alloc's memset; but
that's not so good if an mm_counter_t is a special type.  And how is rss
initialized?  By set_mm_counter, all over the place.  Come on, we just need to
initialize them both at once by set_mm_counter in mm_init (which follows the
memcpy when forking).

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29 21:40:38 -07:00
Hugh Dickins
fc2acab31b [PATCH] mm: tlb_finish_mmu forget rss
zap_pte_range has been counting the pages it frees in tlb->freed, then
tlb_finish_mmu has used that to update the mm's rss.  That got stranger when I
added anon_rss, yet updated it by a different route; and stranger when rss and
anon_rss became mm_counters with special access macros.  And it would no
longer be viable if we're relying on page_table_lock to stabilize the
mm_counter, but calling tlb_finish_mmu outside that lock.

Remove the mmu_gather's freed field, let tlb_finish_mmu stick to its own
business, just decrement the rss mm_counter in zap_pte_range (yes, there was
some point to batching the update, and a subsequent patch restores that).  And
forget the anal paranoia of first reading the counter to avoid going negative
- if rss does go negative, just fix that bug.

Remove the mmu_gather's flushes and avoided_flushes from arm and arm26: no use
was being made of them.  But arm26 alone was actually using the freed, in the
way some others use need_flush: give it a need_flush.  arm26 seems to prefer
spaces to tabs here: respect that.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29 21:40:37 -07:00
Hugh Dickins
4d6ddfa924 [PATCH] mm: tlb_is_full_mm was obscure
tlb_is_full_mm?  What does that mean?  The TLB is full?  No, it means that the
mm's last user has gone and the whole mm is being torn down.  And it's an
inline function because sparc64 uses a different (slightly better)
"tlb_frozen" name for the flag others call "fullmm".

And now the ptep_get_and_clear_full macro used in zap_pte_range refers
directly to tlb->fullmm, which would be wrong for sparc64.  Rather than
correct that, I'd prefer to scrap tlb_is_full_mm altogether, and change
sparc64 to just use the same poor name as everyone else - is that okay?

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29 21:40:37 -07:00
Al Viro
53f9fc93f9 [PATCH] gfp_t: remaining bits of arch/*
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-28 08:16:51 -07:00
David S. Miller
b4d1b82578 [SPARC64]: Fix powering off on SMP.
Doing a "SUNW,stop-self" firmware call on the other cpus is not the
correct thing to do when dropping into the firmware for a halt,
reboot, or power-off.

For now, just do nothing to quiet the other cpus, as the system should
be quiescent enough.  Later we may decide to implement smp_send_stop()
like the other SMP platforms do.

Based upon a report from Christopher Zimmermann.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-10-14 15:26:08 -07:00
David S. Miller
688cb30bdc [SPARC64]: Eliminate PCI IOMMU dma mapping size limit.
The hairy fast allocator in the sparc64 PCI IOMMU code
has a hard limit of 256 pages.  Certain devices can
exceed this when performing very large I/Os.

So replace with a more simple allocator, based largely
upon the arch/ppc64/kernel/iommu.c code.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-10-13 22:15:24 -07:00
David S. Miller
51e8513615 [SPARC64]: Consolidate common PCI IOMMU init code.
All the PCI controller drivers were doing the same thing
setting up the IOMMU software state, put it all in one spot.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-10-13 21:10:08 -07:00
David S. Miller
c9c1083074 [SPARC64]: Fix boot failures on SunBlade-150
The sequence to move over to the Linux trap tables from
the firmware ones needs to be more air tight.  It turns
out that to be %100 safe we do need to be able to translate
OBP mappings in our TLB miss handlers early.

In order not to eat up a lot of kernel image memory with
static page tables, just use the translations array in
the OBP TLB miss handlers.  That solves the bulk of the
problem.

Furthermore, to make sure the OBP TLB miss path will work
even before the fixed MMU globals are loaded, explicitly
load %g1 to TLB_SFSR at the beginning of the i-TLB and
d-TLB miss handlers.

To ease the OBP TLB miss walking of the prom_trans[] array,
we sort it then delete all of the non-OBP entries in there
(for example, there are entries for the kernel image itself
which we're not interested in at all).

We also save about 32K of kernel image size with this change.
Not a bad side effect :-)

There are still some reasons why trampoline.S can't use the
setup_trap_table() yet.  The most noteworthy are:

1) OBP boots secondary processors with non-bias'd stack for
   some reason.  This is easily fixed by using a small bootup
   stack in the kernel image explicitly for this purpose.

2) Doing a firmware call via the normal C call prom_set_trap_table()
   goes through the whole OBP enter/exit sequence that saves and
   restores OBP and Linux kernel state in the MMUs.  This path
   unfortunately does a "flush %g6" while loading up the OBP locked
   TLB entries for the firmware call.

   If we setup the %g6 in the trampoline.S code properly, that
   is in the PAGE_OFFSET linear mapping, but we're not on the
   kernel trap table yet so those addresses won't translate properly.

   One idea is to do a by-hand firmware call like we do in the
   early bootup code and elsewhere here in trampoline.S  But this
   fails as well, as aparently the secondary processors are not
   booted with OBP's special locked TLB entries loaded.  These
   are necessary for the firwmare to processes TLB misses correctly
   up until the point where we take over the trap table.

This does need to be resolved at some point.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-10-12 12:22:46 -07:00
David S. Miller
b1b510aa28 [SPARC64]: Fix net booting on Ultra5
We were not doing alignment properly when remapping the kernel image.

What we want is a 4MB aligned physical address to map at KERNBASE.
Mistakedly we were 4MB aligning the virtual address where the kernel
initially sits, that's wrong.

Instead, we should PAGE align the virtual address, then 4MB align the
physical address result the prom gives to us.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-10-11 15:45:16 -07:00
David S. Miller
5d8e1b181c [SPARC64]: Fix Ultra5, Ultra60, et al. boot failures.
On the boot processor, we need to do the move onto the Linux trap
table a little bit differently else we'll take unhandlable faults in
the firmware address space.

Previously we would do the following:

1) Disable PSTATE_IE in %pstate.
2) Set %tba by hand to sparc64_ttable_tl0
3) Initialize alternate, mmu, and interrupt global
   trap registers.
4) Call prom_set_traptable()

That doesn't work very well actually with the way we boot the kernel
VM these days.  It worked by luck on many systems because the firmware
accesses for the prom_set_traptable() call happened to be loaded into
the TLB already, something we cannot assume.

So the new scheme is this:

1) Clear PSTATE_IE in %pstate and set %pil to 15
2) Call prom_set_traptable()
3) Initialize alternate, mmu, and interrupt global
   trap registers.

and this works quite well.  This sequence has been moved into a
callable function in assembler named setup-trap_table().  The idea is
that eventually trampoline.S can use this code as well.  That isn't
possible currently due to some complications, but eventually we should
be able to do it.

Thanks to Meelis Roos for the Ultra5 boot failure report.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-10-10 16:12:13 -07:00
Sven Hartge
2e457ef667 [SPARC64]: Fix compile error in irq.c
irq.c is missing the inclusion of asm/io.h, which causes
readb() and writeb() the be undefined.

Signed-off-by: Sven Hartge <hartge@ds9.argh.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-10-08 21:12:04 -07:00
David S. Miller
ba6399334d [SPARC64]: Fix userland FPU state corruption.
We need to use stricter memory barriers around the block
load and store instructions we use to save and restore the
FPU register file.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-10-07 13:30:49 -07:00
David S. Miller
2256c13b99 [SPARC64]: Probe for power device on ISA bus too.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-10-06 20:43:54 -07:00
David S. Miller
9ad98c5b44 [SPARC64]: Fix initrd when net booting.
By allocating early memory for the firmware page tables, we
can write over the beginning of the initrd image.

So what we do now is:

1) Read in firmware translations table while still on the
   firmware's trap table.
2) Switch to Linux trap table.
3) Init bootmem.
4) Build firmware page tables using __alloc_bootmem().

And this keeps the initrd from being clobbered.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-10-05 15:12:00 -07:00
David S. Miller
0835ae0f27 [SPARC64]: Replace cheetah+ code patching with variables.
Instead of code patching to handle the page size fields in
the context registers, just use variables from which we get
the proper values.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-10-04 15:23:20 -07:00
David S. Miller
717463d806 [SPARC64]: Fix several bugs in flush_ptrace_access().
1) Use cpudata cache line sizes, not magic constants.
2) Align start address in cheetah case so we do not get
   unaligned address traps.  (pgrep was good at triggering
   this, via /proc/${pid}/cmdline accesses)

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-29 18:50:34 -07:00
David S. Miller
4cb29d1812 [SPARC64]: Kill arch/sparc64/prom/memory.c
No longer used.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-29 18:05:28 -07:00
David S. Miller
13edad7a5c [SPARC64]: Rewrite convoluted physical memory probing.
Delete all of the code working with sp_banks[] and replace
with clean acquisition and sorting of physical memory
parameters from the firmware.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-29 17:58:26 -07:00
David S. Miller
ed3ffaf7b5 [SPARC64]: Solidify check in cheetah_check_main_memory().
Need to make sure the address is below high_memory before
passing it to kern_addr_valid().

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-28 21:48:25 -07:00
David S. Miller
10147570f9 [SPARC64]: Kill all external references to sp_banks[]
Thus, we can mark sp_banks[] static in arch/sparc64/mm/init.c

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-28 21:46:43 -07:00
David S. Miller
0836a0eb40 [SPARC64]: Move phys_base, kern_{base,size}, and sp_banks[] init to paging_init
Also, move prom_probe_memory() into arch/sparc64/mm/init.c

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-28 21:38:08 -07:00
David S. Miller
801ab3c731 [SPARC]: Declare paging_init() in asm/pgtable.h
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-28 21:31:25 -07:00
David S. Miller
efdc1e2083 [SPARC64]: Simplify user fault fixup handling.
Instead of doing byte-at-a-time user accesses to figure
out where the fault occurred, read the saved fault_address
from the current thread structure.

For the sake of defensive programming, if the fault_address
does not fall into the user buffer range, simply assume the
whole area faulted.  This will cause the fixup for
copy_from_user() to clear the entire kernel side buffer.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-28 21:06:47 -07:00
David S. Miller
5fd29752f0 [SPARC64]: Fix fault handling in unaligned trap handler.
We were not calling kernel_mna_trap_fault() correctly.
Instead of being fancy, just return 0 vs. -EFAULT from
the assembler stubs, and handle that return value as
appropriate.

Create an "__retl_efault" stub for assembler exception
table entries and use it where possible.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-28 20:41:45 -07:00
David S. Miller
8cf14af0a7 [SPARC64]: Convert to use generic exception table support.
The funny "range" exception table entries we had were only
used by the compat layer socketcall assembly, and it wasn't
even needed there.

For free we now get proper exception table sorting and fast
binary searching.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-28 20:21:11 -07:00
David S. Miller
705747ab87 [SPARC64]: Fix bug in unaligned load endianness swapping
The in-memory value was being swapped, not the value we
loaded into the register.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-28 16:48:40 -07:00