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[SPARC64]: Fix some SUN4V TLB miss bugs.
Code patching did not sign extend negative branch offsets correctly. Kernel TLB miss path needs patching and %g4 register preservation in order to handle SUN4V correctly. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
parent
fd05068d7b
commit
459b6e621e
@ -48,7 +48,7 @@ kvmap_itlb_tsb_miss:
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kvmap_itlb_vmalloc_addr:
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KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_itlb_longpath)
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KTSB_LOCK_TAG(%g1, %g2, %g4)
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KTSB_LOCK_TAG(%g1, %g2, %g7)
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/* Load and check PTE. */
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ldxa [%g5] ASI_PHYS_USE_EC, %g5
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@ -60,8 +60,29 @@ kvmap_itlb_vmalloc_addr:
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/* fallthrough to TLB load */
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kvmap_itlb_load:
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stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Reload TLB
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661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
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retry
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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nop
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nop
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.previous
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/* For sun4v the ASI_ITLB_DATA_IN store and the retry
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* instruction get nop'd out and we get here to branch
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* to the sun4v tlb load code. The registers are setup
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* as follows:
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*
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* %g4: vaddr
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* %g5: PTE
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* %g6: TAG
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*
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* The sun4v TLB load wants the PTE in %g3 so we fix that
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* up here.
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*/
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ba,pt %xcc, sun4v_itlb_load
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mov %g5, %g3
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kvmap_itlb_longpath:
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@ -80,7 +101,7 @@ kvmap_itlb_longpath:
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kvmap_itlb_obp:
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OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_itlb_longpath)
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KTSB_LOCK_TAG(%g1, %g2, %g4)
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KTSB_LOCK_TAG(%g1, %g2, %g7)
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KTSB_WRITE(%g1, %g5, %g6)
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@ -90,7 +111,7 @@ kvmap_itlb_obp:
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kvmap_dtlb_obp:
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OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_dtlb_longpath)
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KTSB_LOCK_TAG(%g1, %g2, %g4)
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KTSB_LOCK_TAG(%g1, %g2, %g7)
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KTSB_WRITE(%g1, %g5, %g6)
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@ -129,7 +150,7 @@ kvmap_linear_patch:
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kvmap_dtlb_vmalloc_addr:
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KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_dtlb_longpath)
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KTSB_LOCK_TAG(%g1, %g2, %g4)
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KTSB_LOCK_TAG(%g1, %g2, %g7)
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/* Load and check PTE. */
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ldxa [%g5] ASI_PHYS_USE_EC, %g5
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@ -141,8 +162,29 @@ kvmap_dtlb_vmalloc_addr:
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/* fallthrough to TLB load */
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kvmap_dtlb_load:
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stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
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661: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
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retry
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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nop
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nop
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.previous
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/* For sun4v the ASI_DTLB_DATA_IN store and the retry
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* instruction get nop'd out and we get here to branch
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* to the sun4v tlb load code. The registers are setup
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* as follows:
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*
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* %g4: vaddr
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* %g5: PTE
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* %g6: TAG
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*
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* The sun4v TLB load wants the PTE in %g3 so we fix that
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* up here.
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*/
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ba,pt %xcc, sun4v_dtlb_load
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mov %g5, %g3
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kvmap_dtlb_nonlinear:
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/* Catch kernel NULL pointer derefs. */
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@ -185,10 +227,17 @@ kvmap_dtlb_longpath:
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nop
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.previous
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rdpr %tl, %g4
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cmp %g4, 1
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mov TLB_TAG_ACCESS, %g4
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rdpr %tl, %g3
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cmp %g3, 1
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661: mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_DMMU, %g5
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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mov %g4, %g5
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nop
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.previous
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be,pt %xcc, sparc64_realfault_common
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mov FAULT_CODE_DTLB, %g4
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ba,pt %xcc, winfix_trampoline
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@ -96,7 +96,7 @@ sun4v_dtlb_miss:
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/* Load UTSB reg into %g1. */
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mov SCRATCHPAD_UTSBREG1, %g1
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ldxa [%g1 + %g1] ASI_SCRATCHPAD, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g1
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LOAD_DTLB_INFO(%g2, %g4, %g5)
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COMPUTE_TAG_TARGET(%g6, %g4, %g5, %g3, kvmap_dtlb_4v)
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@ -149,14 +149,19 @@ sun4v_dtlb_prot:
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* SCRATCHPAD_MMU_MISS contents in %g2.
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*/
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sun4v_itsb_miss:
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ba,pt %xcc, sun4v_tsb_miss_common
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mov SCRATCHPAD_UTSBREG1, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g1
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brz,pn %g5, kvmap_itlb_4v
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mov FAULT_CODE_ITLB, %g3
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/* Called from trap table with TAG TARGET placed into
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* %g6 and SCRATCHPAD_UTSBREG1 contents in %g1.
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*/
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sun4v_dtsb_miss:
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mov FAULT_CODE_DTLB, %g3
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mov SCRATCHPAD_UTSBREG1, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g1
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brz,pn %g5, kvmap_dtlb_4v
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mov FAULT_CODE_DTLB, %g3
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/* Create TSB pointer into %g1. This is something like:
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*
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@ -312,7 +317,8 @@ sun4v_stdfmna:
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or %g2, %lo(OLD), %g2; \
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sub %g1, %g2, %g1; \
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sethi %hi(BRANCH_ALWAYS), %g3; \
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srl %g1, 2, %g1; \
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sll %g1, 11, %g1; \
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srl %g1, 11 + 2, %g1; \
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or %g3, %lo(BRANCH_ALWAYS), %g3; \
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or %g3, %g1, %g3; \
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stw %g3, [%g2]; \
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@ -186,19 +186,19 @@
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ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5; \
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srlx %g4, 22, %g7; \
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sllx %g5, 48, %g6; \
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brz,pn %g5, kvmap_itlb_4v; \
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ba,pt %xcc, sun4v_itsb_miss; \
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or %g6, %g7, %g6; \
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ba,a,pt %xcc, sun4v_itsb_miss;
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nop;
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#define SUN4V_DTSB_MISS \
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#define SUN4V_DTSB_MISS \
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ldxa [%g0] ASI_SCRATCHPAD, %g2; \
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ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4; \
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ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5; \
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srlx %g4, 22, %g7; \
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sllx %g5, 48, %g6; \
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brz,pn %g5, kvmap_dtlb_4v; \
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ba,pt %xcc, sun4v_dtsb_miss; \
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or %g6, %g7, %g6; \
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ba,a,pt %xcc, sun4v_dtsb_miss;
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nop;
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/* Before touching these macros, you owe it to yourself to go and
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* see how arch/sparc64/kernel/winfixup.S works... -DaveM
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