- Reorganize Tegra AFI/PHY/REFCLK/etc functions (Manikanta Maddireddy)
- Mask Tegra AFI_INTR in runtime suspend (Manikanta Maddireddy)
- Fix Tegra AFI/PCIe powerup sequence (Manikanta Maddireddy)
- Add Tegra124, Tegra132, Tegra210, and Tegra186 support for Gen2 link
speed (Manikanta Maddireddy)
- Advertise Tegra AER support (Manikanta Maddireddy)
- Program Tegra210 UPHY settings (Manikanta Maddireddy)
- Enable Tegra opportunistic UpdateFC and ACK (Manikanta Maddireddy)
- Disable Tegra AFI dynamic clock gating (Manikanta Maddireddy)
- Process Tegra pending DLL transactions before entering L1 or L2 to
prevent receiver errors (Manikanta Maddireddy)
- Enable Tegra xclk clock clamping in L1 (Manikanta Maddireddy)
- Increase Tegra deskew retry time (Manikanta Maddireddy)
- Work around Tegra hardware RAW erratum (Manikanta Maddireddy)
- Update Tegra210 flow control timer frequency (Manikanta Maddireddy)
- Work around Tegra Gen1/Gen2 link number negotiation issue (Manikanta
Maddireddy)
- Work around Tegra PLLE power down issue (Manikanta Maddireddy)
- Program Tegra20 to support cacheable upstream transactions (Manikanta
Maddireddy)
- Log Tegra PRSNT_SENSE_IRQ as debug, not err (Manikanta Maddireddy)
- Add register offset for third Root Port on Tegra186 and Tegra30
(Manikanta Maddireddy)
- Document Tegra PCIe DPD pinctrl property (Manikanta Maddireddy)
- Put Tegra PEX CLK & BIAS pads in DPD mode to reduce power usage when
powergated (Manikanta Maddireddy)
- Add generic DT binding for "reset-gpios" property (Manikanta
Maddireddy)
- Add Tegra support for GPIO-based PERST# (Manikanta Maddireddy)
- Enable Relaxed Ordering only for Tegra20 & Tegra30 (Vidya Sagar)
* remotes/lorenzo/pci/tegra:
PCI: tegra: Enable Relaxed Ordering only for Tegra20 & Tegra30
PCI: tegra: Change link retry log level to debug
PCI: tegra: Add support for GPIO based PERST#
PCI: Add DT binding for "reset-gpios" property
PCI: tegra: Put PEX CLK & BIAS pads in DPD mode
dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop
PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of SoC struct
PCI: tegra: Change PRSNT_SENSE IRQ log to debug
PCI: tegra: Program AFI_CACHE_BAR_{0,1}_{ST,SZ} registers only for Tegra20
PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal
PCI: tegra: Set target speed as Gen1 before starting LTSSM
PCI: tegra: Update flow control timer frequency in Tegra210
PCI: tegra: Add SW fixup for RAW violations
PCI: tegra: Increase the deskew retry time
PCI: tegra: Enable PCIe xclk clock clamping
PCI: tegra: Process pending DLL transactions before entering L1 or L2
PCI: tegra: Disable AFI dynamic clock gating
PCI: tegra: Enable opportunistic UpdateFC and ACK
PCI: tegra: Program UPHY electrical settings for Tegra210
PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability
PCI: tegra: Add PCIe Gen2 link speed support
PCI: tegra: Fix PCIe host power up sequence
PCI: tegra: Mask AFI_INTR in runtime suspend
PCI: tegra: Rearrange Tegra PCIe driver functions
PCI: tegra: Handle failure cases in tegra_pcie_power_on()
soc/tegra: pmc: Export tegra_powergate_power_on()
- Move qcom driver to bulk clock API (Bjorn Andersson)
- Add Qualcomm QCS404 PCIe controller support (Bjorn Andersson)
- Ensure Qualcomm PERST is asserted for at least 100ms (Niklas Cassel)
* remotes/lorenzo/pci/qcom:
PCI: qcom: Ensure that PERST is asserted for at least 100 ms
PCI: qcom: Add QCS404 PCIe controller support
dt-bindings: PCI: qcom: Add QCS404 to the binding
PCI: qcom: Use clk bulk API for 2.4.0 controllers
- DT binding schema examples are now validated against the schemas.
Various examples are fixed due to that.
- Sync dtc with upstream version v1.5.0-30-g702c1b6c0e73
- Initial schemas for networking bindings. This includes ethernet, phy
and mdio common bindings with several Allwinner and stmmac converted
to the schema.
- Conversion of more Arm top-level SoC/board bindings to DT schema
- Conversion of PSCI binding to DT schema
- Rework Arm CPU schema to coexist with other CPU schemas
- Add a bunch of missing vendor prefixes and new ones for SoChip,
Sipeed, Kontron, B&R Industrial Automation GmbH, and Espressif
- Add Mediatek UART RX wakeup support to binding
- Add reset to ST UART binding
- Remove some Linuxisms from the endianness common-properties.txt
binding
- Make the flattened DT read-only after init
- Ignore disabled reserved memory nodes
- Clean-up some dead code in FDT functions
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Merge tag 'devicetree-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull Devicetree updates from Rob Herring:
- DT binding schema examples are now validated against the schemas.
Various examples are fixed due to that.
- Sync dtc with upstream version v1.5.0-30-g702c1b6c0e73
- Initial schemas for networking bindings. This includes ethernet, phy
and mdio common bindings with several Allwinner and stmmac converted
to the schema.
- Conversion of more Arm top-level SoC/board bindings to DT schema
- Conversion of PSCI binding to DT schema
- Rework Arm CPU schema to coexist with other CPU schemas
- Add a bunch of missing vendor prefixes and new ones for SoChip,
Sipeed, Kontron, B&R Industrial Automation GmbH, and Espressif
- Add Mediatek UART RX wakeup support to binding
- Add reset to ST UART binding
- Remove some Linuxisms from the endianness common-properties.txt
binding
- Make the flattened DT read-only after init
- Ignore disabled reserved memory nodes
- Clean-up some dead code in FDT functions
* tag 'devicetree-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (56 commits)
dt-bindings: vendor-prefixes: add Sipeed
dt-bindings: vendor-prefixes: add SoChip
dt-bindings: 83xx-512x-pci: Drop cell-index property
dt-bindings: serial: add documentation for Rx in-band wakeup support
dt-bindings: arm: Convert RDA Micro board/soc bindings to json-schema
of: unittest: simplify getting the adapter of a client
of/fdt: pass early_init_dt_reserve_memory_arch() with bool type nomap
of/platform: Drop superfluous cast in of_device_make_bus_id()
dt-bindings: usb: ehci: Fix example warnings
dt-bindings: net: Use phy-mode instead of phy-connection-type
dt-bindings: simple-framebuffer: Add requirement for pipelines
dt-bindings: display: Fix simple-framebuffer example
dt-bindings: net: mdio: Add child nodes
dt-bindings: net: mdio: Add address and size cells
dt-bindings: net: mdio: Add a nodename pattern
dt-bindings: mtd: sunxi-nand: Drop 'maxItems' from child 'reg' property
dt-bindings: arm: Limit cpus schema to only check Arm 'cpu' nodes
dt-bindings: backlight: lm3630a: correct schema validation
dt-bindings: net: dwmac: Deprecate the PHY reset properties
dt-bindings: net: sun8i-emac: Convert the binding to a schemas
...
28eac2b74c ("powerpc/fsl: Remove cell-index from PCI nodes"),
and for now it is still not used, drop it from doc.
Cc: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave"
is not used in current code, and "apb_csr" is not used by some platforms.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
Add PCIe support for the RZ/G2M (a.k.a. R8A774A1).
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Mostly due to x86 and acpi conversion, several documentation
links are still pointing to the old file. Fix them.
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Reviewed-by: Wolfram Sang <wsa@the-dreams.de>
Reviewed-by: Sven Van Asbroeck <TheSven73@gmail.com>
Reviewed-by: Bhupesh Sharma <bhsharma@redhat.com>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
The Qualcomm QCS404 platform contains a PCIe controller, add this to the
Qualcomm PCI binding document. The controller is the same version as the
one used in IPQ4019, but the PHY part is described separately, hence the
difference in clocks and resets.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
- Move IRQ register address computation inside macros (Kishon Vijay
Abraham I)
- Separate legacy IRQ and MSI configuration (Kishon Vijay Abraham I)
- Use hwirq, not virq, to get MSI IRQ number offset (Kishon Vijay Abraham
I)
- Squash ks_pcie_handle_msi_irq() into ks_pcie_msi_irq_handler() (Kishon
Vijay Abraham I)
- Add dwc support for platforms with custom MSI controllers (Kishon Vijay
Abraham I)
- Add keystone-specific MSI controller (Kishon Vijay Abraham I)
- Remove dwc host_ops previously used for keystone-specific MSI (Kishon
Vijay Abraham I)
- Skip dwc default MSI init if platform has custom MSI controller (Kishon
Vijay Abraham I)
- Implement .start_link() and .stop_link() for keystone endpoint support
(Kishon Vijay Abraham I)
- Add keystone "reg-names" DT binding (Kishon Vijay Abraham I)
- Squash ks_pcie_dw_host_init() into ks_pcie_add_pcie_port() (Kishon
Vijay Abraham I)
- Get keystone register resources from DT by name, not index (Kishon
Vijay Abraham I)
- Get DT resources in .probe() to prepare for endpoint support (Kishon
Vijay Abraham I)
- Add "ti,syscon-pcie-mode" DT property for PCIe mode configuration
(Kishon Vijay Abraham I)
- Explicitly set keystone to host mode (Kishon Vijay Abraham I)
- Document DT "atu" reg-names requirement for DesignWare core >= 4.80
(Kishon Vijay Abraham I)
- Enable dwc iATU unroll for endpoint mode as well as host mode (Kishon
Vijay Abraham I)
- Add dwc "version" to identify core >= 4.80 for ATU programming (Kishon
Vijay Abraham I)
- Don't build ARM32-specific keystone code on ARM64 (Kishon Vijay Abraham
I)
- Add DT binding for keystone PCIe RC in AM654 SoC (Kishon Vijay Abraham
I)
- Add keystone support for AM654 SoC PCIe RC (Kishon Vijay Abraham I)
- Reset keystone PHYs before enabling them (Kishon Vijay Abraham I)
- Make of_pci_get_max_link_speed() available to endpoint drivers as well
as host drivers (Kishon Vijay Abraham I)
- Add keystone support for DT "max-link-speed" property (Kishon Vijay
Abraham I)
- Add endpoint library support for BAR buffer alignment (Kishon Vijay
Abraham I)
- Make all dw_pcie_ep_ops structs const (Kishon Vijay Abraham I)
- Fix fencepost error in dw_pcie_ep_find_capability() (Kishon Vijay
Abraham I)
- Add dwc hooks for dbi/dbi2 that share the same address space (Kishon
Vijay Abraham I)
- Add keystone support for TI AM654x in endpoint mode (Kishon Vijay
Abraham I)
- Configure designware endpoints to advertise smallest resizable BAR
(1MB) (Kishon Vijay Abraham I)
- Align designware endpoint ATU windows for raising MSIs (Kishon Vijay
Abraham I)
- Add endpoint test support for TI AM654x (Kishon Vijay Abraham I)
- Fix endpoint test test_reg_bar issue (Kishon Vijay Abraham I)
* remotes/lorenzo/pci/keystone:
misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test
misc: pci_endpoint_test: Add support to test PCI EP in AM654x
PCI: designware-ep: Use aligned ATU window for raising MSI interrupts
PCI: designware-ep: Configure Resizable BAR cap to advertise the smallest size
PCI: keystone: Add support for PCIe EP in AM654x Platforms
dt-bindings: PCI: Add PCI EP DT binding documentation for AM654
PCI: dwc: Add callbacks for accessing dbi2 address space
PCI: dwc: Fix dw_pcie_ep_find_capability() to return correct capability offset
PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops
PCI: endpoint: Add support to specify alignment for buffers allocated to BARs
PCI: keystone: Add support to set the max link speed from DT
PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers
PCI: keystone: Invoke phy_reset() API before enabling PHY
PCI: keystone: Add support for PCIe RC in AM654x Platforms
dt-bindings: PCI: Add PCI RC DT binding documentation for AM654
PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64
PCI: dwc: Fix ATU identification for designware version >= 4.80
PCI: dwc: Enable iATU unroll for endpoint too
dt-bindings: PCI: Document "atu" reg-names
PCI: keystone: Explicitly set the PCIe mode
dt-bindings: PCI: Add dt-binding to configure PCIe mode
PCI: keystone: Move resources initialization to prepare for EP support
PCI: keystone: Use platform_get_resource_byname() to get memory resources
PCI: keystone: Perform host initialization in a single function
dt-bindings: PCI: keystone: Add "reg-names" binding information
PCI: keystone: Cleanup error_irq configuration
PCI: keystone: Add start_link()/stop_link() dw_pcie_ops
PCI: dwc: Remove default MSI initialization for platform specific MSI chips
PCI: dwc: Remove Keystone specific dw_pcie_host_ops
PCI: keystone: Use Keystone specific msi_irq_chip
PCI: dwc: Add support to use non default msi_irq_chip
PCI: keystone: Cleanup ks_pcie_msi_irq_handler()
PCI: keystone: Use hwirq to get the MSI IRQ number offset
PCI: keystone: Add separate functions for configuring MSI and legacy interrupt
PCI: keystone: Cleanup interrupt related macros
# Conflicts:
# drivers/pci/controller/dwc/pcie-designware.h
Add devicetree binding documentation for PCIe in EP mode present in
AM654 SoC.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Add devicetree binding documentation for PCIe in RC mode present in
AM654 SoC.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Document "atu" reg-names required to get the register space for ATU in
Synopsys designware core version >= 4.80.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Add "ti,syscon-pcie-mode" dt-binding to hold phandle to the syscon
register that should be used to configure PCIe in RC mode or EP mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Provide a way for the firmware to tell the OS which devices are external to
the machine and therefore untrusted. The property can describe for example
Thunderbolt and other user-accessible ports, which should always have the
strongest IOMMU protection.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Grant Likely <grant.likely@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Add "reg-names" binding information in order for device tree node
to be populated with the correct register strings.
This will break old DT compatibility. However Keystone PCI has never
worked in upstream kernel due to lack of SERDES support, so, before
SERDES support is added, cleanup the Keystone PCI dt-bindings.
This new binding will also be used by PCI in AM654 platform.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
- Use memcpy_fromio()/memcpy_toio() instead of plain memcpy() in PCI
endpoint framework (Wen Yang)
- Add interface to discover supported endpoint features to replace a
bitfield that wasn't flexible enough (Kishon Vijay Abraham I)
- Implement the new supported-feature interface for designware-plat,
dra7xx, rockchip, cadence (Kishon Vijay Abraham I)
- Fix issues with 64-bit BAR in endpoints (Kishon Vijay Abraham I)
- Add layerscape endpoint mode support (Xiaowei Bao)
* remotes/lorenzo/pci/endpoint:
misc: pci_endpoint_test: Add the layerscape EP device support
PCI: layerscape: Add EP mode support
arm64: dts: Add the PCIE EP node in dts
dt-bindings: add DT binding for the layerscape PCIe controller with EP mode
PCI: endpoint: Remove features member in struct pci_epc
PCI: designware-plat: Remove setting epc->features in Designware plat EP driver
PCI: rockchip: Remove pci_epf_linkup() from Rockchip EP driver
PCI: cadence: Remove pci_epf_linkup() from Cadence EP driver
PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features
PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is 64Bit
PCI: pci-epf-test: Remove setting epf_bar flags in function driver
PCI: endpoint: Fix pci_epf_alloc_space() to set correct MEM TYPE flags
PCI: endpoint: Add helper to get first unreserved BAR
PCI: cadence: Populate ->get_features() cdns_pcie_epc_ops
PCI: rockchip: Populate ->get_features() dw_pcie_ep_ops
PCI: pci-dra7xx: Populate ->get_features() dw_pcie_ep_ops
PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops
PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_ops
PCI: endpoint: Add new pci_epc_ops to get EPC features
PCI: endpoint: functions: Use memcpy_fromio()/memcpy_toio()
- Add dra72x/dra74x/dra76x SoC compatible strings (Kishon Vijay
Abraham I)
- Enable x2 mode support for dra72x/dra74x/dra76x SoC (Kishon Vijay
Abraham I)
- Configure dra7xx PHY to PCIe mode (Kishon Vijay Abraham I)
- Simplify dwc (remove unnecessary header includes, name variables
consistently, reduce inverted logic, etc) (Gustavo Pimentel)
- Add i.MX8MQ support (Andrey Smirnov)
- Add message to help debug dwc MSI-X mask bit errors (Gustavo Pimentel)
- Work around imx7d PCIe PLL erratum (Trent Piepho)
- Don't assert qcom reset GPIO during probe (Bjorn Andersson)
- Skip dwc MSI init if MSIs have been disabled (Lucas Stach)
* remotes/lorenzo/pci/dwc:
PCI: dwc: skip MSI init if MSIs have been explicitly disabled
PCI: dwc: Remove superfluous shifting in definitions
PCI: dwc: Make use of GENMASK/FIELD_PREP
PCI: dwc: Make use of BIT() in constant definitions
PCI: dwc: Share code for dw_pcie_rd/wr_other_conf()
PCI: dwc: Make use of IS_ALIGNED()
PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQ
dt-bindings: imx6q-pcie: Add "pcie_aux" clock for imx8mq
PCI: qcom: Don't deassert reset GPIO during probe
PCI: imx: Add workaround for e10728, IMX7d PCIe PLL failure
ARM: dts: imx7d: Add node for PCIe PHY
dt-bindings: imx6q-pcie: Add description of imx7d pcie phy
PCI: dwc: Print debug error message when MSI-X entry control mask bit is set
PCI: imx6: Add support for i.MX8MQ
PCI: imx6: Convert DIRECT_SPEED_CHANGE quirk code to use a flag
PCI: imx6: Mark PHY functions as i.MX6 specific
PCI: imx6: Introduce drvdata
PCI: dwc: Replace bit rotation operation (1 << bit) with BIT(bit)
PCI: dwc: Improve code readability and simplify mask/unmask operations
PCI: dwc: Rename variable name from data to d on dw_pcie_irq_domain_free()
PCI: dwc: Rename variable name from data to d on dw_pci_msi_set_affinity()
PCI: dwc: Rename variable name from data to d on dw_pci_setup_msi_msg()
PCI: dwc: Rename variable name from data to d on dw_pci_bottom_mask/unmask()
PCI: dwc: Remove unnecessary header include (signal.h)
PCI: dwc: Remove unnecessary header include (of_gpio.h)
PCI: dwc: dra7xx: Invoke phy_set_mode() API to set PHY mode to PHY_MODE_PCIE
PCI: dwc: dra7xx: Enable x2 mode support for dra74x, dra76x and dra72x
dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7
dt-bindings: PCI: dra7xx: Add SoC specific compatible strings
Add support for altr,pcie-root-port-2.0.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Add the documentation for the Device Tree binding for the layerscape PCIe
controller with EP mode.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <minghuan.lian@nxp.com>
Reviewed-by: Zhiqiang Hou <zhiqiang.hou@nxp.com>
Reviewed-by: Rob Herring <robh+dt@kernel.org>
There is a separate PHY device with its own registers on imx7d. It's
currently unused, but a PCIe erratum on imx7d will require it for the
workaround.
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Add PCIe support for the RZ/G2E (a.k.a. R8A774C0).
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Add syscon properties required for configuring PCIe in x2 lane mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Add new compatible strings for dra74x SoC (also used by dra76x) and
dra72x. This can be used to perform SoC specific configuration
(like configuring PCIe in x2 lane mode).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
As usual, this is where the bulk of our changes end up landing each
merge window.
The individual updates are too many to enumerate, many many platforms
have seen additions of device descriptions such that they are
functionally more complete (in fact, this is often the bulk of updates
we see).
Instead I've mostly focused on highlighting the new platforms below as
they are introduced. Sometimes the introduction is of mostly a fragment,
that later gets filled in on later releases, and in some cases it's
near-complete platform support. The latter is more common for derivative
platforms that already has similar support in-tree.
Two SoCs are slight outliers from the usual range of additions. Allwinner
support for F1C100s, a quite old SoC (ARMv5-based) shipping in the
Lychee Pi Nano platform. At the other end is NXP Layerscape LX2160A,
a 16-core 2.2GHz Cortex-A72 SoC with a large amount of I/O aimed at
infrastructure/networking.
TI updates stick out in the diff stats too, in particular because they
have moved the description of their L4 on-chip interconnect to devicetree,
which opens up for removal of even more of their platform-specific
'hwmod' description tables over the next few releases.
SoCs:
- Qualcomm QCS404 (4x Cortex-A53)
- Allwinner T3 (rebranded R40) and f1c100s (armv5)
- NXP i.MX7ULP (1x Cortex-A7 + 1x Cortex-M4)
- NXP LS1028A (2x Cortex-A72), LX2160A (16x Cortex-A72)
New platforms:
- Rockchip: Gru Scarlet (RK3188 Tablet)
- Amlogic: Phicomm N1 (S905D), Libretech S805-AC
- Broadcom: Linksys EA6500 v2 Wi-Fi router (BCM4708)
- Qualcomm: QCS404 base platform and EVB
- Qualcomm: Remove of Arrow SD600
- PXA: First PXA3xx DT board: Raumfeld
- Aspeed: Facebook Backpack-CMM BMC
- Renesas iWave G20D-Q7 (RZ/G1N)
- Allwinner t3-cqa3t-bv3 (T3/R40) and Lichee Pi Nano (F1C100s)
- Allwinner Emlid Neutis N5, Mapleboard MP130
- Marvell Macchiatobin Single Shot (Armada 8040, no 10GbE)
- i.MX: mtrion emCON-MX6, imx6ul-pico-pi, imx7d-sdb-reva
- VF610: Liebherr's BK4 device, ZII SCU4 AIB board
- i.MX7D PICO Hobbit baseboard
- i.MX7ULP EVK board
- NXP LX2160AQDS and LX2160ARDB boards
Other:
- Coresight binding updates across the board
- CPU cooling maps updates across the board
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM Device-tree updates from Olof Johansson:
"As usual, this is where the bulk of our changes end up landing each
merge window.
The individual updates are too many to enumerate, many many platforms
have seen additions of device descriptions such that they are
functionally more complete (in fact, this is often the bulk of updates
we see).
Instead I've mostly focused on highlighting the new platforms below as
they are introduced. Sometimes the introduction is of mostly a
fragment, that later gets filled in on later releases, and in some
cases it's near-complete platform support. The latter is more common
for derivative platforms that already has similar support in-tree.
Two SoCs are slight outliers from the usual range of additions.
Allwinner support for F1C100s, a quite old SoC (ARMv5-based) shipping
in the Lychee Pi Nano platform. At the other end is NXP Layerscape
LX2160A, a 16-core 2.2GHz Cortex-A72 SoC with a large amount of I/O
aimed at infrastructure/networking.
TI updates stick out in the diff stats too, in particular because they
have moved the description of their L4 on-chip interconnect to
devicetree, which opens up for removal of even more of their
platform-specific 'hwmod' description tables over the next few
releases.
SoCs:
- Qualcomm QCS404 (4x Cortex-A53)
- Allwinner T3 (rebranded R40) and f1c100s (armv5)
- NXP i.MX7ULP (1x Cortex-A7 + 1x Cortex-M4)
- NXP LS1028A (2x Cortex-A72), LX2160A (16x Cortex-A72)
New platforms:
- Rockchip: Gru Scarlet (RK3188 Tablet)
- Amlogic: Phicomm N1 (S905D), Libretech S805-AC
- Broadcom: Linksys EA6500 v2 Wi-Fi router (BCM4708)
- Qualcomm: QCS404 base platform and EVB
- Qualcomm: Remove of Arrow SD600
- PXA: First PXA3xx DT board: Raumfeld
- Aspeed: Facebook Backpack-CMM BMC
- Renesas iWave G20D-Q7 (RZ/G1N)
- Allwinner t3-cqa3t-bv3 (T3/R40) and Lichee Pi Nano (F1C100s)
- Allwinner Emlid Neutis N5, Mapleboard MP130
- Marvell Macchiatobin Single Shot (Armada 8040, no 10GbE)
- i.MX: mtrion emCON-MX6, imx6ul-pico-pi, imx7d-sdb-reva
- VF610: Liebherr's BK4 device, ZII SCU4 AIB board
- i.MX7D PICO Hobbit baseboard
- i.MX7ULP EVK board
- NXP LX2160AQDS and LX2160ARDB boards
Other:
- Coresight binding updates across the board
- CPU cooling maps updates across the board"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (648 commits)
ARM: dts: suniv: Fix improper bindings include patch
ARM: dts: sunxi: Enable Broadcom-based Bluetooth for multiple boards
arm64: dts: allwinner: a64: bananapi-m64: Add Bluetooth device node
ARM: dts: suniv: Fix improper bindings include patch
arm64: dts: Add spi-[tx/rx]-bus-width for the FSL QSPI controller
arm64: dts: Remove unused properties from FSL QSPI driver nodes
ARM: dts: Add spi-[tx/rx]-bus-width for the FSL QSPI controller
ARM: dts: imx6sx-sdb: Fix the reg properties for the FSL QSPI nodes
ARM: dts: Remove unused properties from FSL QSPI driver nodes
arm64: dts: ti: k3-am654: Enable main domain McSPI0
arm64: dts: ti: k3-am654: Add McSPI DT nodes
arm64: dts: ti: k3-am654: Populate power-domain property for UART nodes
arm64: dts: ti: k3-am654-base-board: Enable ECAP PWM
arm64: dts: ti: k3-am65-main: Add ECAP PWM node
arm64: dts: ti: k3-am654-base-board: Add I2C nodes
arm64: dts: ti: am654-base-board: Add pinmux for main uart0
arm64: dts: ti: k3-am65: Add pinctrl regions
dt-bindings: pinctrl: k3: Introduce pinmux definitions
ARM: dts: exynos: Specify I2S assigned clocks in proper node
ARM: dts: exynos: Add missing CPUs in cooling maps for Odroid X2
...
Add DT bindings for PCIe controller implemented in UniPhier SoCs when
configured in Root Complex (host) mode. This controller is based on
the DesignWare PCIe core.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang <yue.wang@amlogic.com>
Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
The "num-lanes" property is not used, remove it.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Removed the compatible string "snps,dw-pcie", it is for the reference
platform driver for PCI RC IP Protoyping Kits based on the ARC SDP,
so it is not suitable for all platform with designware PCIe controller,
and platform vendors have themselves' drivers.
The compatible string "snsp,dw-pcie" was added by mistake and it's not
matched that time, but it is matched because PCIe drivers has been
collected recently.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The PCIe compatible string for LS1043A was lost, so add it.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Whilst making an unrelated change to some Documentation, Linus sayeth:
| Afaik, even in Britain, "whilst" is unusual and considered more
| formal, and "while" is the common word.
|
| [...]
|
| Can we just admit that we work with computers, and we don't need to
| use þe eald Englisc spelling of words that most of the world never
| uses?
dictionary.com refers to the word as "Chiefly British", which is
probably an undesirable attribute for technical documentation.
Replace all occurrences under Documentation/ with "while".
Cc: David Howells <dhowells@redhat.com>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michael Halcrow <mhalcrow@google.com>
Cc: Jonathan Corbet <corbet@lwn.net>
Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
The PCIe and PCIE_PHY blocks are in different power domains on imx6sx
and this needs to be described using multi-pd bindings.
This was not required until now because the power-domain of the PCIe
block (DISPLAY) was always on.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
- Quirk Keystone K2G to limit MRRS to 256 (Kishon Vijay Abraham I)
- Update Keystone to use MRRS quirk for host bridge instead of open
coding (Kishon Vijay Abraham I)
- Refactor Keystone link establishment (Kishon Vijay Abraham I)
- Simplify and speed up Keystone link training (Kishon Vijay Abraham I)
- Remove unused Keystone host_init argument (Kishon Vijay Abraham I)
- Merge Keystone driver files into one (Kishon Vijay Abraham I)
- Remove redundant Keystone platform_set_drvdata() (Kishon Vijay Abraham
I)
- Rename Keystone functions for uniformity (Kishon Vijay Abraham I)
- Add Keystone device control module DT binding (Kishon Vijay Abraham I)
- Use SYSCON API to get Keystone control module device IDs (Kishon Vijay
Abraham I)
- Clean up Keystone PHY handling (Kishon Vijay Abraham I)
- Use runtime PM APIs to enable Keystone clock (Kishon Vijay Abraham I)
- Clean up Keystone config space access checks (Kishon Vijay Abraham I)
- Get Keystone outbound window count from DT (Kishon Vijay Abraham I)
- Clean up Keystone outbound window configuration (Kishon Vijay Abraham
I)
- Clean up Keystone DBI setup (Kishon Vijay Abraham I)
- Clean up Keystone ks_pcie_link_up() (Kishon Vijay Abraham I)
- Fix Keystone IRQ status checking (Kishon Vijay Abraham I)
- Add debug messages for all Keystone errors (Kishon Vijay Abraham I)
- Clean up Keystone includes and macros (Kishon Vijay Abraham I)
* remotes/lorenzo/pci/keystone:
PCI: keystone: Cleanup macros defined in pci-keystone.c
PCI: keystone: Reorder header file in alphabetical order
PCI: keystone: Add debug error message for all errors
PCI: keystone: Use ERR_IRQ_STATUS instead of ERR_IRQ_STATUS_RAW to get interrupt status
PCI: keystone: Cleanup ks_pcie_link_up()
PCI: keystone: Cleanup set_dbi_mode() and get_dbi_mode()
PCI: keystone: Cleanup outbound window configuration
PCI: keystone: Get number of outbound windows from DT
PCI: keystone: Cleanup configuration space access
PCI: keystone: Invoke runtime PM APIs to enable clock
PCI: keystone: Cleanup PHY handling
PCI: keystone: Use SYSCON APIs to get device ID from control module
dt-bindings: PCI: keystone: Add bindings to get device control module
PCI: keystone: Use uniform function naming convention
PCI: keystone: Remove redundant platform_set_drvdata() invocation
PCI: keystone: Merge pci-keystone-dw.c and pci-keystone.c
PCI: keystone: Remove unused argument from ks_dw_pcie_host_init()
PCI: keystone: Do not initiate link training multiple times
PCI: keystone: Move dw_pcie_setup_rc() out of ks_pcie_establish_link()
PCI: keystone: Use quirk to set MRRS for PCI host bridge
PCI: keystone: Use quirk to limit MRRS for K2G
Add bindings to get device control module which has the device id and
vendor id to be configured in the keystone PCIe controller.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Add support for r8a7744. The Renesas RZ/G1N (R8A7744) PCIe controller
is identical to the R-Car Gen2 family.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
This is documented as "required" but won't be present in old dtbs.
These resets are also present on other imx chips but right now only
imx7d implements them through the reset controller subsystem.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Add internal PCI bridge support for r8a7744 SoC. The Renesas RZ/G1N
(R8A7744) internal PCI bridge is identical to the R-Car Gen2 family.
This doesn't change the driver, so it does nothing by itself. But it does
mean that checkpatch won't complain about a future patch that adds
"renesas,pci-r8a7744" to a DT, which helps ensure that shipped DTs use
documented compatibility strings.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Document the R-Car E3 (R8A77990) SoC in the R-Car PCIe bindings.
Signed-off-by: Tho Vu <tho.vu.wh@rvc.renesas.com>
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Phil Edworthy <phil.edworthy@renesas.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Cc: Simon Horman <horms+renesas@verge.net.au>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: linux-renesas-soc@vger.kernel.org
Update device tree binding documentation of TI's dra7xx PCI controller
for enabling unaligned mem access as applicable not just in EP mode but
in host mode as well.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
