When tegra-drm.ko is built as a module, these MODULE_DEVICE_TABLEs allow
the module to be auto-loaded since the module will match the devices
instantiated from device tree.
(Notes for stable: in 3.14+, just git rm any conflicting file, since they
are added in later kernels. For 3.13 and below, manual merging will be
needed)
Cc: <stable@vger.kernel.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Since the device will no longer be used, may as well keep it in reset to
potentially save some power and make sure it is in a clean state the
next time it's probed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra20 and Tegra30 both required the buffer line stride to be aligned
on 8 byte boundaries. Tegra114 and Tegra124 increased the alignment to
64 bytes. Introduce a parameter to specify the alignment requirements
for each display controller and round up the pitch of newly allocated
framebuffers appropriately.
Originally-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This change uses the value of bits-per-color from panel to remove one
more hardcoded value.
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Job submission currently relies on the fact that struct drm_tegra_reloc
and struct host1x_reloc are the same size and uses a simple call to the
copy_from_user() function to copy them to kernel space. This causes the
handle to be stored in the buffer object field, which then needs a cast
to a 32 bit integer to resolve it to a proper buffer object pointer and
store it back in the buffer object field.
On 64-bit architectures that will no longer work, since pointers are 64
bits wide whereas handles will remain 32 bits. This causes the sizes of
both structures to because different and copying will no longer work.
Fix this by adding a new function, host1x_reloc_get_user(), that copies
the structures field by field.
While at it, use substructures for the command and target buffers in
struct host1x_reloc for better readability. Also use unsized types to
make it more obvious that this isn't part of userspace ABI.
Signed-off-by: Thierry Reding <treding@nvidia.com>
This matches what other drivers do for equivalent IOCTLs.
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The DRM_TEGRA_GEM_SET_FLAGS IOCTL can be used to set the flags of a
buffer object after it has been allocated or imported. Flags associated
with a buffer object can be queried using the DRM_TEGRA_GEM_GET_FLAGS
IOCTL.
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Currently the tiling parameters of buffer objects can only be set at
allocation time, and only a single tiled mode is supported. This new
DRM_TEGRA_GEM_SET_TILING IOCTL allows more modes to be set and also
allows the tiling mode to be changed after the allocation. This will
enable the Tegra DRM driver to import buffers from a GPU and directly
scan them out by configuring the display controller appropriately.
To complement this, the DRM_TEGRA_GEM_GET_TILING IOCTL can query the
current tiling mode of a buffer object. This is necessary when importing
buffers via handle (as is done in Mesa for example) so that userspace
can determine the proper parameters for the 2D or 3D engines.
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra124 supports a block-linear mode in addition to the regular pitch
linear and tiled modes. Add support for these by moving the internal
representation into a structure rather than a simple flag.
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Handle the MIPI_DSI_CLOCK_NONCONTINUOUS flag and only set TX-only
clock behavior when this flag is present to allow panels requiring
continuous clock mode to operate with this driver.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
We should unlock before returning the error code.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit converts the PMC support code to a platform driver. Because
the boot process needs to call into this driver very early, also set up
a minimal environment via an early initcall.
Signed-off-by: Thierry Reding <treding@nvidia.com>
In order to not clutter the include/linux directory with SoC specific
headers, move the Tegra-specific headers out into a separate directory.
Signed-off-by: Thierry Reding <treding@nvidia.com>
This allows reservation objects to be used in dma-buf. it's required
for implementing polling support on the fences that belong to a dma-buf.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Acked-by: Mauro Carvalho Chehab <m.chehab@samsung.com> #drivers/media/v4l2-core/
Acked-by: Thomas Hellstrom <thellstrom@vmware.com> #drivers/gpu/drm/ttm
Acked-by: Sumit Semwal <sumit.semwal@linaro.org>
Acked-by: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net> #drivers/gpu/drm/armada/
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
A race condition currently exists on Tegra, where it can happen that a
monitor attached via HDMI isn't detected during the initial FB helper
setup, but the hotplug event happens too early to be processed by the
poll helpers because they haven't been initialized yet. This happens
because on some boards the HDMI driver can control the regulator that
supplies the +5V pin on the HDMI connector. Therefore depending on the
timing between the initialization of the HDMI driver and the rest of
DRM, it's possible that the monitor returns the hotplug signal right
within the window where we would miss it.
Unfortunately, drm_kms_helper_poll_init() will wreak havoc when called
before at least some parts of the FB helpers have been set up.
This commit fixes this by splitting out the minimum of initialization
required to make drm_kms_helper_poll_init() work into a separate
function that can be called early. It is then safe to move all of the
poll helper initialization to an earlier point in time (before the
HDMI output driver has a chance to enable the +5V supply). That way if
the hotplug signal is returned before the initial FB helper setup, the
monitor will be forcefully detected at that point, and if the hotplug
signal is returned after that it will be properly handled by the poll
helpers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
To implement hotplug detection in a race-free manner, drivers must call
drm_kms_helper_poll_init() before hotplug events can be triggered. Such
events can be triggered right after any of the encoders or connectors
are initialized. At the same time, if the drm_fb_helper_hotplug_event()
helper is used by a driver, then the poll helper requires some parts of
the FB helper to be initialized to prevent a crash.
At the same time, drm_fb_helper_init() requires information that is not
necessarily available at such an early stage (number of CRTCs and
connectors), so it cannot be used yet.
Add a new helper, drm_fb_helper_prepare(), that initializes the bare
minimum needed to allow drm_kms_helper_poll_init() to execute and any
subsequent hotplug events to be processed properly.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
There's no need for this to be modifiable. Make it const so that it can
be put into the .rodata section.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Introduce generic functions to register and unregister connectors. This
provides a common place to add and remove associated user space
interfaces.
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
Reviewed-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
According to the DP specification the disparity of the first symbol
should always be negative. It is therefore safe to assume that panels
will conform to that and therefore parameterizing this field should
never be necessary.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The number of HBLANK and VBLANK symbols can be computed at runtime so
that they can be set appropriately depending on the video mode and DP
link.
These values are used by the packet generation logic to determine how
many audio samples can be transferred during the blanking intervals.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The currently hardcoded link parameters don't work on all eDP panels, so
compute the parameters at runtime depending on the mode and panel type
to allow the driver to cope with a wider variety of panels.
Note that the number of bits per pixel of the panel is still hardcoded,
but this can be addressed in a separate patch.
This is largely based on a patch by Stéphane Marchesin but the algorithm
was largely rewritten to be more readable and concise.
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Lanes are powered up in decreasing order. Power them down in increasing
order for consistency.
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The comment above mentions link A/B but this isn't what the code does,
so let's fix that.
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The code currently rounds up the clock to the next MHZ, which is
rounding up a 69.5MHz clock to 70MHz on my machine. This in turn
prevents the display from syncing. Removing this rounding fixes eDP
for me.
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Other output drivers set up debugfs slightly differently. Bring the SOR
driver in line with those for consistency.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Removing only the root directory will fail when there are still files in
it. Instead of manually removing all files, remove the whole directory
recursively.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Doing so allows the hotplug events generated by the connector to be
properly handled by the DRM poll helpers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Calling the drm_helper_hpd_irq_event() helper can sleep, so instead of
invoking it directly from the interrupt handler, schedule a work queue
and run it from there.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable hardware cursor support on Tegra124. Earlier generations support
the hardware cursor to some degree as well, but not in a way that can be
generically exposed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The DRM core can now cope with drivers that don't have an associated
struct drm_bus, so the host1x implementation is no longer useful.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra124 is mostly backwards-compatible with Tegra114. However, Tegra124
supports a few more features (e.g. interlacing, ...). Introduce a new
compatible string and TMDS tables to cope with these differences.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Accessing the CRC debugfs file will hang the system if the SOR is not
enabled, so make sure that it is stays enabled until the CRC has been
read.
Signed-off-by: Thierry Reding <treding@nvidia.com>
In some cases the pixel clock used to not be correct, which is why it
had to be recomputed. It turns out that the reason why it wasn't correct
is that it was used wrongly. If used correctly there's not need for the
recomputation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The shift clock divider is highly dependent on the type of output, so
push computation of it down into the output drivers. The old code used
to work merely by accident.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Program the shift clock divider in tegra_crtc_setup_clk() since that's
where the divider is computed, so passing it around can be avoided.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Assert the DSI controller's reset when the driver is unloaded to reduce
power consumption and to put the controller into a known state for
subsequent driver reloads.
Signed-off-by: Thierry Reding <treding@nvidia.com>
To prevent the enable or disable operations to potentially be run
multiple times, add guards to return early when the output is already
in the targetted state.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The packet sequencer needs to be programmed depending on the video mode
of the attached peripheral. Add support for non-burst video modes with
sync events (as opposed to sync pulses) and select either sequence
depending on the video mode.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The DSI controllers are powered by a (typically 1.2V) regulator. Usually
this is always on, so there was no need to support enabling or disabling
it thus far. But in order not to consume any power when DSI is inactive,
give the driver a chance to enable or disable the supply as needed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
A bunch of registers are initialized to 0 upon during driver probe. It
turns out that none of these are actually needed, so they can simply be
dropped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The pixel format enumeration values used by the Tegra DSI controller
don't match those defined by the DSI framework. Make sure to convert
them to the internal format before writing it to the register.
Signed-off-by: Thierry Reding <treding@nvidia.com>
For some reason when the PW*_ENABLE and PM*_ENABLE fields are cleared
during disable, the HDMI output stops working properly. Resetting and
initializing doesn't help.
Comment out those accesses for now until it has been determined what to
do about them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Disable LVDS mode according to register documentation. It seems like
this has no effect on the operation of HDMI, but it's probably a good
idea to do this anyway.
Signed-off-by: Thierry Reding <treding@nvidia.com>
This reflects the power-up sequence as described in the documentation,
but it doesn't seem to be strictly necessary to get HDMI to work.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Clocks are never enabled or disabled in atomic context, so we can use
the clk_prepare_enable() and clk_disable_unprepare() helpers instead.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The generic Tegra output code already sets up the clocks properly, so
there's no need to do it again when the HDMI output is enabled.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Revert commit 18ebc0f404 "drm/tegra: hdmi: Enable VDD earlier for
hotplug/DDC" and instead add a new supply for the +5V pin on the HDMI
connector.
The vdd-supply property refers to the regulator that supplies the
AVDD_HDMI input on Tegra, rather than the +5V HDMI connector pin. This
was never a problem before, because all boards had that pin hooked up to
a regulator that was always on. Starting with Dalmore and continuing
with Venice2, the +5V pin is controllable via a GPIO. For reasons
unknown, the GPIO ended up as the controlling GPIO of the AVDD_HDMI
supply in the Dalmore and Venice2 DTS files. But that's not correct.
Instead, a separate supply must be introduced so that the +5V pin can be
controlled separately from the supplies that feed the HDMI block within
Tegra.
A new hdmi-supply property is introduced that takes the place of the
vdd-supply and vdd-supply is only enabled when HDMI is enabled rather
than all the time.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Setting the bits in this register is dependent on the output type driven
by the display controller. All output drivers already set these properly
so there is no need to do it here again.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The tegra_dc_format() and tegra_dc_setup_window() functions are only
used internally by the display controller driver. Move them upwards in
order to make them static and get rid of the function prototypes.
Signed-off-by: Thierry Reding <treding@nvidia.com>
V_DIRECTION is the name of the field in the documentation, so use that
for consistency. Also add the H_DIRECTION field for completeness.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The SOR allows the computation of a 32 bit CRC of the content that it
transmits. This functionality is exposed via debugfs and is useful to
verify proper operation of the SOR.
Signed-off-by: Thierry Reding <treding@nvidia.com>
YUYV is UYVY with swapped bytes. Luckily the Tegra DC hardware can swap
bytes during scan-out, so supporting YUYV is simply a matter of writing
the correct value to the byteswap register.
This patch modifies tegra_dc_format() to return the byte swap parameter
via an output parameter in addition to returning the pixel format. Many
other formats can potentially be supported in a similar way.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Remove extern keyword from function prototypes since it isn't needed and
drop an unnecessary forward declaration.
Signed-off-by: Thierry Reding <treding@nvidia.com>
All drm_fb_helper_restore_fbdev_mode() call sites, save one, do the same
locking. Simplify this into drm_fb_helper_restore_fbdev_mode_unlocked().
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This should avoid races between connector probing and HPD
irqs in the future, currently mode_config.mutex blocks this
possibility.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Next pull request, this time more of the drm de-midlayering work. The big
thing is that his patch series here removes everything from drm_bus except
the set_busid callback. Thierry has a few more patches on top of this to
make that one optional to.
With that we can ditch all the non-pci drm_bus implementations, which
Thierry has already done for the fake tegra host1x drm_bus.
Reviewed by Thierry, Laurent and David and now also survived some testing
on my intel boxes to make sure the irq fumble is fixed correctly ;-) The
last minute rebase was just to add the r-b tags from Thierry for the 2
patches I've redone.
* 'drm-init-cleanup' of git://people.freedesktop.org/~danvet/drm:
drm/<drivers>: don't set driver->dev_priv_size to 0
drm: Remove dev->kdriver
drm: remove drm_bus->get_name
drm: rip out dev->devname
drm: inline drm_pci_set_unique
drm: remove bus->get_irq implementations
drm: pass the irq explicitly to drm_irq_install
drm/irq: Look up the pci irq directly in the drm_control ioctl
drm/irq: track the irq installed in drm_irq_install in dev->irq
drm: rename dev->count_lock to dev->buf_lock
drm: Rip out totally bogus vga_switcheroo->can_switch locking
drm: kill drm_bus->bus_type
drm: remove drm_dev_to_irq from drivers
drm/irq: remove cargo-culted locking from irq_install/uninstall
drm/irq: drm_control is a legacy ioctl, so pci devices only
drm/pci: fold in irq_by_busid support
drm/irq: simplify irq checks in drm_wait_vblank
A single fix for some framebuffer reference counting fallout caused by
the primary plane helpers introduced in 3.15-rc1.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJTWQzGAAoJEN0jrNd/PrOhrkAP/2BQvFszaEeMlI1sb18DK9pm
tu3BNf+gB/ZvsMVok79KdeDHi73v5acwqDapDmCcHKS1JRpqbKMgzWDrXYg39WWi
0i+nyWt43ajXqO3/PvrDiqDRTwb4Ee/GdQMVVti6+VcSYlKSMqrcCsL2SStfiUIU
z6tL0WpEF5oKRHwfSKjFP3CRkSiElLbjKDk5Z/b1noZoahjdFrc54fWpK71+Tf5C
HZ7vsWJxgqip0CRtRqYer8auLSdHN7LhNBRVCGWbgSNHMuKp07U/9qktmBFgLtkO
gOGu6W7wLR8sgCmNpDv6ht5pvu3cGWKRCDTSmbF79CTCdc/Wb2rMs/JSeq4CJPcP
wZ+TwnUwNp+Qv2McTONp6wCZ/qpBBcZgymOVCt9bossKs03DMT4H7C5ypri8QrQM
40V8KEmYpiAcO5JN0oXUd4Q2n6NniZwCP4xt/U4cUXTjCqMAnLBozCji8ApDLegX
wmSz2+G0NGAcnJEK482PE+lxavOaWPyRg1y777VCfOSstqiSaukmrg4/xxrMdp+a
fDSZWLdVPqZUaUr5qWPl0Szbihw3brmMSCzubrP5dOtw8MUUHXIRGbBE5w2PH8tD
do4yvxPPO9W0iH6PW+rN4Z4ll+SS0EQwsohBPA0/Z2CAC+CrMAseBb/71/syocqA
JIY2cogdFI0Ynzp6t4xn
=uM53
-----END PGP SIGNATURE-----
Merge tag 'drm/tegra/for-3.15-rc3' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Fixes for v3.15-rc3
A single fix for some framebuffer reference counting fallout caused by
the primary plane helpers introduced in 3.15-rc1.
* tag 'drm/tegra/for-3.15-rc3' of git://anongit.freedesktop.org/tegra/linux:
drm/tegra: restrict plane loops to legacy planes
In Matt Ropers primary plane series a set of prep patches like
commit af2b653bfb
Author: Matt Roper <matthew.d.roper@intel.com>
Date: Tue Apr 1 15:22:32 2014 -0700
drm/i915: Restrict plane loops to only operate on overlay planes (v2)
ensured that all exisiting users of the mode_config->plane_list
wouldn't change behaviour. Unfortunately tegra seems to have fallen
through the cracks. Fix it.
This regression was introduced in
commit e13161af80
Author: Matt Roper <matthew.d.roper@intel.com>
Date: Tue Apr 1 15:22:38 2014 -0700
drm: Add drm_crtc_init_with_planes() (v2)
The result was that we've unref'ed the fb for the primary plane twice,
leading to a use-after free bug. This is because the drm core will
already set crtc->primary->fb to NULL and do the unref for us, and the
crtc disable hook is called by the drm crtc helpers for exactly this
case.
Aside: Now that the fbdev helpers clean up planes there's no longer a
need to do this in drivers. So this could probably be nuked entirely
in linux-next.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This was only ever used to pretty-print the irq driver name. And on
kms systems due to set_version bonghits we never set up the prettier
name, ever. Which make this a bit pointless.
Also, we can always dig out the driver-instance/irq relationship
through other means, so this isn't that useful. So just rip it out to
simplify the set_version/set_busid insanity a bit.
Also delete the temporary busname from drm_pci_set_busid, it's now
unused.
v2: Rebase on top of the new host1x drm_bus for tegra.
Reviewed-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Completely unused. Hooray, midlayer mistakes that didn't cause work to
undo!
v2: Rebase on top of the recent tegra changes which added a host1x drm
bus.
Reviewed-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Certain types of I2C-over-AUX transactions require that only the address
is transferred. Detect this by looking at the AUX message's size and set
the address-only bit appropriately.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Implement eDP support for Tegra124 and support the PRIME vmap()/vunmap()
operations.
A symbol that is required for upcoming V4L2 support is now exported by
the host1x driver.
Relicense drivers under the GPL v2 for consistency. One exception is the
public header file, which is relicensed under MIT to abide by the common
rule.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJTPlzgAAoJEN0jrNd/PrOhR2AQALMfTgwlcUb53NkYKyuotf1g
dcUeCXrYlOZQhEkTEBkp8rjU3kYHcLieQW5NFUpVKMy4VTvb1nXPB0VrEJjajtrx
coAzffIVzqhWOUz4iGHphoIhzfQ6xQTNCd8B2bT/4pdnHuHNt4A10blFfxlBYPwD
2hw4alTYpaNhsSso3dDB2ORSKZsCWlFC/bPJVA/yGtrXon/CR8Q9sGIqcEnKa6fp
gPfdxJChr2c5FeFIgQRnkt+MHOl+SgpkzxNXX5c5ffY6kt1HvKKJZfTv4cbOsSrn
7xPtgv0PKiiGtReRXZxZKB/xOGKJBCDM2oXfv02pMT5bCIRTzpmkWne3cuU2b2Mn
FN67ZBHCSPRiBcdHIc7pGwP8jIg21zZ/7IqWW9/4yAXksYV3Ii7TdQY3eL3PCrBP
3802ygJznKuVx2S1xLMI7z4DXV+44cLCCWzmglWEQPQfKFCVgTsmuLr8HiM1Tj1m
YvEibgL72ggDsInGF4nrwidEirvtRqHSn/qcD19p1gRORKxR8P7e9LUmWN/PHlkV
iKfcaMyWpHuCLcCyKC2b9iieAtLDz1Hsn9MiaQ7BcZUVVMAS6OVrrrm14Q5Wbi/Z
RxfF0hRjPDEXyrxo2LKrVLQbxeMhkmBfkc532YZCwSxoWvgScUfE73lB/kk68Iv2
c0WnbuHrH41dslXH4yPl
=LGu0
-----END PGP SIGNATURE-----
Merge tag 'drm/tegra/for-3.15-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v3.15-rc1
Implement eDP support for Tegra124 and support the PRIME vmap()/vunmap()
operations.
A symbol that is required for upcoming V4L2 support is now exported by
the host1x driver.
Relicense drivers under the GPL v2 for consistency. One exception is the
public header file, which is relicensed under MIT to abide by the common
rule.
* tag 'drm/tegra/for-3.15-rc1' of git://anongit.freedesktop.org/tegra/linux:
drm/tegra: Use standard GPL v2 license text
drm/tegra: Relicense under GPL v2
drm/tegra: Relicense public header under MIT
drm/tegra: Add eDP support
gpu: host1x: export host1x_syncpt_incr_max() function
drm/tegra: prime: Add vmap support
Use the more canonical and concise variant of the GPL v2 license text.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The majority of the code in this driver is licensed under the GPL v2, so
relicense the rest under GPL v2 as well for consistency.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add support for eDP functionality found on Tegra124 and later SoCs. Only
fast link training is currently supported.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Now that CRTC's have a primary plane, there's no need to track the
framebuffer in the CRTC. Replace all references to the CRTC fb with the
primary plane's fb.
This patch was generated by the Coccinelle semantic patching tool using
the following rules:
@@ struct drm_crtc C; @@
- (C).fb
+ C.primary->fb
@@ struct drm_crtc *C; @@
- (C)->fb
+ C->primary->fb
v3: Generate patch via coccinelle. Actual removal of crtc->fb has been
moved to a subsequent patch.
v2: Fixup several lingering crtc->fb instances that were missed in the
first patch iteration. [Rob Clark]
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJTJlUvAAoJEHm+PkMAQRiGOhYH/1I+Bc7N7Rjr6QQAtBIy0GPC
XMqSE/gpgxlvRneQbQsvTUlPnWRhgzLGendT9HFKawkaQ0UNuZdRVyBHGFmpuED8
RlbicVVuuEZabrxEnCd7UPvYvEyK5pLIFpCRs5B+ManB1qLki2Ar03ymH1NRxOde
edmPbSUFo2aONITrEBm7tqT3cShTmBaDGP/zU0TNDMNrpVVDbHZolSNu2z4xOTa5
GqAOEbluLQ6jP3yxWur/V3Lk3W7pB6TabfX4o6UZu0F3iFnJxRMIzHXrI3o4yLTj
HEwmB3npfc8DIUk4oik7RkN+aqxDcdg/rBLQD63+xxt6zCkP+0q16brC0R67qWE=
=n9Ml
-----END PGP SIGNATURE-----
Merge tag 'v3.14-rc7' into drm-next
Linux 3.14-rc7
Backmerge to help out Intel guys.
Lets not trick ourselves into thinking "drm_device" objects are not
ref-counted. That's just utterly stupid. We manage "drm_minor" objects on
each drm-device and each minor can have an unlimited number of open
handles. Each of these handles has the drm_minor (and thus the drm_device)
as private-data in the file-handle. Therefore, we may not destroy
"drm_device" until all these handles are closed.
It is *not* possible to reset all these pointers atomically and restrict
access to them, and this is *not* how this is done! Instead, we use
ref-counts to make sure the object is valid and not freed.
Note that we currently use "dev->open_count" for that, which is *exactly*
the same as a reference-count, just open coded. So this patch doesn't
change any semantics on DRM devices (well, this patch just introduces the
ref-count, anyway. Follow-up patches will replace open_count by it).
Also note that generic VFS revoke support could allow us to drop this
ref-count again. We could then just synchronously disable any fops->xy()
calls. However, this is not the case, yet, and no such patches are
in sight (and I seriously question the idea of dropping the ref-cnt
again).
Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Add guard to check whether RGB output is already enabled in the way it's
done for HDMI output. Fixes possible hang on trying to disable output twice
(first time during driver probe and second on fb registering).
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
These patches fix some issues caused by the DRM panel support from the
previous pull request and add two more panels (for the Toshiba AC100 as
well as the Seaboard and Ventana).
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJS4TK6AAoJEN0jrNd/PrOhwXoP/i09xa9CKOnpy8Ewdmgi5gBt
vnjzqjwmHzZRpNeWw2xvcqzv5kKgXkpPdMhNUjErlJTUC1S6uCf/Uj+ExppYYysW
7uxNjPQQc6jgX+0342MabKITeZyTk9iEWPqTDtHDP5O2vXi4XSaQTMm9HpWGe1qZ
1CTb0yJc1epXGJPutlqhJSZgKwzrs6Pm2Q/nsTdxpGPAoTQj9J0NebDaZwJmmFGi
qNyfI4DVBp1sj8AgtUkQQn9x5oLDpdvHKLPHsAWgHnNTKqRxY8C0EL+S2TYGa812
sx8jvZgjvBoPuwaOr4hcOx91OFdfOoKVap9D/corU+UjstF9lTd+PvAHzZMO5qte
yQhWmYFn1gGr/I9b9K/mAB98s83W7lMmSs/7HtiawvLtogZ/t8xvSp94R7X8SGd1
wYcw3NqzgDxrcpJjDOsLIw1Pa4PxXoChtV0SfiaEoVlGn5WSONS/8cKeNwbO6e9D
gKkd/zvCMsYqHt7p8zDizcQKi4W+8zYiZySOfLohZzhf0qaoQnnD5yirfiIpljqA
Ql40F4XP3OF3CliikcSwFhvrTUCLb08Ol0MV6FX1H1iMae0dgiFqtz7AihFTbKHZ
PQeskMgEemxhIqKEsH0JcpV3+YxLRlWy/3I+OO7QczsL0xKD30FQ9Xhsu9EFx8gu
jXVvMDldeefaVBuTdqCb
=NfNj
-----END PGP SIGNATURE-----
Merge tag 'drm/for-3.14-rc1-20140123' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v3.14-rc1 (update)
These patches fix some issues caused by the DRM panel support from the
previous pull request and add two more panels (for the Toshiba AC100 as
well as the Seaboard and Ventana).
* tag 'drm/for-3.14-rc1-20140123' of git://anongit.freedesktop.org/tegra/linux:
drm/tegra: Obtain head number from DT
drm/panel: update EDID BLOB in panel_simple_get_modes()
gpu: host1x: Remove unnecessary include
drm/tegra: Use proper data type
drm/tegra: Clarify how panel modes override others
drm/tegra: Fix possible CRTC mask for RGB outputs
drm/i915: Use drm_encoder_crtc_ok()
drm: Move drm_encoder_crtc_ok() to core
drm: provide a helper for the encoder possible_crtcs mask
drm/tegra: Don't check resource with devm_ioremap_resource()
drm/panel: Add support for Chunghwa CLAA101WA01A panel
drm/panel: Add support for Samsung LTN101NT05 panel
The head number of a given display controller is fixed in hardware and
required to program outputs appropriately. Relying on the driver probe
order to determine this number will not work, since that could yield a
situation where the second head was probed first and would be assigned
head number 0 instead of 1.
By explicitly specifying the head number in the device tree, it is no
longer necessary to rely on these assumptions. As a fallback, if the
property isn't available, derive the head number from the display
controller node's position in the device tree. That's somewhat more
reliable than the previous default but not a proper solution.
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
When a panel advertises one or more modes, they are used exclusively.
Other methods for obtaining the mode, such as DDC as used for HDMI or
binary EDID blobs embedded in the DT, are ignored. The panel drivers
should be providing this functionality if they want to expose it as
well.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The mask of possible CRTCs that an output (DRM encoder) can be attached
to is relative to the position within the DRM device's list of CRTCs.
Deferred probing can cause this to not match the pipe number associated
with a CRTC. Use the newly introduced drm_crtc_mask() to compute the
mask by looking up the proper index of the given CRTC in the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
devm_ioremap_resource() does sanity checks on the given resource. No
need to duplicate this in the driver.
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This series of changes brings DRM panel support as well as initial code
to register DSI hosts and peripherals and bind them to DSI drivers. The
panel and DSI code are both used by the simple panel driver.
The Tegra-specific changes build on top of this work to add support for
various panels found on Tegra boards. New drivers enable the DSI host
found on Tegra114 and a special hardware block that calibrates the pads
used for DSI and CSI. The host1x and the display controller drivers gain
basic Tegra124 support. To round of the new features, the DRM driver now
sports a very simple PRIME implementation.
In addition there are various improvements such as the host1x API being
exported so that client drivers (like the Tegra DRM driver) can be built
as modules. HDMI now does better power management and legacy FBDEV can
now be disabled via Kconfig (though it's still enabled by default). A
few sparse warnings have been squashed and various parts of the code
have become more robust.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJStLL5AAoJEN0jrNd/PrOhtD0QAJwhRTuEh8xCJ7pu1eK3TMh2
BYCD5UOiqnPAcDjJlTsiX0NaNQQ15+9uIjSIbbk36tfZ5cWbiP5yURYyMZp1HjvP
woGqsdI4eHVXswXNPMMIeTRrQKNMoQV82uvFAnE3QsfFwdkB+9p5tSUxnqXSuJ5U
ZKv1AL4FC0FdAnvugEz1lBzxqthoLm0mQ9xwkoYN2hT9ak1bnZUljfGYp2G/0xqM
RqhKgboZapL4Aul8lLIqqTCgo9XS3xN8Zo8F3WwyuOYJTgGZ6EK25H2bMvPBx0NO
fBNeacVd2jaCrELL6ZdsodKuu+TbHM82Sc6mZTA3YxN/E4tFUTfT++LQF7w505mA
PGHiZylwfDUPhGRRA8tYEz+OVQvT1FMhKEswlhDki0RJF5OHReQdrmBl0HfiUfmn
cQC9/WzGIqIP68tuuxOf8tdKHbAP1sOf7WgjFrBVX86hktN2Aq2f4dYtB7tf1c5O
1wTY+NPho8avscCycWdcqAtrgz2/KHBo4KvO7f9dqiTFa+A6KXdqe1dZaFrsPBjL
N4SizpY9VW7zJnmW9dIhb7qopVNw4g9OzCfH9dmpqrCnHpNFfmXYqDuppcSz7X5h
fWpXtA6iAEVIa5CE44liZWv/5SU8Mowrb8YbBgC/EoMWphDfnzporvcHe94GLNiy
O1iUYmI3mv48JKs30bYD
=lQsh
-----END PGP SIGNATURE-----
Merge tag 'drm/for-3.14-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v3.14-rc1
This series of changes brings DRM panel support as well as initial code
to register DSI hosts and peripherals and bind them to DSI drivers. The
panel and DSI code are both used by the simple panel driver.
The Tegra-specific changes build on top of this work to add support for
various panels found on Tegra boards. New drivers enable the DSI host
found on Tegra114 and a special hardware block that calibrates the pads
used for DSI and CSI. The host1x and the display controller drivers gain
basic Tegra124 support. To round of the new features, the DRM driver now
sports a very simple PRIME implementation.
In addition there are various improvements such as the host1x API being
exported so that client drivers (like the Tegra DRM driver) can be built
as modules. HDMI now does better power management and legacy FBDEV can
now be disabled via Kconfig (though it's still enabled by default). A
few sparse warnings have been squashed and various parts of the code
have become more robust.
* tag 'drm/for-3.14-rc1' of git://anongit.freedesktop.org/tegra/linux: (121 commits)
drm/tegra: fix compile w/ CONFIG_DYNAMIC_DEBUG
drm/tegra: Add PRIME support
drm/tegra: Relocate some output-specific code
drm/tegra: Add Tegra124 DC support
drm/tegra: Fix small leak on error in tegra_fb_alloc()
drm/tegra: Make legacy fbdev support optional
drm/tegra: Sort reverse-dependencies alphabetically
drm/tegra: Fix return value check
drm/tegra: Add DSI support
drm/tegra: Disable outputs for power-saving
drm/tegra: Track HDMI enable state
drm/tegra: Fix HDMI audio frequency typo
drm/tegra: Do not export tegra_bo_ops
drm/tegra: Remove spurious blank line
drm/tegra: Increase compile test coverage
drm/tegra: Allow the driver to be built as a module
gpu: host1x: Add Tegra124 support
gpu: host1x: clk_round_rate() can return a zero upon error
gpu: host1x: Fix build warnings
gpu: host1x: Increase compile test coverage
...
With CONFIG_DYNAMIC_DEBUG=y, the following compile error occurs:
drivers/gpu/drm/tegra/mipi-phy.c: In function ‘mipi_dphy_timing_validate’:
drivers/gpu/drm/tegra/mipi-phy.c:69:11: error: ‘EINVAL’ undeclared (first use in this function)
drivers/gpu/drm/tegra/mipi-phy.c:69:11: note: each undeclared identifier is reported only once for each function it appears in
Fix this by directly including the header that defines EINVAL.
Fixes: dec727399a ("drm/tegra: Add DSI support")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Implement very basic PRIME support. This currently only works with
buffers that are contiguous in memory and will refuse to import any
physically non-contiguous buffers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Some of the code in the CRTC's mode setting code is specific to the RGB
output or needs to be called slightly differently depending on the type
of output. Push that code down into the output drivers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra124 and later support interlacing, but the driver doesn't support
it yet. Make sure interlacing stays disabled on hardware that supports
it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
If we don't have enough memory for ->planes then we leak "fb".
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
A lot of the modern userspace is capable of working without the legacy
fbdev support. kmscon can be used as a replacement for the framebuffer
console, and KMS X drivers create their own framebuffers.
Most people don't have a system where all of this works yet, though, so
leave support enabled by default.
Signed-off-by: Thierry Reding <treding@nvidia.com>
In case of error, the devm_ioremap_resource() function returns ERR_PTR()
and never NULL. The NULL test in the return value check should therefore
be replaced with IS_ERR().
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit adds support for both DSI outputs found on Tegra. Only very
minimal functionality is implemented, so advanced features like ganged
mode won't work.
Due to the lack of other test hardware, some sections of the driver are
hardcoded to work with Dalmore.
Signed-off-by: Thierry Reding <treding@nvidia.com>
When an output is disabled, its DPMS mode is usually set to off. Instead
of only disabling the panel (if one is attached), turn the output off
entirely to save more power.
HDMI doesn't have any panels attached, so it previously didn't save any
power at all. With this commit, however, the complete HDMI interface
will be turned off, therefore allowing an attached monitor to go into a
standby mode.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The DRM core doesn't track enable and disable state of encoders and/or
connectors, so calls to the output's .enable() and .disable() are not
guaranteed to be balanced. Track the enable state internally so that
calls to regulator and clock frameworks remain balanced.
Signed-off-by: Thierry Reding <treding@nvidia.com>
These buffer object operations are never used outside of the GEM
implementation so there is no use in exporting them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
