Commit Graph

7 Commits

Author SHA1 Message Date
Roger Quadros
918ee0d21b usb: phy: omap-usb3: Don't use omap_get_control_dev()
omap_get_control_dev() is being deprecated as it doesn't support
multiple instances. As control device is present only from OMAP4
onwards which supports DT only, we use phandles to get the
reference to the control device.

As we don't support non-DT boot, we just bail out on probe
if device node is not present.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-10-03 15:47:31 -07:00
Roger Quadros
6cb9310a32 usb: phy: omap: Add new device types and remove omap_control_usb3_phy_power()
Add support for new device types and in the process rid of "ti,type"
device tree property. The correct type of device will be determined
from the compatible string instead.

Introduce a compatible string for each device type. At the moment
we support 4 types OTGHS, USB2, PIPE3 (e.g. USB3) and DRA7USB2.

Update DT binding information to reflect these changes.

Also get rid of omap_control_usb3_phy_power(). Just one function
i.e. omap_control_usb_phy_power() will now take care of all PHY types.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-10-03 15:47:30 -07:00
Sachin Kamat
1b97be8ce4 usb: phy: omap-usb3: Fix return value
The function returns a pointer. Hence return NULL instead of 0.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-09-17 11:05:30 -05:00
Roger Quadros
519c6013d3 usb: phy: omap-usb3: Improve DPLL parameter lookup code
Use a mapping table (dpll_map) to match the possible system clock rates
to the appropriate DPLL parameters.

Introduce a function "omap_usb3_get_dpll_params()" that will
return the matching DPLL parameters for the given clock rate.

Also, bail out on phy init if DPLL locking fails.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-07-29 13:58:09 +03:00
Ruchika Kharwar
690c70bab1 usb: phy: omap-usb3: fix dpll clock index
Correction of the omap_usb3_dpll_params array when the sys_clk_rate is
20MHz.

Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Signed-off-by: Ruchika Kharwar <ruchika@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-07-15 13:05:30 +03:00
Ruchika Kharwar
81fbf101f2 usb: phy: omap-usb3: updated dpll M,N values to support DRA7xx devices
Addition of the M and N recommended values for the USB3 PHY DPLL.
Sysclk for DRA7xx is 20MHz.

This yields:
Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz

Signed-off-by: Ruchika Kharwar <ruchika@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-06-01 00:22:49 +03:00
Felipe Balbi
94ae98433a usb: phy: rename all phy drivers to phy-$name-usb.c
this will make sure that we have sensible names
for all phy drivers. Current situation was already
quite bad with too generic names being used.

Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-03-18 11:18:08 +02:00