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usb: phy: omap-usb3: Improve DPLL parameter lookup code
Use a mapping table (dpll_map) to match the possible system clock rates to the appropriate DPLL parameters. Introduce a function "omap_usb3_get_dpll_params()" that will return the matching DPLL parameters for the given clock rate. Also, bail out on phy init if DPLL locking fails. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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@ -27,7 +27,6 @@
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#include <linux/delay.h>
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#include <linux/usb/omap_control_usb.h>
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#define NUM_SYS_CLKS 6
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#define PLL_STATUS 0x00000004
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#define PLL_GO 0x00000008
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#define PLL_CONFIGURATION1 0x0000000C
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@ -57,26 +56,32 @@
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*/
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# define PLL_IDLE_TIME 100;
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enum sys_clk_rate {
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CLK_RATE_UNDEFINED = -1,
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CLK_RATE_12MHZ,
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CLK_RATE_16MHZ,
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CLK_RATE_19MHZ,
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CLK_RATE_20MHZ,
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CLK_RATE_26MHZ,
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CLK_RATE_38MHZ
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struct usb_dpll_map {
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unsigned long rate;
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struct usb_dpll_params params;
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};
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static struct usb_dpll_params omap_usb3_dpll_params[NUM_SYS_CLKS] = {
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{1250, 5, 4, 20, 0}, /* 12 MHz */
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{3125, 20, 4, 20, 0}, /* 16.8 MHz */
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{1172, 8, 4, 20, 65537}, /* 19.2 MHz */
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{1000, 7, 4, 10, 0}, /* 20 MHz */
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{1250, 12, 4, 20, 0}, /* 26 MHz */
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{3125, 47, 4, 20, 92843}, /* 38.4 MHz */
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static struct usb_dpll_map dpll_map[] = {
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{12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
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{16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
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{19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
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{20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
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{26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
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{38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
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};
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static struct usb_dpll_params *omap_usb3_get_dpll_params(unsigned long rate)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(dpll_map); i++) {
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if (rate == dpll_map[i].rate)
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return &dpll_map[i].params;
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}
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return 0;
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}
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static int omap_usb3_suspend(struct usb_phy *x, int suspend)
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{
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struct omap_usb *phy = phy_to_omapusb(x);
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@ -116,26 +121,6 @@ static int omap_usb3_suspend(struct usb_phy *x, int suspend)
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return 0;
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}
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static inline enum sys_clk_rate __get_sys_clk_index(unsigned long rate)
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{
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switch (rate) {
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case 12000000:
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return CLK_RATE_12MHZ;
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case 16800000:
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return CLK_RATE_16MHZ;
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case 19200000:
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return CLK_RATE_19MHZ;
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case 20000000:
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return CLK_RATE_20MHZ;
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case 26000000:
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return CLK_RATE_26MHZ;
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case 38400000:
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return CLK_RATE_38MHZ;
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default:
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return CLK_RATE_UNDEFINED;
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}
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}
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static void omap_usb_dpll_relock(struct omap_usb *phy)
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{
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u32 val;
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@ -155,39 +140,39 @@ static int omap_usb_dpll_lock(struct omap_usb *phy)
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{
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u32 val;
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unsigned long rate;
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enum sys_clk_rate clk_index;
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struct usb_dpll_params *dpll_params;
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rate = clk_get_rate(phy->sys_clk);
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clk_index = __get_sys_clk_index(rate);
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if (clk_index == CLK_RATE_UNDEFINED) {
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pr_err("dpll cannot be locked for sys clk freq:%luHz\n", rate);
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rate = clk_get_rate(phy->sys_clk);
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dpll_params = omap_usb3_get_dpll_params(rate);
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if (!dpll_params) {
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dev_err(phy->dev,
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"No DPLL configuration for %lu Hz SYS CLK\n", rate);
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return -EINVAL;
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}
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val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
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val &= ~PLL_REGN_MASK;
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val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
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val |= dpll_params->n << PLL_REGN_SHIFT;
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omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
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val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
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val &= ~PLL_SELFREQDCO_MASK;
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val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
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val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
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omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
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val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
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val &= ~PLL_REGM_MASK;
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val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
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val |= dpll_params->m << PLL_REGM_SHIFT;
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omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
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val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
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val &= ~PLL_REGM_F_MASK;
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val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
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val |= dpll_params->mf << PLL_REGM_F_SHIFT;
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omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
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val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
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val &= ~PLL_SD_MASK;
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val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
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val |= dpll_params->sd << PLL_SD_SHIFT;
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omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
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omap_usb_dpll_relock(phy);
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@ -198,8 +183,12 @@ static int omap_usb_dpll_lock(struct omap_usb *phy)
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static int omap_usb3_init(struct usb_phy *x)
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{
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struct omap_usb *phy = phy_to_omapusb(x);
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int ret;
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ret = omap_usb_dpll_lock(phy);
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if (ret)
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return ret;
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omap_usb_dpll_lock(phy);
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omap_control_usb3_phy_power(phy->control_dev, 1);
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return 0;
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