Commit Graph

9 Commits

Author SHA1 Message Date
Rob Herring
a96cbb146a clk: Explicitly include correct DT includes
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.

Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # samsung
Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # versaclock5
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230718143156.1066339-1-robh@kernel.org
Acked-by: Abel Vesa <abel.vesa@linaro.org> #imx
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-07-19 13:13:16 -07:00
Konrad Dybcio
e88c533d8a clk: qcom: gcc-sm6115: Add missing PLL config properties
When the driver was ported upstream, PLL ctl register values were omitted.
Add them to ensure the PLLs are fully configured like we expect them to.

Fixes: cbe63bfdc5 ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Iskren Chernev <me@iskren.info>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230601-topic-alpha_ctl-v1-2-b6a932dfcf68@linaro.org
2023-06-13 16:15:04 -07:00
Konrad Dybcio
996c32b745 clk: qcom: gcc-sm6115: Mark RCGs shared where applicable
The vast majority of shared RCGs were not marked as such. Fix it.

Fixes: cbe63bfdc5 ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230404224719.909746-1-konrad.dybcio@linaro.org
2023-04-07 09:18:24 -07:00
Konrad Dybcio
85d4e6ea08 clk: qcom: gcc-sm6115: Use floor_ops for SDCC1/2 core clk
Just like in case of other SoCs change SDCC1/SDCC2 ops
to floor to avoid overclocking the controller.

Fixes: cbe63bfdc5 ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Iskren Chernev <me@iskren.info>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221209123910.178609-1-konrad.dybcio@linaro.org
2022-12-27 21:26:16 -06:00
Iskren Chernev
9e48f0519b clk: qcom: Merge alt alpha plls for qcm2260, sm6115
The qcom2260 and sm6115 GCC drivers use a common modified DEFAULT and
BRAMMO alpha pll offsets. Move these common offsets to the shared place
to avoid duplication. The new layouts have a suffix EVO similar to LUCID
and RIVIAN.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220830075620.974009-4-iskren.chernev@gmail.com
2022-09-26 22:18:14 -05:00
Iskren Chernev
65f1fa35aa clk: qcom: gcc-sm6115: Move alpha pll bramo overrides
sm6115 uses a modified default and bramo alpha pll offsets. Put them in
the same place for consistency.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220830075620.974009-3-iskren.chernev@gmail.com
2022-09-26 22:18:14 -05:00
Adam Skladowski
068a0605ef clk: qcom: gcc-sm6115: Override default Alpha PLL regs
The DEFAULT and BRAMMO PLL offsets are non-standard in downstream, but
currently only BRAMMO ones are overridden. Override DEFAULT ones too.

A very similar thing is happening in gcc-qcm2290 driver.

Fixes: cbe63bfdc5 ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115")
Signed-off-by: Adam Skladowski <a_skl39@protonmail.com>
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220830075620.974009-2-iskren.chernev@gmail.com
2022-09-26 22:18:14 -05:00
Shawn Guo
e41bdd1864 clk: qcom: gcc-sm6115: Fix offset for hlos1_vote_turing_mmu_tbu0_gdsc
It looks that the offset 0x7d060 is a copy & paste from above
hlos1_vote_turing_mmu_tbu1_gdsc.  Correct it to 0x7d07c as per
downstream kernel.

Fixes: cbe63bfdc5 ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115")
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210919022308.24046-1-shawn.guo@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13 10:43:39 -07:00
Iskren Chernev
cbe63bfdc5 clk: qcom: Add Global Clock controller (GCC) driver for SM6115
Add support for the global clock controller found on SM6115
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.

Based on CAF implementation. GDSCs ported from downstream DT.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Link: https://lore.kernel.org/r/20210805161107.1194521-3-iskren.chernev@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-08-28 20:54:21 -07:00